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drm/amd/pp: Add rv_read_arg_from_smc to smu backend function table
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
52911e0356
commit
88c1a70d58
3 changed files with 11 additions and 14 deletions
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@ -386,11 +386,11 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
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ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
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rv_read_arg_from_smc(hwmgr, &result);
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result = smum_get_argument(hwmgr);
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rv_data->gfx_min_freq_limit = result * 100;
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
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rv_read_arg_from_smc(hwmgr, &result);
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result = smum_get_argument(hwmgr);
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rv_data->gfx_max_freq_limit = result * 100;
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return 0;
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@ -726,7 +726,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
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switch (type) {
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case PP_SCLK:
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
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rv_read_arg_from_smc(hwmgr, &now);
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now = smum_get_argument(hwmgr);
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size += sprintf(buf + size, "0: %uMhz %s\n",
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data->gfx_min_freq_limit / 100,
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@ -739,7 +739,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
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break;
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case PP_MCLK:
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
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rv_read_arg_from_smc(hwmgr, &now);
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now = smum_get_argument(hwmgr);
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for (i = 0; i < mclk_table->count; i++)
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size += sprintf(buf + size, "%d: %uMhz %s\n",
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@ -971,14 +971,14 @@ static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
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switch (idx) {
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case AMDGPU_PP_SENSOR_GFX_SCLK:
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
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rv_read_arg_from_smc(hwmgr, &sclk);
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sclk = smum_get_argument(hwmgr);
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/* in units of 10KHZ */
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*((uint32_t *)value) = sclk * 100;
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*size = 4;
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break;
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case AMDGPU_PP_SENSOR_GFX_MCLK:
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
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rv_read_arg_from_smc(hwmgr, &mclk);
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mclk = smum_get_argument(hwmgr);
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/* in units of 10KHZ */
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*((uint32_t *)value) = mclk * 100;
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*size = 4;
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@ -72,16 +72,14 @@ int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
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return 0;
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}
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int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
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static int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr)
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{
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uint32_t reg;
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reg = soc15_get_register_offset(MP1_HWID, 0,
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mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
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*arg = cgs_read_register(hwmgr->device, reg);
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return 0;
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return cgs_read_register(hwmgr->device, reg);
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}
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int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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@ -190,8 +188,7 @@ static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr)
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rv_send_msg_to_smc(hwmgr,
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PPSMC_MSG_GetDriverIfVersion);
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rv_read_arg_from_smc(hwmgr,
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&smc_driver_if_version);
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smc_driver_if_version = rv_read_arg_from_smc(hwmgr);
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if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION) {
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pr_err("Attempt to read SMC IF Version Number Failed!\n");
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@ -253,7 +250,7 @@ static int rv_start_smu(struct pp_hwmgr *hwmgr)
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struct cgs_firmware_info info = {0};
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
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rv_read_arg_from_smc(hwmgr, &hwmgr->smu_version);
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hwmgr->smu_version = rv_read_arg_from_smc(hwmgr);
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info.version = hwmgr->smu_version >> 8;
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cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
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@ -330,6 +327,7 @@ const struct pp_smumgr_func rv_smu_funcs = {
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.send_msg_to_smc_with_parameter = &rv_send_msg_to_smc_with_parameter,
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.download_pptable_settings = NULL,
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.upload_pptable_settings = NULL,
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.get_argument = rv_read_arg_from_smc,
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};
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@ -50,7 +50,6 @@ struct rv_smumgr {
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struct smu_table_array smu_tables;
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};
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int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
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int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
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uint8_t *table, int16_t table_id);
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int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
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