From 88c80af75cd1b0b2de6a26851db4b3d91d8f9371 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 3 Aug 2023 16:27:34 +0530 Subject: [PATCH] dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs [ Upstream commit df873243b2398a082d34a006bebe0e0ed7538f5c ] Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by: Imran Shaik Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson Stable-dep-of: 06d71fa10f2e ("clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock") Signed-off-by: Sasha Levin --- Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml | 3 ++- include/dt-bindings/clock/qcom,qdu1000-gcc.h | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml index 767a9d03aa32..d712b1a87e25 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 maintainers: - - Melody Olvera + - Taniya Das + - Imran Shaik description: | Qualcomm global clock control module which supports the clocks, resets and diff --git a/include/dt-bindings/clock/qcom,qdu1000-gcc.h b/include/dt-bindings/clock/qcom,qdu1000-gcc.h index ddbc6b825e80..2fd36cbfddbb 100644 --- a/include/dt-bindings/clock/qcom,qdu1000-gcc.h +++ b/include/dt-bindings/clock/qcom,qdu1000-gcc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ /* - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H @@ -138,6 +138,8 @@ #define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 #define GCC_PCIE_0_PIPE_CLK_SRC 129 #define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 +#define GCC_GPLL1_OUT_EVEN 131 +#define GCC_DDRSS_ECPRI_GSI_CLK 132 /* GCC resets */ #define GCC_ECPRI_CC_BCR 0