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powerpc/xive: add OPAL extensions for the XIVE native exploitation support
The support for XIVE native exploitation mode in Linux/KVM needs a couple more OPAL calls to get and set the state of the XIVE internal structures being used by a sPAPR guest. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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8c2ffd9174
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5 changed files with 127 additions and 3 deletions
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@ -186,8 +186,8 @@
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#define OPAL_XIVE_FREE_IRQ 140
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#define OPAL_XIVE_SYNC 141
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#define OPAL_XIVE_DUMP 142
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#define OPAL_XIVE_RESERVED3 143
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#define OPAL_XIVE_RESERVED4 144
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#define OPAL_XIVE_GET_QUEUE_STATE 143
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#define OPAL_XIVE_SET_QUEUE_STATE 144
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#define OPAL_SIGNAL_SYSTEM_RESET 145
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#define OPAL_NPU_INIT_CONTEXT 146
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#define OPAL_NPU_DESTROY_CONTEXT 147
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@ -210,7 +210,8 @@
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#define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
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#define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
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#define OPAL_NX_COPROC_INIT 167
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#define OPAL_LAST 167
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#define OPAL_XIVE_GET_VP_STATE 170
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#define OPAL_LAST 170
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#define QUIESCE_HOLD 1 /* Spin all calls at entry */
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#define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */
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@ -279,6 +279,13 @@ int64_t opal_xive_allocate_irq(uint32_t chip_id);
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int64_t opal_xive_free_irq(uint32_t girq);
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int64_t opal_xive_sync(uint32_t type, uint32_t id);
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int64_t opal_xive_dump(uint32_t type, uint32_t id);
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int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
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__be32 *out_qtoggle,
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__be32 *out_qindex);
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int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
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uint32_t qtoggle,
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uint32_t qindex);
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int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
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int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,
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uint64_t desc, uint16_t pe_number);
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@ -109,12 +109,26 @@ extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
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extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
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extern void xive_native_sync_source(u32 hw_irq);
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extern void xive_native_sync_queue(u32 hw_irq);
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extern bool is_xive_irq(struct irq_chip *chip);
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extern int xive_native_enable_vp(u32 vp_id, bool single_escalation);
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extern int xive_native_disable_vp(u32 vp_id);
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extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
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extern bool xive_native_has_single_escalation(void);
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extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio,
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u64 *out_qpage,
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u64 *out_qsize,
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u64 *out_qeoi_page,
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u32 *out_escalate_irq,
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u64 *out_qflags);
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extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle,
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u32 *qindex);
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extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
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u32 qindex);
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extern int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
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#else
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static inline bool xive_enabled(void) { return false; }
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@ -260,6 +260,9 @@ OPAL_CALL(opal_xive_get_vp_info, OPAL_XIVE_GET_VP_INFO);
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OPAL_CALL(opal_xive_set_vp_info, OPAL_XIVE_SET_VP_INFO);
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OPAL_CALL(opal_xive_sync, OPAL_XIVE_SYNC);
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OPAL_CALL(opal_xive_dump, OPAL_XIVE_DUMP);
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OPAL_CALL(opal_xive_get_queue_state, OPAL_XIVE_GET_QUEUE_STATE);
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OPAL_CALL(opal_xive_set_queue_state, OPAL_XIVE_SET_QUEUE_STATE);
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OPAL_CALL(opal_xive_get_vp_state, OPAL_XIVE_GET_VP_STATE);
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OPAL_CALL(opal_signal_system_reset, OPAL_SIGNAL_SYSTEM_RESET);
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OPAL_CALL(opal_npu_init_context, OPAL_NPU_INIT_CONTEXT);
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OPAL_CALL(opal_npu_destroy_context, OPAL_NPU_DESTROY_CONTEXT);
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@ -437,6 +437,12 @@ void xive_native_sync_source(u32 hw_irq)
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}
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EXPORT_SYMBOL_GPL(xive_native_sync_source);
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void xive_native_sync_queue(u32 hw_irq)
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{
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opal_xive_sync(XIVE_SYNC_QUEUE, hw_irq);
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}
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EXPORT_SYMBOL_GPL(xive_native_sync_queue);
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static const struct xive_ops xive_native_ops = {
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.populate_irq_data = xive_native_populate_irq_data,
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.configure_irq = xive_native_configure_irq,
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@ -711,3 +717,96 @@ bool xive_native_has_single_escalation(void)
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return xive_has_single_esc;
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}
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EXPORT_SYMBOL_GPL(xive_native_has_single_escalation);
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int xive_native_get_queue_info(u32 vp_id, u32 prio,
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u64 *out_qpage,
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u64 *out_qsize,
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u64 *out_qeoi_page,
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u32 *out_escalate_irq,
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u64 *out_qflags)
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{
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__be64 qpage;
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__be64 qsize;
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__be64 qeoi_page;
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__be32 escalate_irq;
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__be64 qflags;
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s64 rc;
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rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize,
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&qeoi_page, &escalate_irq, &qflags);
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if (rc) {
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pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n",
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vp_id, prio, rc);
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return -EIO;
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}
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if (out_qpage)
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*out_qpage = be64_to_cpu(qpage);
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if (out_qsize)
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*out_qsize = be32_to_cpu(qsize);
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if (out_qeoi_page)
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*out_qeoi_page = be64_to_cpu(qeoi_page);
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if (out_escalate_irq)
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*out_escalate_irq = be32_to_cpu(escalate_irq);
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if (out_qflags)
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*out_qflags = be64_to_cpu(qflags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(xive_native_get_queue_info);
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int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex)
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{
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__be32 opal_qtoggle;
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__be32 opal_qindex;
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s64 rc;
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rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle,
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&opal_qindex);
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if (rc) {
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pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n",
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vp_id, prio, rc);
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return -EIO;
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}
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if (qtoggle)
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*qtoggle = be32_to_cpu(opal_qtoggle);
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if (qindex)
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*qindex = be32_to_cpu(opal_qindex);
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return 0;
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}
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EXPORT_SYMBOL_GPL(xive_native_get_queue_state);
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int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex)
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{
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s64 rc;
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rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex);
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if (rc) {
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pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n",
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vp_id, prio, rc);
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return -EIO;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(xive_native_set_queue_state);
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int xive_native_get_vp_state(u32 vp_id, u64 *out_state)
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{
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__be64 state;
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s64 rc;
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rc = opal_xive_get_vp_state(vp_id, &state);
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if (rc) {
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pr_err("OPAL failed to get vp state for VCPU %d : %lld\n",
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vp_id, rc);
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return -EIO;
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}
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if (out_state)
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*out_state = be64_to_cpu(state);
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return 0;
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}
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EXPORT_SYMBOL_GPL(xive_native_get_vp_state);
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