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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-28 03:40:04 +00:00
drm/i915: Move mi_set_context() into the legacy ringbuffer submission
The legacy i915_switch_context() is only applicable to the legacy ringbuffer submission method, so move it from the general i915_gem_context.c to intel_ringbuffer.c (rename pending!). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171123152631.31385-2-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
b1c24a6137
commit
8911a31c81
2 changed files with 185 additions and 199 deletions
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@ -567,204 +567,6 @@ void i915_gem_context_close(struct drm_file *file)
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idr_destroy(&file_priv->context_idr);
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}
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static inline int
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mi_set_context(struct drm_i915_gem_request *req, u32 flags)
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{
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struct drm_i915_private *dev_priv = req->i915;
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struct intel_engine_cs *engine = req->engine;
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enum intel_engine_id id;
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const int num_rings =
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/* Use an extended w/a on gen7 if signalling from other rings */
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(HAS_LEGACY_SEMAPHORES(dev_priv) && IS_GEN7(dev_priv)) ?
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INTEL_INFO(dev_priv)->num_rings - 1 :
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0;
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int len;
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u32 *cs;
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flags |= MI_MM_SPACE_GTT;
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if (IS_HASWELL(dev_priv))
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/* These flags are for resource streamer on HSW+ */
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flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
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else
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flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
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len = 4;
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if (IS_GEN7(dev_priv))
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len += 2 + (num_rings ? 4*num_rings + 6 : 0);
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cs = intel_ring_begin(req, len);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
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if (IS_GEN7(dev_priv)) {
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*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
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if (num_rings) {
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struct intel_engine_cs *signaller;
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*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
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for_each_engine(signaller, dev_priv, id) {
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if (signaller == engine)
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continue;
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*cs++ = i915_mmio_reg_offset(
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RING_PSMI_CTL(signaller->mmio_base));
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*cs++ = _MASKED_BIT_ENABLE(
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GEN6_PSMI_SLEEP_MSG_DISABLE);
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}
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}
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}
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*cs++ = MI_NOOP;
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*cs++ = MI_SET_CONTEXT;
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*cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
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/*
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* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
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* WaMiSetContext_Hang:snb,ivb,vlv
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*/
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*cs++ = MI_NOOP;
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if (IS_GEN7(dev_priv)) {
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if (num_rings) {
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struct intel_engine_cs *signaller;
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i915_reg_t last_reg = {}; /* keep gcc quiet */
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*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
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for_each_engine(signaller, dev_priv, id) {
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if (signaller == engine)
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continue;
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last_reg = RING_PSMI_CTL(signaller->mmio_base);
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*cs++ = i915_mmio_reg_offset(last_reg);
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*cs++ = _MASKED_BIT_DISABLE(
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GEN6_PSMI_SLEEP_MSG_DISABLE);
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}
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/* Insert a delay before the next switch! */
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = i915_mmio_reg_offset(last_reg);
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*cs++ = i915_ggtt_offset(engine->scratch);
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*cs++ = MI_NOOP;
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}
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*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
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}
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intel_ring_advance(req, cs);
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return 0;
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}
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static int remap_l3(struct drm_i915_gem_request *req, int slice)
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{
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u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
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int i;
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if (!remap_info)
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return 0;
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cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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/*
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* Note: We do not worry about the concurrent register cacheline hang
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* here because no other code should access these registers other than
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* at initialization time.
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*/
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*cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
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for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
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*cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
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*cs++ = remap_info[i];
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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return 0;
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}
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/**
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* i915_switch_context() - perform a GPU context switch.
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* @rq: request for which we'll execute the context switch
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*
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* The context life cycle is simple. The context refcount is incremented and
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* decremented by 1 on create and destroy. If the context is in use by the GPU,
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* it will have a refcount > 1. This allows us to destroy the context abstract
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* object while letting the normal object tracking destroy the backing BO.
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*
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* This function should not be used in execlists mode. Instead the context is
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* switched by writing to the ELSP and requests keep a reference to their
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* context.
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*/
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int i915_switch_context(struct drm_i915_gem_request *rq)
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{
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struct intel_engine_cs *engine = rq->engine;
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struct i915_gem_context *to_ctx = rq->ctx;
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struct i915_hw_ppgtt *to_mm =
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to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
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struct i915_gem_context *from_ctx = engine->legacy_active_context;
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struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt;
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u32 hw_flags = 0;
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int ret, i;
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lockdep_assert_held(&rq->i915->drm.struct_mutex);
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GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
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if (to_mm != from_mm ||
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(to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) {
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trace_switch_mm(engine, to_ctx);
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ret = to_mm->switch_mm(to_mm, rq);
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if (ret)
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goto err;
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to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
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engine->legacy_active_ppgtt = to_mm;
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hw_flags = MI_FORCE_RESTORE;
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}
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if (to_ctx->engine[engine->id].state &&
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(to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
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GEM_BUG_ON(engine->id != RCS);
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/*
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* The kernel context(s) is treated as pure scratch and is not
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* expected to retain any state (as we sacrifice it during
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* suspend and on resume it may be corrupted). This is ok,
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* as nothing actually executes using the kernel context; it
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* is purely used for flushing user contexts.
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*/
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if (i915_gem_context_is_kernel(to_ctx))
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hw_flags = MI_RESTORE_INHIBIT;
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ret = mi_set_context(rq, hw_flags);
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if (ret)
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goto err_mm;
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engine->legacy_active_context = to_ctx;
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}
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if (to_ctx->remap_slice) {
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for (i = 0; i < MAX_L3_SLICES; i++) {
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if (!(to_ctx->remap_slice & BIT(i)))
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continue;
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ret = remap_l3(rq, i);
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if (ret)
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goto err_ctx;
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}
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to_ctx->remap_slice = 0;
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}
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return 0;
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err_ctx:
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engine->legacy_active_context = from_ctx;
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err_mm:
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engine->legacy_active_ppgtt = from_mm;
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err:
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return ret;
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}
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static bool engine_has_idle_kernel_context(struct intel_engine_cs *engine)
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{
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struct i915_gem_timeline *timeline;
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@ -1385,6 +1385,190 @@ void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
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intel_ring_reset(engine->buffer, 0);
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}
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static inline int mi_set_context(struct drm_i915_gem_request *rq, u32 flags)
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{
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struct drm_i915_private *i915 = rq->i915;
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struct intel_engine_cs *engine = rq->engine;
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enum intel_engine_id id;
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const int num_rings =
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/* Use an extended w/a on gen7 if signalling from other rings */
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(HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
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INTEL_INFO(i915)->num_rings - 1 :
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0;
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int len;
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u32 *cs;
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flags |= MI_MM_SPACE_GTT;
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if (IS_HASWELL(i915))
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/* These flags are for resource streamer on HSW+ */
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flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
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else
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flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
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len = 4;
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if (IS_GEN7(i915))
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len += 2 + (num_rings ? 4*num_rings + 6 : 0);
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cs = intel_ring_begin(rq, len);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
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if (IS_GEN7(i915)) {
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*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
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if (num_rings) {
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struct intel_engine_cs *signaller;
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*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
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for_each_engine(signaller, i915, id) {
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if (signaller == engine)
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continue;
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*cs++ = i915_mmio_reg_offset(
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RING_PSMI_CTL(signaller->mmio_base));
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*cs++ = _MASKED_BIT_ENABLE(
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GEN6_PSMI_SLEEP_MSG_DISABLE);
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}
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}
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}
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*cs++ = MI_NOOP;
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*cs++ = MI_SET_CONTEXT;
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*cs++ = i915_ggtt_offset(rq->ctx->engine[RCS].state) | flags;
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/*
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* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
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* WaMiSetContext_Hang:snb,ivb,vlv
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*/
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*cs++ = MI_NOOP;
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if (IS_GEN7(i915)) {
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if (num_rings) {
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struct intel_engine_cs *signaller;
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i915_reg_t last_reg = {}; /* keep gcc quiet */
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*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
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for_each_engine(signaller, i915, id) {
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if (signaller == engine)
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continue;
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last_reg = RING_PSMI_CTL(signaller->mmio_base);
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*cs++ = i915_mmio_reg_offset(last_reg);
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*cs++ = _MASKED_BIT_DISABLE(
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GEN6_PSMI_SLEEP_MSG_DISABLE);
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}
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/* Insert a delay before the next switch! */
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*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
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*cs++ = i915_mmio_reg_offset(last_reg);
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*cs++ = i915_ggtt_offset(engine->scratch);
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*cs++ = MI_NOOP;
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}
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*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
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}
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intel_ring_advance(rq, cs);
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return 0;
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}
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static int remap_l3(struct drm_i915_gem_request *rq, int slice)
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{
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u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
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int i;
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if (!remap_info)
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return 0;
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cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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/*
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* Note: We do not worry about the concurrent register cacheline hang
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* here because no other code should access these registers other than
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* at initialization time.
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*/
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*cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
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for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
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*cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
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*cs++ = remap_info[i];
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(rq, cs);
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return 0;
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}
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static int switch_context(struct drm_i915_gem_request *rq)
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{
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struct intel_engine_cs *engine = rq->engine;
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struct i915_gem_context *to_ctx = rq->ctx;
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struct i915_hw_ppgtt *to_mm =
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to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
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struct i915_gem_context *from_ctx = engine->legacy_active_context;
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struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt;
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u32 hw_flags = 0;
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int ret, i;
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lockdep_assert_held(&rq->i915->drm.struct_mutex);
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GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
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if (to_mm != from_mm ||
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(to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) {
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trace_switch_mm(engine, to_ctx);
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ret = to_mm->switch_mm(to_mm, rq);
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if (ret)
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goto err;
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to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
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engine->legacy_active_ppgtt = to_mm;
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hw_flags = MI_FORCE_RESTORE;
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}
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if (to_ctx->engine[engine->id].state &&
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(to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
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GEM_BUG_ON(engine->id != RCS);
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/*
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* The kernel context(s) is treated as pure scratch and is not
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* expected to retain any state (as we sacrifice it during
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* suspend and on resume it may be corrupted). This is ok,
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* as nothing actually executes using the kernel context; it
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* is purely used for flushing user contexts.
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*/
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if (i915_gem_context_is_kernel(to_ctx))
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hw_flags = MI_RESTORE_INHIBIT;
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ret = mi_set_context(rq, hw_flags);
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if (ret)
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goto err_mm;
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engine->legacy_active_context = to_ctx;
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}
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if (to_ctx->remap_slice) {
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for (i = 0; i < MAX_L3_SLICES; i++) {
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if (!(to_ctx->remap_slice & BIT(i)))
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continue;
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ret = remap_l3(rq, i);
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if (ret)
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goto err_ctx;
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}
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to_ctx->remap_slice = 0;
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}
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return 0;
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err_ctx:
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engine->legacy_active_context = from_ctx;
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err_mm:
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engine->legacy_active_ppgtt = from_mm;
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err:
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return ret;
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}
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static int ring_request_alloc(struct drm_i915_gem_request *request)
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{
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int ret;
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@ -1401,7 +1585,7 @@ static int ring_request_alloc(struct drm_i915_gem_request *request)
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if (ret)
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return ret;
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ret = i915_switch_context(request);
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ret = switch_context(request);
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if (ret)
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return ret;
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