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clk: imx6sx: add mmdc1 ipg clock
i.MX6SX has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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acc4f98d44
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2 changed files with 3 additions and 1 deletions
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@ -431,6 +431,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18);
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clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18);
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clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
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clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
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clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
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clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
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clks[IMX6SX_CLK_MMDC_P1_IPG] = imx_clk_gate2("mmdc_p1_ipg", "ipg", base + 0x74, 26);
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clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2_flags("ocram", "ocram_podf", base + 0x74, 28, CLK_IS_CRITICAL);
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clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2_flags("ocram", "ocram_podf", base + 0x74, 28, CLK_IS_CRITICAL);
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/* CCGR4 */
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/* CCGR4 */
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@ -279,6 +279,7 @@
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#define IMX6SX_CLK_LVDS2_OUT 266
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#define IMX6SX_CLK_LVDS2_OUT 266
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#define IMX6SX_CLK_LVDS2_IN 267
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#define IMX6SX_CLK_LVDS2_IN 267
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#define IMX6SX_CLK_ANACLK2 268
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#define IMX6SX_CLK_ANACLK2 268
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#define IMX6SX_CLK_CLK_END 269
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#define IMX6SX_CLK_MMDC_P1_IPG 269
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#define IMX6SX_CLK_CLK_END 270
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#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
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#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
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