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PCI: uniphier-ep: Add NX1 support
Add basic support for UniPhier NX1 SoC as non-legacy SoC. This includes a compatible string, SoC-dependent data containing init() and wait() functions for the controller. Link: https://lore.kernel.org/r/1644480596-20037-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
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1 changed files with 81 additions and 0 deletions
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@ -10,6 +10,7 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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@ -31,6 +32,17 @@
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#define PCL_RSTCTRL2 0x0024
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#define PCL_RSTCTRL_PHY_RESET BIT(0)
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#define PCL_PINCTRL0 0x002c
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#define PCL_PERST_PLDN_REGEN BIT(12)
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#define PCL_PERST_NOE_REGEN BIT(11)
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#define PCL_PERST_OUT_REGEN BIT(8)
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#define PCL_PERST_PLDN_REGVAL BIT(4)
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#define PCL_PERST_NOE_REGVAL BIT(3)
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#define PCL_PERST_OUT_REGVAL BIT(0)
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#define PCL_PIPEMON 0x0044
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#define PCL_PCLK_ALIVE BIT(15)
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#define PCL_MODE 0x8000
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#define PCL_MODE_REGEN BIT(8)
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#define PCL_MODE_REGVAL BIT(0)
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@ -51,6 +63,9 @@
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#define PCL_APP_INTX 0x8074
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#define PCL_APP_INTX_SYS_INT BIT(0)
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#define PCL_APP_PM0 0x8078
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#define PCL_SYS_AUX_PWR_DET BIT(8)
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/* assertion time of INTx in usec */
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#define PCL_INTX_WIDTH_USEC 30
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@ -123,6 +138,55 @@ static void uniphier_pcie_pro5_init_ep(struct uniphier_pcie_ep_priv *priv)
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msleep(100);
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}
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static void uniphier_pcie_nx1_init_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 val;
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/* set EP mode */
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val = readl(priv->base + PCL_MODE);
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val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
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writel(val, priv->base + PCL_MODE);
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/* use auxiliary power detection */
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val = readl(priv->base + PCL_APP_PM0);
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val |= PCL_SYS_AUX_PWR_DET;
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writel(val, priv->base + PCL_APP_PM0);
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/* assert PERST# */
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val = readl(priv->base + PCL_PINCTRL0);
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val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
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| PCL_PERST_PLDN_REGVAL);
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val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
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| PCL_PERST_PLDN_REGEN;
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writel(val, priv->base + PCL_PINCTRL0);
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uniphier_pcie_ltssm_enable(priv, false);
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usleep_range(100000, 200000);
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/* deassert PERST# */
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val = readl(priv->base + PCL_PINCTRL0);
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val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
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writel(val, priv->base + PCL_PINCTRL0);
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}
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static int uniphier_pcie_nx1_wait_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 status;
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int ret;
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/* wait PIPE clock */
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ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
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status & PCL_PCLK_ALIVE, 100000, 1000000);
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if (ret) {
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dev_err(priv->pci.dev,
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"Failed to initialize controller in EP mode\n");
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return ret;
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}
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return 0;
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}
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static int uniphier_pcie_start_link(struct dw_pcie *pci)
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{
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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@ -353,11 +417,28 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
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},
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};
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static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
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.has_gio = false,
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.init = uniphier_pcie_nx1_init_ep,
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.wait = uniphier_pcie_nx1_wait_ep,
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.features = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = false,
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.align = 1 << 12,
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.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
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},
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};
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static const struct of_device_id uniphier_pcie_ep_match[] = {
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{
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.compatible = "socionext,uniphier-pro5-pcie-ep",
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.data = &uniphier_pro5_data,
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},
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{
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.compatible = "socionext,uniphier-nx1-pcie-ep",
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.data = &uniphier_nx1_data,
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},
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{ /* sentinel */ },
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};
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