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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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mvneta: implement SGMII-based in-band link state signaling
When MDIO bus is unavailable (common setup for SGMII), the in-band signaling must be used to correctly track link state. This patch enables the in-band status delivery for link state changes, namely: - link up/down - link speed - duplex full/half fixed_phy_update_state() is used to update phy status. CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Florian Fainelli <f.fainelli@gmail.com> CC: netdev@vger.kernel.org CC: linux-kernel@vger.kernel.org Signed-off-by: Stas Sergeev <stsp@users.sourceforge.net> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
a3bebdce41
commit
898b2970e2
1 changed files with 95 additions and 11 deletions
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@ -100,6 +100,8 @@
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#define MVNETA_TXQ_CMD 0x2448
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#define MVNETA_TXQ_DISABLE_SHIFT 8
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#define MVNETA_TXQ_ENABLE_MASK 0x000000ff
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#define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
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#define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
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#define MVNETA_ACC_MODE 0x2500
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#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
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#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
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@ -122,6 +124,7 @@
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#define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
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#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
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#define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
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#define MVNETA_MISCINTR_INTR_MASK BIT(31)
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#define MVNETA_INTR_OLD_CAUSE 0x25a8
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#define MVNETA_INTR_OLD_MASK 0x25ac
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@ -165,6 +168,7 @@
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#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
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#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
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#define MVNETA_GMAC_CTRL_2 0x2c08
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#define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
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#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
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#define MVNETA_GMAC2_PORT_RGMII BIT(4)
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#define MVNETA_GMAC2_PORT_RESET BIT(6)
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@ -180,9 +184,11 @@
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#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
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#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
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#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
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#define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
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#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
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#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
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#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
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#define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
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#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
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#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
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#define MVNETA_MIB_COUNTERS_BASE 0x3080
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@ -304,6 +310,7 @@ struct mvneta_port {
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unsigned int link;
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unsigned int duplex;
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unsigned int speed;
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int use_inband_status:1;
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};
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/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
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@ -994,6 +1001,20 @@ static void mvneta_defaults_set(struct mvneta_port *pp)
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val &= ~MVNETA_PHY_POLLING_ENABLE;
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mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
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if (pp->use_inband_status) {
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val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
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val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
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MVNETA_GMAC_FORCE_LINK_DOWN |
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MVNETA_GMAC_AN_FLOW_CTRL_EN);
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val |= MVNETA_GMAC_INBAND_AN_ENABLE |
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MVNETA_GMAC_AN_SPEED_EN |
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MVNETA_GMAC_AN_DUPLEX_EN;
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mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
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val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
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val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
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mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
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}
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mvneta_set_ucast_table(pp, -1);
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mvneta_set_special_mcast_table(pp, -1);
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mvneta_set_other_mcast_table(pp, -1);
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@ -2043,6 +2064,28 @@ static irqreturn_t mvneta_isr(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static int mvneta_fixed_link_update(struct mvneta_port *pp,
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struct phy_device *phy)
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{
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struct fixed_phy_status status;
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struct fixed_phy_status changed = {};
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u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
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status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
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if (gmac_stat & MVNETA_GMAC_SPEED_1000)
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status.speed = SPEED_1000;
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else if (gmac_stat & MVNETA_GMAC_SPEED_100)
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status.speed = SPEED_100;
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else
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status.speed = SPEED_10;
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status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
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changed.link = 1;
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changed.speed = 1;
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changed.duplex = 1;
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fixed_phy_update_state(phy, &status, &changed);
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return 0;
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}
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/* NAPI handler
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* Bits 0 - 7 of the causeRxTx register indicate that are transmitted
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* packets on the corresponding TXQ (Bit 0 is for TX queue 1).
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@ -2063,8 +2106,18 @@ static int mvneta_poll(struct napi_struct *napi, int budget)
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}
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/* Read cause register */
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cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
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(MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
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cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
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if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
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u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
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mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
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if (pp->use_inband_status && (cause_misc &
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(MVNETA_CAUSE_PHY_STATUS_CHANGE |
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MVNETA_CAUSE_LINK_CHANGE |
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MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
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mvneta_fixed_link_update(pp, pp->phy_dev);
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}
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}
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/* Release Tx descriptors */
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if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
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@ -2109,7 +2162,9 @@ static int mvneta_poll(struct napi_struct *napi, int budget)
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napi_complete(napi);
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local_irq_save(flags);
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mvreg_write(pp, MVNETA_INTR_NEW_MASK,
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MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
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MVNETA_RX_INTR_MASK(rxq_number) |
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MVNETA_TX_INTR_MASK(txq_number) |
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MVNETA_MISCINTR_INTR_MASK);
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local_irq_restore(flags);
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}
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@ -2373,7 +2428,13 @@ static void mvneta_start_dev(struct mvneta_port *pp)
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/* Unmask interrupts */
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mvreg_write(pp, MVNETA_INTR_NEW_MASK,
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MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
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MVNETA_RX_INTR_MASK(rxq_number) |
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MVNETA_TX_INTR_MASK(txq_number) |
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MVNETA_MISCINTR_INTR_MASK);
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mvreg_write(pp, MVNETA_INTR_MISC_MASK,
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MVNETA_CAUSE_PHY_STATUS_CHANGE |
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MVNETA_CAUSE_LINK_CHANGE |
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MVNETA_CAUSE_PSC_SYNC_CHANGE);
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phy_start(pp->phy_dev);
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netif_tx_start_all_queues(pp->dev);
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@ -2523,9 +2584,7 @@ static void mvneta_adjust_link(struct net_device *ndev)
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val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
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val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
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MVNETA_GMAC_CONFIG_GMII_SPEED |
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MVNETA_GMAC_CONFIG_FULL_DUPLEX |
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MVNETA_GMAC_AN_SPEED_EN |
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MVNETA_GMAC_AN_DUPLEX_EN);
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MVNETA_GMAC_CONFIG_FULL_DUPLEX);
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if (phydev->duplex)
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val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
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@ -2554,12 +2613,24 @@ static void mvneta_adjust_link(struct net_device *ndev)
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if (status_change) {
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if (phydev->link) {
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u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
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val |= (MVNETA_GMAC_FORCE_LINK_PASS |
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MVNETA_GMAC_FORCE_LINK_DOWN);
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mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
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if (!pp->use_inband_status) {
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u32 val = mvreg_read(pp,
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MVNETA_GMAC_AUTONEG_CONFIG);
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val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
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val |= MVNETA_GMAC_FORCE_LINK_PASS;
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mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
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val);
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}
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mvneta_port_up(pp);
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} else {
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if (!pp->use_inband_status) {
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u32 val = mvreg_read(pp,
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MVNETA_GMAC_AUTONEG_CONFIG);
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val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
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val |= MVNETA_GMAC_FORCE_LINK_DOWN;
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mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
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val);
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}
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mvneta_port_down(pp);
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}
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phy_print_status(phydev);
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@ -2910,6 +2981,9 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
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return -EINVAL;
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}
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if (pp->use_inband_status)
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ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE;
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/* Cancel Port Reset */
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ctrl &= ~MVNETA_GMAC2_PORT_RESET;
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mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
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@ -2934,6 +3008,7 @@ static int mvneta_probe(struct platform_device *pdev)
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char hw_mac_addr[ETH_ALEN];
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const char *mac_from;
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int phy_mode;
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int fixed_phy = 0;
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int err;
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/* Our multiqueue support is not complete, so for now, only
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@ -2967,6 +3042,7 @@ static int mvneta_probe(struct platform_device *pdev)
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dev_err(&pdev->dev, "cannot register fixed PHY\n");
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goto err_free_irq;
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}
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fixed_phy = 1;
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/* In the case of a fixed PHY, the DT node associated
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* to the PHY is the Ethernet MAC DT node.
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pp = netdev_priv(dev);
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pp->phy_node = phy_node;
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pp->phy_interface = phy_mode;
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pp->use_inband_status = (phy_mode == PHY_INTERFACE_MODE_SGMII) &&
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fixed_phy;
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pp->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pp->clk)) {
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platform_set_drvdata(pdev, pp->dev);
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if (pp->use_inband_status) {
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struct phy_device *phy = of_phy_find_device(dn);
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mvneta_fixed_link_update(pp, phy);
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}
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return 0;
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err_free_stats:
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