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ARM: dts: Group omap3 CM_FCLKEN_DSS clocks 

The clksel related registers on omap3 cause unique_unit_address and
node_name_chars_strict warnings with the W=1 or W=2 make flags enabled.

With the clock drivers updated, we can now avoid most of these warnings
by grouping the TI component clocks using the TI clksel binding, and
with the use of clock-output-names property to avoid non-standard node
names for the clocks.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2022-04-29 09:57:36 +03:00
parent 0019a9543a
commit 89953638a8
3 changed files with 56 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm/boot/dts/omap3430es1-clocks.dtsi
View File

@ -170,13 +170,20 @@
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};
dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
reg = <0x0e00>;
ti,set-rate-parent;
clock@e00 {
compatible = "ti,clksel";
reg = <0xe00>;
#clock-cells = <2>;
#address-cells = <0>;
dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "dss1_alwon_fck_3430es1";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
ti,set-rate-parent;
};
};
dss_ick: dss_ick_3430es1@e10 {

21
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
View File

@ -179,13 +179,20 @@
};
};
dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
reg = <0x0e00>;
ti,set-rate-parent;
clock@e00 {
compatible = "ti,clksel";
reg = <0xe00>;
#clock-cells = <2>;
#address-cells = <0>;
dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clock-output-names = "dss1_alwon_fck_3430es2";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
ti,set-rate-parent;
};
};
dss_ick: dss_ick_3430es2@e10 {

48
arch/arm/boot/dts/omap3xxx-clocks.dtsi
View File

@ -1022,28 +1022,36 @@
clock-div = <1>;
};
dss_tv_fck: dss_tv_fck@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&omap_54m_fck>;
reg = <0x0e00>;
ti,bit-shift = <2>;
};
/* CM_FCLKEN_DSS */
clock@e00 {
compatible = "ti,clksel";
reg = <0xe00>;
#clock-cells = <2>;
#address-cells = <0>;
dss_96m_fck: dss_96m_fck@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&omap_96m_fck>;
reg = <0x0e00>;
ti,bit-shift = <2>;
};
dss_tv_fck: clock-dss-tv-fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "dss_tv_fck";
clocks = <&omap_54m_fck>;
ti,bit-shift = <2>;
};
dss2_alwon_fck: dss2_alwon_fck@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
reg = <0x0e00>;
ti,bit-shift = <1>;
dss_96m_fck: clock-dss-96m-fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "dss_96m_fck";
clocks = <&omap_96m_fck>;
ti,bit-shift = <2>;
};
dss2_alwon_fck: clock-dss2-alwon-fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clock-output-names = "dss2_alwon_fck";
clocks = <&sys_ck>;
ti,bit-shift = <1>;
};
};
dummy_ck: dummy_ck {