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ARM: dts: Group omap3 CM_FCLKEN_DSS clocks
The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren <tony@atomide.com>
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parent
0019a9543a
commit
89953638a8
3 changed files with 56 additions and 34 deletions
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@ -170,13 +170,20 @@ usb_l4_ick: usb_l4_ick {
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clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
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};
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dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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ti,bit-shift = <0>;
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reg = <0x0e00>;
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ti,set-rate-parent;
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clock@e00 {
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compatible = "ti,clksel";
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reg = <0xe00>;
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#clock-cells = <2>;
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#address-cells = <0>;
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dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clock-output-names = "dss1_alwon_fck_3430es1";
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clocks = <&dpll4_m4x2_ck>;
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ti,bit-shift = <0>;
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ti,set-rate-parent;
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};
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};
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dss_ick: dss_ick_3430es1@e10 {
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@ -179,13 +179,20 @@ mmchs3_fck: clock-mmchs3-fck {
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};
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};
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dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
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#clock-cells = <0>;
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compatible = "ti,dss-gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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ti,bit-shift = <0>;
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reg = <0x0e00>;
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ti,set-rate-parent;
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clock@e00 {
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compatible = "ti,clksel";
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reg = <0xe00>;
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#clock-cells = <2>;
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#address-cells = <0>;
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dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
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#clock-cells = <0>;
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compatible = "ti,dss-gate-clock";
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clock-output-names = "dss1_alwon_fck_3430es2";
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clocks = <&dpll4_m4x2_ck>;
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ti,bit-shift = <0>;
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ti,set-rate-parent;
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};
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};
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dss_ick: dss_ick_3430es2@e10 {
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@ -1022,28 +1022,36 @@ core_l4_ick: core_l4_ick {
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clock-div = <1>;
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};
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dss_tv_fck: dss_tv_fck@e00 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&omap_54m_fck>;
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reg = <0x0e00>;
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ti,bit-shift = <2>;
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};
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/* CM_FCLKEN_DSS */
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clock@e00 {
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compatible = "ti,clksel";
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reg = <0xe00>;
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#clock-cells = <2>;
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#address-cells = <0>;
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dss_96m_fck: dss_96m_fck@e00 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&omap_96m_fck>;
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reg = <0x0e00>;
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ti,bit-shift = <2>;
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};
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dss_tv_fck: clock-dss-tv-fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clock-output-names = "dss_tv_fck";
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clocks = <&omap_54m_fck>;
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ti,bit-shift = <2>;
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};
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dss2_alwon_fck: dss2_alwon_fck@e00 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&sys_ck>;
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reg = <0x0e00>;
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ti,bit-shift = <1>;
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dss_96m_fck: clock-dss-96m-fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clock-output-names = "dss_96m_fck";
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clocks = <&omap_96m_fck>;
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ti,bit-shift = <2>;
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};
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dss2_alwon_fck: clock-dss2-alwon-fck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clock-output-names = "dss2_alwon_fck";
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clocks = <&sys_ck>;
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ti,bit-shift = <1>;
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};
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};
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dummy_ck: dummy_ck {
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