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ARM: remove zte zx platform 

The ZTE ZX set-top-box SoC platform was added in 2015 by Jun Nie, with
Baoyou Xie and Shawn Guo subsequently becoming maintainers after the
addition of the 64-bit variant.

However, the only machines that were ever supported upstream are the
reference designs, not actual set-top-box devices that would benefit
from this support. All ZTE set-top-boxes from the past few years seem
to be based on third-party SoCs. While there is very little information
about zx296702 and zx296718 on the web, I found some references to other
chips from the same family, such as zx296716 and zx296719, which were
never submitted for upstream support. Finally, there is no support for
the GPU on either of them, with the lima and panfrost device drivers
having been added after work on the zx platform had stopped.

Shawn confirmed that he has not seen any interest in this platform for
the past four years, and that it can be removed.

Thanks to Jun and Shawn for maintaining this platform over the past
five years.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-01-18 14:06:09 +01:00
parent f3a732843a
commit 89d4f98ae9
34 changed files with 1 additions and 2265 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
Documentation/devicetree/bindings/arm/zte,sysctrl.txt
View File

@ -1,30 +0,0 @@
ZTE sysctrl Registers
Registers for 'zte,zx296702' SoC:
System management required properties:
- compatible = "zte,sysctrl"
Low power management required properties:
- compatible = "zte,zx296702-pcu"
Bus matrix required properties:
- compatible = "zte,zx-bus-matrix"
Registers for 'zte,zx296718' SoC:
System management required properties:
- compatible = "zte,zx296718-aon-sysctrl"
- compatible = "zte,zx296718-sysctrl"
Example:
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};

28
Documentation/devicetree/bindings/arm/zte.yaml
View File

@ -1,28 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/zte.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ZTE platforms device tree bindings
maintainers:
- Jun Nie <jun.nie@linaro.org>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- zte,zx296702-ad1
- const: zte,zx296702
- items:
- enum:
- zte,zx296718-evb
- const: zte,zx296718
additionalProperties: true
...

20
Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
View File

@ -1,20 +0,0 @@
ZTE zx2967 SoCs Reset Controller
=======================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: should be one of the following.
* zte,zx296718-reset
- reg: physical base address of the controller and length of memory mapped
region.
- #reset-cells: must be 1.
example:
reset: reset-controller@1461060 {
compatible = "zte,zx296718-reset";
reg = <0x01461060 0x8>;
#reset-cells = <1>;
};

2
Documentation/devicetree/bindings/serial/pl011.yaml
View File

@ -19,7 +19,6 @@ select:
contains:
enum:
- arm,pl011
- zte,zx296702-uart
required:
- compatible
@ -30,7 +29,6 @@ properties:
- const: arm,pl011
- const: arm,primecell
- items:
- const: zte,zx296702-uart
- const: arm,primecell
reg:

19
Documentation/devicetree/bindings/soc/zte/pd-2967xx.txt
View File

@ -1,19 +0,0 @@
* ZTE zx2967 family Power Domains
zx2967 family includes support for multiple power domains which are used
to gate power to one or more peripherals on the processor.
Required Properties:
- compatible: should be one of the following.
* zte,zx296718-pcu - for zx296718 power domain.
- reg: physical base address of the controller and length of memory mapped
region.
- #power-domain-cells: Must be 1.
Example:
pcu_domain: pcu@117000 {
compatible = "zte,zx296718-pcu";
reg = <0x00117000 0x1000>;
#power-domain-cells = <1>;
};

42
MAINTAINERS
View File

@ -2704,40 +2704,6 @@ S: Maintained
F: arch/arm/mach-pxa/include/mach/z2.h
F: arch/arm/mach-pxa/z2.c
ARM/ZTE ARCHITECTURE
M: Jun Nie <jun.nie@linaro.org>
M: Shawn Guo <shawnguo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/zte.yaml
F: Documentation/devicetree/bindings/clock/zx2967*.txt
F: Documentation/devicetree/bindings/dma/zxdma.txt
F: Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
F: Documentation/devicetree/bindings/i2c/i2c-zx2967.txt
F: Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
F: Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
F: Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
F: Documentation/devicetree/bindings/soc/zte/
F: Documentation/devicetree/bindings/sound/zte,*.txt
F: Documentation/devicetree/bindings/thermal/zx2967-thermal.txt
F: Documentation/devicetree/bindings/watchdog/zte,zx2967-wdt.txt
F: arch/arm/boot/dts/zx2967*
F: arch/arm/mach-zx/
F: arch/arm64/boot/dts/zte/
F: drivers/clk/zte/
F: drivers/dma/zx_dma.c
F: drivers/gpio/gpio-zx.c
F: drivers/i2c/busses/i2c-zx2967.c
F: drivers/mmc/host/dw_mmc-zx.*
F: drivers/pinctrl/zte/
F: drivers/soc/zte/
F: drivers/thermal/zx2967_thermal.c
F: drivers/watchdog/zx2967_wdt.c
F: include/dt-bindings/clock/zx2967*.h
F: include/dt-bindings/soc/zte,*.h
F: sound/soc/codecs/zx_aud96p22.c
F: sound/soc/zte/
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@xilinx.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -6029,14 +5995,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/xlnx/
F: drivers/gpu/drm/xlnx/
DRM DRIVERS FOR ZTE ZX
M: Shawn Guo <shawnguo@kernel.org>
L: dri-devel@lists.freedesktop.org
S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/zte,vou.txt
F: drivers/gpu/drm/zte/
DRM PANEL DRIVERS
M: Thierry Reding <thierry.reding@gmail.com>
R: Sam Ravnborg <sam@ravnborg.org>

2
arch/arm/Kconfig
View File

@ -718,8 +718,6 @@ source "arch/arm/mach-vexpress/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-zx/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
# ARMv7-M architecture

14
arch/arm/Kconfig.debug
View File

@ -1353,18 +1353,6 @@ choice
This option selects UART0 on VIA/Wondermedia System-on-a-chip
devices, including VT8500, WM8505, WM8650 and WM8850.
config DEBUG_ZTE_ZX
bool "Use ZTE ZX UART"
select DEBUG_UART_PL01X
depends on ARCH_ZX
help
Say Y here if you are enabling ZTE ZX296702 SOC and need
debug uart support.
This option is preferred over the platform specific
options; the platform specific options are deprecated
and will be soon removed.
config DEBUG_ZYNQ_UART0
bool "Kernel low-level debugging on Xilinx Zynq using UART0"
depends on ARCH_ZYNQ
@ -1599,7 +1587,6 @@ config DEBUG_UART_PHYS
default 0x02531000 if DEBUG_KEYSTONE_UART1
default 0x03010fe0 if ARCH_RPC
default 0x07000000 if DEBUG_SUN9I_UART0
default 0x09405000 if DEBUG_ZTE_ZX
default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
DEBUG_VEXPRESS_UART0_CA9
default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
@ -1782,7 +1769,6 @@ config DEBUG_UART_VIRT
default 0xfb020000 if DEBUG_OMAP3UART3
default 0xfb042000 if DEBUG_OMAP3UART4
default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
default 0xfc705000 if DEBUG_ZTE_ZX
default 0xfcfe8600 if DEBUG_BCM63XX_UART
default 0xfd000000 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX
default 0xfd883000 if DEBUG_ALPINE_UART0

1
arch/arm/Makefile
View File

@ -220,7 +220,6 @@ machine-$(CONFIG_ARCH_U8500) += ux500
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
machine-$(CONFIG_ARCH_VT8500) += vt8500
machine-$(CONFIG_ARCH_ZX) += zx
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_PLAT_SPEAR) += spear

1
arch/arm/boot/dts/Makefile
View File

@ -1387,7 +1387,6 @@ dtb-$(CONFIG_ARCH_MSTARV7) += \
mstar-infinity2m-ssd202d-ssd201htv2.dtb \
mstar-infinity3-msc313e-breadbee.dtb \
mstar-mercury5-ssc8336n-midrived08.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-ast2600-evb.dtb \

48
arch/arm/boot/dts/zx296702-ad1.dts
View File

@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "zx296702.dtsi"
/ {
model = "ZTE ZX296702 AD1 Board";
compatible = "zte,zx296702-ad1", "zte,zx296702";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
memory {
device_type = "memory";
reg = <0x50000000 0x20000000>;
};
};
&mmc0 {
supports-highspeed;
non-removable;
disable-wp;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
&mmc1 {
supports-highspeed;
non-removable;
disable-wp;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
&uart0 {
status = "okay";
};

142
arch/arm/boot/dts/zx296702.dtsi
View File

@ -1,142 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/zx296702-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "zte,zx296702-smp";
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2cc>;
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2cc>;
reg = <1>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
matrix: bus-matrix@400000 {
compatible = "zte,zx-bus-matrix";
reg = <0x00400000 0x1000>;
};
intc: interrupt-controller@801000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00801000 0x1000>,
<0x00800100 0x100>;
};
global_timer: timer@8000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x00800200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
clocks = <&topclk ZX296702_A9_PERIPHCLK>;
};
l2cc: cache-controller@c00000 {
compatible = "arm,pl310-cache";
reg = <0x00c00000 0x1000>;
cache-unified;
cache-level = <2>;
arm,data-latency = <1 1 1>;
arm,tag-latency = <1 1 1>;
arm,double-linefill = <1>;
arm,double-linefill-incr = <0>;
};
pcu: pcu@a0008000 {
compatible = "zte,zx296702-pcu";
reg = <0xa0008000 0x1000>;
};
topclk: topclk@9800000 {
compatible = "zte,zx296702-topcrm-clk";
reg = <0x09800000 0x1000>;
#clock-cells = <1>;
};
lsp1clk: lsp1clk@9400000 {
compatible = "zte,zx296702-lsp1crpm-clk";
reg = <0x09400000 0x1000>;
#clock-cells = <1>;
};
lsp0clk: lsp0clk@b000000 {
compatible = "zte,zx296702-lsp0crpm-clk";
reg = <0x0b000000 0x1000>;
#clock-cells = <1>;
};
uart0: serial@9405000 {
compatible = "zte,zx296702-uart";
reg = <0x09405000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lsp1clk ZX296702_UART0_WCLK>;
status = "disabled";
};
uart1: serial@9406000 {
compatible = "zte,zx296702-uart";
reg = <0x09406000 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lsp1clk ZX296702_UART1_WCLK>;
status = "disabled";
};
mmc0: mmc@9408000 {
compatible = "snps,dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x09408000 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
clocks = <&lsp1clk ZX296702_SDMMC0_PCLK>,
<&lsp1clk ZX296702_SDMMC0_WCLK>;
clock-names = "biu", "ciu";
status = "disabled";
};
mmc1: mmc@b003000 {
compatible = "snps,dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0b003000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
clocks = <&lsp0clk ZX296702_SDMMC1_PCLK>,
<&lsp0clk ZX296702_SDMMC1_WCLK>;
clock-names = "biu", "ciu";
status = "disabled";
};
sysctrl: sysctrl@a0007000 {
compatible = "zte,sysctrl", "syscon";
reg = <0xa0007000 0x1000>;
};
};
};

122
arch/arm/configs/zx_defconfig
View File

@ -1,122 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_CGROUP_DEBUG=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_SCHED=y
CONFIG_RT_GROUP_SCHED=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_ZX=y
CONFIG_SOC_ZX296702=y
# CONFIG_SWP_EMULATE is not set
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_SMP=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_KSM=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HIBERNATION=y
CONFIG_PM_RUNTIME=y
CONFIG_PM_DEBUG=y
CONFIG_SUSPEND_TIME=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyAMA0,115200 debug earlyprintk root=/dev/ram rw rootwait"
#CONFIG_NET is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=192
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_UID_STAT=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_CHR_DEV_SCH=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_UEVENT=y
CONFIG_DM_VERITY=y
CONFIG_NETDEVICES=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO=y
CONFIG_SERIO_LIBPS2=y
CONFIG_SPI=y
CONFIG_LOGO=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_CONSOLE_POLL=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_DW=y
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_DEBUG=y
CONFIG_FUSE_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
#CONFIG_NFS_FS is not set
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_INFO=y
CONFIG_FRAME_WARN=4096
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_PANIC_TIMEOUT=5
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_RCU_CPU_STALL_TIMEOUT=60
# CONFIG_FTRACE is not set
CONFIG_KGDB=y
CONFIG_KGDB_KDB=y
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_PREEMPT=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_STACKTRACE=y
CONFIG_DEBUG_ZTE_ZX=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_LZO=y
CONFIG_GPIOLIB=y

21
arch/arm/mach-zx/Kconfig
View File

@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
menuconfig ARCH_ZX
bool "ZTE ZX family"
depends on ARCH_MULTI_V7
help
Support for ZTE ZX-based family of processors. TV
set-top-box processor is supported. More will be
added soon.
if ARCH_ZX
config SOC_ZX296702
def_bool y
select ARM_GIC
select ARM_GLOBAL_TIMER
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select PM_GENERIC_DOMAINS if PM
help
Support for ZTE ZX296702 SoC which is a dual core CortexA9MP
endif

3
arch/arm/mach-zx/Makefile
View File

@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_SOC_ZX296702) += zx296702.o zx296702-pm-domain.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o

16
arch/arm/mach-zx/core.h
View File

@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2014 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*/
#ifndef __MACH_ZX_CORE_H
#define __MACH_ZX_CORE_H
extern void zx_resume_jump(void);
extern size_t zx_suspend_iram_sz;
extern unsigned long zx_secondary_startup_pa;
void zx_secondary_startup(void);
#endif /* __MACH_ZX_CORE_H */

30
arch/arm/mach-zx/headsmp.S
View File

@ -1,30 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2014 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*/
#include <linux/linkage.h>
.align 3
.arm
/* It runs from physical address */
ENTRY(zx_resume_jump)
adr r1, zx_secondary_startup_pa
ldr r0, [r1]
bx r0
ENDPROC(zx_resume_jump)
ENTRY(zx_secondary_startup_pa)
.word zx_secondary_startup_pa
ENTRY(zx_suspend_iram_sz)
.word . - zx_resume_jump
ENDPROC(zx_secondary_startup_pa)
ENTRY(zx_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(zx_secondary_startup)

186
arch/arm/mach-zx/platsmp.c
View File

@ -1,186 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2014 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/fncpy.h>
#include <asm/proc-fns.h>
#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include "core.h"
#define AON_SYS_CTRL_RESERVED1 0xa8
#define BUS_MATRIX_REMAP_CONFIG 0x00
#define PCU_CPU0_CTRL 0x00
#define PCU_CPU1_CTRL 0x04
#define PCU_CPU1_ST 0x0c
#define PCU_GLOBAL_CTRL 0x14
#define PCU_EXPEND_CONTROL 0x34
#define ZX_IRAM_BASE 0x00200000
static void __iomem *pcu_base;
static void __iomem *matrix_base;
static void __iomem *scu_base;
void __init zx_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
unsigned long base = 0;
void __iomem *aonsysctrl_base;
void __iomem *sys_iram;
base = scu_a9_get_base();
scu_base = ioremap(base, SZ_256);
if (!scu_base) {
pr_err("%s: failed to map scu\n", __func__);
return;
}
scu_enable(scu_base);
np = of_find_compatible_node(NULL, NULL, "zte,sysctrl");
if (!np) {
pr_err("%s: failed to find sysctrl node\n", __func__);
return;
}
aonsysctrl_base = of_iomap(np, 0);
if (!aonsysctrl_base) {
pr_err("%s: failed to map aonsysctrl\n", __func__);
of_node_put(np);
return;
}
/*
* Write the address of secondary startup into the
* system-wide flags register. The BootMonitor waits
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(__pa_symbol(zx_secondary_startup),
aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
iounmap(aonsysctrl_base);
of_node_put(np);
np = of_find_compatible_node(NULL, NULL, "zte,zx296702-pcu");
pcu_base = of_iomap(np, 0);
of_node_put(np);
WARN_ON(!pcu_base);
np = of_find_compatible_node(NULL, NULL, "zte,zx-bus-matrix");
matrix_base = of_iomap(np, 0);
of_node_put(np);
WARN_ON(!matrix_base);
/* Map the first 4 KB IRAM for suspend usage */
sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false);
zx_secondary_startup_pa = __pa_symbol(zx_secondary_startup);
fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz);
}
static int zx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static bool first_boot = true;
if (first_boot) {
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
first_boot = false;
return 0;
}
/* Swap the base address mapping between IRAM and IROM */
writel_relaxed(0x1, matrix_base + BUS_MATRIX_REMAP_CONFIG);
/* Power on CPU1 */
writel_relaxed(0x0, pcu_base + PCU_CPU1_CTRL);
/* Wait for power on ack */
while (readl_relaxed(pcu_base + PCU_CPU1_ST) & 0x4)
cpu_relax();
/* Swap back the mapping of IRAM and IROM */
writel_relaxed(0x0, matrix_base + BUS_MATRIX_REMAP_CONFIG);
return 0;
}
#ifdef CONFIG_HOTPLUG_CPU
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
asm volatile(
"mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
/*
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, %3\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
static int zx_cpu_kill(unsigned int cpu)
{
unsigned long timeout = jiffies + msecs_to_jiffies(2000);
writel_relaxed(0x2, pcu_base + PCU_CPU1_CTRL);
while ((readl_relaxed(pcu_base + PCU_CPU1_ST) & 0x3) != 0x0) {
if (time_after(jiffies, timeout)) {
pr_err("*** cpu1 poweroff timeout\n");
break;
}
}
return 1;
}
static void zx_cpu_die(unsigned int cpu)
{
scu_power_mode(scu_base, SCU_PM_POWEROFF);
cpu_enter_lowpower();
while (1)
cpu_do_idle();
}
#endif
static void zx_secondary_init(unsigned int cpu)
{
scu_power_mode(scu_base, SCU_PM_NORMAL);
}
static const struct smp_operations zx_smp_ops __initconst = {
.smp_prepare_cpus = zx_smp_prepare_cpus,
.smp_secondary_init = zx_secondary_init,
.smp_boot_secondary = zx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = zx_cpu_kill,
.cpu_die = zx_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(zx_smp, "zte,zx296702-smp", &zx_smp_ops);

202
arch/arm/mach-zx/zx296702-pm-domain.c
View File

@ -1,202 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Linaro Ltd.
*
* Author: Jun Nie <jun.nie@linaro.org>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/slab.h>
#define PCU_DM_CLKEN 0x18
#define PCU_DM_RSTEN 0x1C
#define PCU_DM_ISOEN 0x20
#define PCU_DM_PWRDN 0x24
#define PCU_DM_ACK_SYNC 0x28
enum {
PCU_DM_NEON0 = 0,
PCU_DM_NEON1,
PCU_DM_GPU,
PCU_DM_DECPPU,
PCU_DM_VOU,
PCU_DM_R2D,
PCU_DM_TOP,
};
static void __iomem *pcubase;
struct zx_pm_domain {
struct generic_pm_domain dm;
unsigned int bit;
};
static int normal_power_off(struct generic_pm_domain *domain)
{
struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
unsigned long loop = 1000;
u32 tmp;
tmp = readl_relaxed(pcubase + PCU_DM_CLKEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp, pcubase + PCU_DM_CLKEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_ISOEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_ISOEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_RSTEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp, pcubase + PCU_DM_RSTEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_PWRDN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_PWRDN);
do {
tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit);
} while (--loop && !tmp);
if (!loop) {
pr_err("Error: %s %s fail\n", __func__, domain->name);
return -EIO;
}
return 0;
}
static int normal_power_on(struct generic_pm_domain *domain)
{
struct zx_pm_domain *zpd = (struct zx_pm_domain *)domain;
unsigned long loop = 10000;
u32 tmp;
tmp = readl_relaxed(pcubase + PCU_DM_PWRDN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp, pcubase + PCU_DM_PWRDN);
do {
tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit);
} while (--loop && tmp);
if (!loop) {
pr_err("Error: %s %s fail\n", __func__, domain->name);
return -EIO;
}
tmp = readl_relaxed(pcubase + PCU_DM_RSTEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_RSTEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_ISOEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp, pcubase + PCU_DM_ISOEN);
udelay(5);
tmp = readl_relaxed(pcubase + PCU_DM_CLKEN);
tmp &= ~BIT(zpd->bit);
writel_relaxed(tmp | BIT(zpd->bit), pcubase + PCU_DM_CLKEN);
udelay(5);
return 0;
}
static struct zx_pm_domain gpu_domain = {
.dm = {
.name = "gpu_domain",
.power_off = normal_power_off,
.power_on = normal_power_on,
},
.bit = PCU_DM_GPU,
};
static struct zx_pm_domain decppu_domain = {
.dm = {
.name = "decppu_domain",
.power_off = normal_power_off,
.power_on = normal_power_on,
},
.bit = PCU_DM_DECPPU,
};
static struct zx_pm_domain vou_domain = {
.dm = {
.name = "vou_domain",
.power_off = normal_power_off,
.power_on = normal_power_on,
},
.bit = PCU_DM_VOU,
};
static struct zx_pm_domain r2d_domain = {
.dm = {
.name = "r2d_domain",
.power_off = normal_power_off,
.power_on = normal_power_on,
},
.bit = PCU_DM_R2D,
};
static struct generic_pm_domain *zx296702_pm_domains[] = {
&vou_domain.dm,
&gpu_domain.dm,
&decppu_domain.dm,
&r2d_domain.dm,
};
static int zx296702_pd_probe(struct platform_device *pdev)
{
struct genpd_onecell_data *genpd_data;
struct resource *res;
int i;
genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL);
if (!genpd_data)
return -ENOMEM;
genpd_data->domains = zx296702_pm_domains;
genpd_data->num_domains = ARRAY_SIZE(zx296702_pm_domains);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "no memory resource defined\n");
return -ENODEV;
}
pcubase = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pcubase)) {
dev_err(&pdev->dev, "ioremap fail.\n");
return -EIO;
}
for (i = 0; i < ARRAY_SIZE(zx296702_pm_domains); ++i)
pm_genpd_init(zx296702_pm_domains[i], NULL, false);
of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data);
return 0;
}
static const struct of_device_id zx296702_pm_domain_matches[] __initconst = {
{ .compatible = "zte,zx296702-pcu", },
{ },
};
static struct platform_driver zx296702_pd_driver __initdata = {
.driver = {
.name = "zx-powerdomain",
.owner = THIS_MODULE,
.of_match_table = zx296702_pm_domain_matches,
},
.probe = zx296702_pd_probe,
};
static int __init zx296702_pd_init(void)
{
return platform_driver_register(&zx296702_pd_driver);
}
subsys_initcall(zx296702_pd_init);

22
arch/arm/mach-zx/zx296702.c
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2014 Linaro Ltd.
* Copyright (C) 2014 ZTE Corporation.
*/
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
static const char *const zx296702_dt_compat[] __initconst = {
"zte,zx296702",
NULL,
};
DT_MACHINE_START(ZX, "ZTE ZX296702 (Device Tree)")
.dt_compat = zx296702_dt_compat,
.l2c_aux_val = 0,
.l2c_aux_mask = ~0,
MACHINE_END

6
arch/arm64/Kconfig.platforms
View File

@ -317,12 +317,6 @@ config ARCH_XGENE
help
This enables support for AppliedMicro X-Gene SOC Family
config ARCH_ZX
bool "ZTE ZX SoC Family"
select PINCTRL
help
This enables support for ZTE ZX SoC Family
config ARCH_ZYNQMP
bool "Xilinx ZynqMP Family"
help

1
arch/arm64/boot/dts/Makefile
View File

@ -29,4 +29,3 @@ subdir-y += synaptics
subdir-y += ti
subdir-y += toshiba
subdir-y += xilinx
subdir-y += zte

3
arch/arm64/boot/dts/zte/Makefile
View File

@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296718-pcbox.dtb

144
arch/arm64/boot/dts/zte/zx296718-evb.dts
View File

@ -1,144 +0,0 @@
/*
* Copyright 2016 ZTE Corporation.
* Copyright 2016 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "zx296718.dtsi"
/ {
model = "ZTE zx296718 evaluation board";
compatible = "zte,zx296718-evb", "zte,zx296718";
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
sound-spdif0 {
compatible = "audio-graph-card";
dais = <&spdif0_port>;
};
sound-i2s0 {
compatible = "audio-graph-card";
dais = <&i2s0_port>;
pinctrl-names = "default";
pinctrl-0 = <&amplifier_pins>;
pa-gpios = <&bgpio4 0 GPIO_ACTIVE_HIGH>;
widgets = "Line", "Line Out Jack";
routing = "Amplifier", "LINEOUTL",
"Amplifier", "LINEOUTR",
"Line Out Jack", "Amplifier";
};
};
&aud96p22 {
port {
aud96p22_endpoint: endpoint {
remote-endpoint = <&i2s0_endpoint>;
};
};
};
&emmc {
status = "okay";
};
&hdmi {
status = "okay";
port {
hdmi_endpoint: endpoint {
remote-endpoint = <&spdif0_endpoint>;
};
};
};
&i2c0 {
status = "okay";
};
&i2s0 {
status = "okay";
i2s0_port: port {
i2s0_endpoint: endpoint {
remote-endpoint = <&aud96p22_endpoint>;
dai-format = "i2s";
frame-master;
bitclock-master;
};
};
};
&pmm {
amplifier_pins: amplifier {
pins = "TSI3_DATA";
function = "BGPIO";
};
};
&sd1 {
status = "okay";
};
&spdif0 {
status = "okay";
spdif0_port: port {
spdif0_endpoint: endpoint {
remote-endpoint = <&hdmi_endpoint>;
};
};
};
&tvenc {
status = "okay";
};
&uart0 {
status = "okay";
};

143
arch/arm64/boot/dts/zte/zx296718-pcbox.dts
View File

@ -1,143 +0,0 @@
/*
* Copyright (C) 2017 Sanechips Technology Co., Ltd.
* Copyright 2017 Linaro Ltd.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "zx296718.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "ZTE ZX296718 PCBOX Board";
compatible = "zte,zx296718-pcbox", "zte,zx296718";
chosen {
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
a53_vdd0v9: regulator-a53 {
compatible = "pwm-regulator";
pwms = <&pwm 3 1250 PWM_POLARITY_INVERTED>;
regulator-name = "A53_VDD0V9";
regulator-min-microvolt = <855000>;
regulator-max-microvolt = <1183000>;
pwm-dutycycle-unit = <100>;
pwm-dutycycle-range = <0 100>;
regulator-always-on;
regulator-boot-on;
};
sound-spdif0 {
compatible = "audio-graph-card";
dais = <&spdif0_port>;
};
sound-i2s0 {
compatible = "audio-graph-card";
dais = <&i2s0_port>;
};
};
&aud96p22 {
port {
aud96p22_endpoint: endpoint {
remote-endpoint = <&i2s0_endpoint>;
};
};
};
&cpu0 {
cpu-supply = <&a53_vdd0v9>;
};
&emmc {
status = "okay";
};
&hdmi {
status = "disabled";
port {
hdmi_endpoint: endpoint {
remote-endpoint = <&spdif0_endpoint>;
};
};
};
&i2c0 {
status = "okay";
};
&i2s0 {
status = "okay";
i2s0_port: port {
i2s0_endpoint: endpoint {
remote-endpoint = <&aud96p22_endpoint>;
dai-format = "i2s";
frame-master;
bitclock-master;
};
};
};
&irdec {
status = "okay";
};
&pmm {
pwm3_pins: pwm3 {
pins = "KEY_ROW2";
function = "PWM";
};
vga_pins: vga {
pins = "KEY_COL1", "KEY_COL2", "VGA_HS", "VGA_VS";
function = "VGA";
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pins>;
status = "okay";
};
&sd0 {
status = "okay";
};
&sd1 {
status = "okay";
};
&spdif0 {
status = "okay";
spdif0_port: port {
spdif0_endpoint: endpoint {
remote-endpoint = <&hdmi_endpoint>;
};
};
};
&tvenc {
status = "disabled";
};
&uart0 {
status = "okay";
};
&vga {
pinctrl-names = "default";
pinctrl-0 = <&vga_pins>;
status = "okay";
};

627
arch/arm64/boot/dts/zte/zx296718.dtsi
View File

@ -1,627 +0,0 @@
/*
* Copyright 2016 ZTE Corporation.
* Copyright 2016 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/zx296718-clock.h>
/ {
compatible = "zte,zx296718";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
gpio0 = &bgpio0;
gpio1 = &bgpio1;
gpio2 = &bgpio2;
gpio3 = &bgpio3;
gpio4 = &bgpio4;
gpio5 = &bgpio5;
gpio6 = &bgpio6;
serial0 = &uart0;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <866000>;
clock-latency-ns = <500000>;
};
opp-648000000 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <866000>;
clock-latency-ns = <500000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <888000>;
clock-latency-ns = <500000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <898000>;
clock-latency-ns = <500000>;
};
opp-1188000000 {
opp-hz = /bits/ 64 <1188000000>;
opp-microvolt = <1015000>;
clock-latency-ns = <500000>;
};
};
clk24k: clk-24k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000>;
clock-output-names = "rtcclk";
};
osc32k: clk-osc32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "osc32k";
};
osc12m: clk-osc12m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
clock-output-names = "osc12m";
};
osc24m: clk-osc24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc24m";
};
osc25m: clk-osc25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "osc25m";
};
osc60m: clk-osc60m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
clock-output-names = "osc60m";
};
osc99m: clk-osc99m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <99000000>;
clock-output-names = "osc99m";
};
osc125m: clk-osc125m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "osc125m";
};
osc198m: clk-osc198m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <198000000>;
clock-output-names = "osc198m";
};
pll_audio: clk-pll-884m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <884000000>;
clock-output-names = "pll_audio";
};
pll_ddr: clk-pll-932m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <932000000>;
clock-output-names = "pll_ddr";
};
pll_hsic: clk-pll-960m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <960000000>;
clock-output-names = "pll_hsic";
};
pll_mac: clk-pll-1000m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
clock-output-names = "pll_mac";
};
pll_mm0: clk-pll-1188m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1188000000>;
clock-output-names = "pll_mm0";
};
pll_mm1: clk-pll-1296m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1296000000>;
clock-output-names = "pll_mm1";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@2a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x02a00000 0x10000>,
<0x02b00000 0xc0000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
irdec: ir-decoder@111000 {
compatible = "zte,zx296718-irdec";
reg = <0x111000 0x1000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
iocfg: pin-controller@119000 {
compatible = "zte,zx296718-iocfg";
reg = <0x119000 0x1000>;
};
uart0: uart@11f000 {
compatible = "arm,pl011", "arm,primecell";
arm,primecell-periphid = <0x001feffe>;
reg = <0x11f000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24m>;
clock-names = "apb_pclk";
status = "disabled";
};
sd0: mmc@1110000 {
compatible = "zte,zx296718-dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01110000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
data-addr = <0x200>;
fifo-watermark-aligned;
bus-width = <4>;
clock-frequency = <50000000>;
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
status = "disabled";
};
sd1: mmc@1111000 {
compatible = "zte,zx296718-dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01111000 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
data-addr = <0x200>;
fifo-watermark-aligned;
bus-width = <4>;
clock-frequency = <167000000>;
clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <167000000>;
cap-sdio-irq;
cap-sd-highspeed;
status = "disabled";
};
dma: dma-controller@1460000 {
compatible = "zte,zx296702-dma";
reg = <0x01460000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24m>;
clock-names = "dmaclk";
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <32>;
};
lsp0crm: clock-controller@1420000 {
compatible = "zte,zx296718-lsp0crm";
reg = <0x01420000 0x1000>;
#clock-cells = <1>;
};
bgpio0: gpio@142d000 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d000 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 48 16>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio1: gpio@142d040 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d040 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 80 16>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio2: gpio@142d080 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d080 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 80 3
&pmm 3 32 4
&pmm 7 83 9>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio3: gpio@142d0c0 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d0c0 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 92 16>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio4: gpio@142d100 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d100 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 108 12
&pmm 12 121 4>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio5: gpio@142d140 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d140 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 125 16>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
bgpio6: gpio@142d180 {
compatible = "zte,zx296718-gpio", "zte,zx296702-gpio";
reg = <0x142d180 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmm 0 141 2>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
};
lsp1crm: clock-controller@1430000 {
compatible = "zte,zx296718-lsp1crm";
reg = <0x01430000 0x1000>;
#clock-cells = <1>;
};
pwm: pwm@1439000 {
compatible = "zte,zx296718-pwm";
reg = <0x1439000 0x1000>;
clocks = <&lsp1crm LSP1_PWM_PCLK>,
<&lsp1crm LSP1_PWM_WCLK>;
clock-names = "pclk", "wclk";
#pwm-cells = <3>;
status = "disabled";
};
vou: vou@1440000 {
compatible = "zte,zx296718-vou";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1440000 0x10000>;
dpc: dpc@0 {
compatible = "zte,zx296718-dpc";
reg = <0x0000 0x1000>, <0x1000 0x1000>,
<0x5000 0x1000>, <0x6000 0x1000>,
<0xa000 0x1000>;
reg-names = "osd", "timing_ctrl",
"dtrc", "vou_ctrl",
"otfppu";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
<&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
clock-names = "aclk", "ppu_wclk",
"main_wclk", "aux_wclk";
};
vga: vga@8000 {
compatible = "zte,zx296718-vga";
reg = <0x8000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topcrm VGA_I2C_WCLK>;
clock-names = "i2c_wclk";
zte,vga-power-control = <&sysctrl 0x170 0xe0>;
status = "disabled";
};
hdmi: hdmi@c000 {
compatible = "zte,zx296718-hdmi";
reg = <0xc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
clocks = <&topcrm HDMI_OSC_CEC>,
<&topcrm HDMI_OSC_CLK>,
<&topcrm HDMI_XCLK>;
clock-names = "osc_cec", "osc_clk", "xclk";
#sound-dai-cells = <0>;
status = "disabled";
};
tvenc: tvenc@2000 {
compatible = "zte,zx296718-tvenc";
reg = <0x2000 0x1000>;
zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
status = "disabled";
};
};
topcrm: clock-controller@1461000 {
compatible = "zte,zx296718-topcrm";
reg = <0x01461000 0x1000>;
#clock-cells = <1>;
};
pmm: pin-controller@1462000 {
compatible = "zte,zx296718-pmm";
reg = <0x1462000 0x1000>;
zte,auxiliary-controller = <&iocfg>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};
emmc: mmc@1470000{
compatible = "zte,zx296718-dw-mshc";
reg = <0x01470000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
zte,aon-syscon = <&aon_sysctrl>;
bus-width = <8>;
fifo-depth = <128>;
data-addr = <0x200>;
fifo-watermark-aligned;
clock-frequency = <167000000>;
clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <167000000>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
disable-wp;
status = "disabled";
};
audiocrm: clock-controller@1480000 {
compatible = "zte,zx296718-audiocrm";
reg = <0x01480000 0x1000>;
#clock-cells = <1>;
};
i2s0: i2s@1482000 {
compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
reg = <0x01482000 0x1000>;
clocks = <&audiocrm AUDIO_I2S0_WCLK>,
<&audiocrm AUDIO_I2S0_PCLK>;
clock-names = "wclk", "pclk";
assigned-clocks = <&audiocrm I2S0_WCLK_MUX>;
assigned-clock-parents = <&topcrm AUDIO_99M>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma 22>, <&dma 23>;
dma-names = "tx", "rx";
#sound-dai-cells = <0>;
status = "disabled";
};
i2c0: i2c@1486000 {
compatible = "zte,zx296718-i2c";
reg = <0x01486000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&audiocrm AUDIO_I2C0_WCLK>;
clock-frequency = <1600000>;
status = "disabled";
aud96p22: codec@22 {
compatible = "zte,zx-aud96p22";
#sound-dai-cells = <0>;
reg = <0x22>;
};
};
spdif0: spdif@1488000 {
compatible = "zte,zx296702-spdif";
reg = <0x1488000 0x1000>;
clocks = <&audiocrm AUDIO_SPDIF0_WCLK>;
clock-names = "tx";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#sound-dai-cells = <0>;
dmas = <&dma 30>;
dma-names = "tx";
status = "disabled";
};
};
};

2
drivers/reset/Kconfig
View File

@ -173,7 +173,7 @@ config RESET_SCMI
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST
default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC
default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARC
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,

1
drivers/soc/Kconfig
View File

@ -22,7 +22,6 @@ source "drivers/soc/ti/Kconfig"
source "drivers/soc/ux500/Kconfig"
source "drivers/soc/versatile/Kconfig"
source "drivers/soc/xilinx/Kconfig"
source "drivers/soc/zte/Kconfig"
source "drivers/soc/kendryte/Kconfig"
endmenu

1
drivers/soc/Makefile
View File

@ -28,5 +28,4 @@ obj-y += ti/
obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_PLAT_VERSATILE) += versatile/
obj-y += xilinx/
obj-$(CONFIG_ARCH_ZX) += zte/
obj-$(CONFIG_SOC_KENDRYTE) += kendryte/

15
drivers/soc/zte/Kconfig
View File

@ -1,15 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# ZTE SoC drivers
#
menuconfig SOC_ZTE
depends on ARCH_ZX || COMPILE_TEST
bool "ZTE SoC driver support"
if SOC_ZTE
config ZX2967_PM_DOMAINS
bool "ZX2967 PM domains"
depends on PM_GENERIC_DOMAINS
endif

6
drivers/soc/zte/Makefile
View File

@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# ZTE SOC drivers
#
obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx2967_pm_domains.o
obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx296718_pm_domains.o

181
drivers/soc/zte/zx296718_pm_domains.c
View File

@ -1,181 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 ZTE Ltd.
*
* Author: Baoyou Xie <baoyou.xie@linaro.org>
*/
#include <dt-bindings/soc/zte,pm_domains.h>
#include "zx2967_pm_domains.h"
static u16 zx296718_offsets[REG_ARRAY_SIZE] = {
[REG_CLKEN] = 0x18,
[REG_ISOEN] = 0x1c,
[REG_RSTEN] = 0x20,
[REG_PWREN] = 0x24,
[REG_ACK_SYNC] = 0x28,
};
enum {
PCU_DM_VOU = 0,
PCU_DM_SAPPU,
PCU_DM_VDE,
PCU_DM_VCE,
PCU_DM_HDE,
PCU_DM_VIU,
PCU_DM_USB20,
PCU_DM_USB21,
PCU_DM_USB30,
PCU_DM_HSIC,
PCU_DM_GMAC,
PCU_DM_TS,
};
static struct zx2967_pm_domain vou_domain = {
.dm = {
.name = "vou_domain",
},
.bit = PCU_DM_VOU,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain sappu_domain = {
.dm = {
.name = "sappu_domain",
},
.bit = PCU_DM_SAPPU,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain vde_domain = {
.dm = {
.name = "vde_domain",
},
.bit = PCU_DM_VDE,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain vce_domain = {
.dm = {
.name = "vce_domain",
},
.bit = PCU_DM_VCE,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain hde_domain = {
.dm = {
.name = "hde_domain",
},
.bit = PCU_DM_HDE,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain viu_domain = {
.dm = {
.name = "viu_domain",
},
.bit = PCU_DM_VIU,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain usb20_domain = {
.dm = {
.name = "usb20_domain",
},
.bit = PCU_DM_USB20,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain usb21_domain = {
.dm = {
.name = "usb21_domain",
},
.bit = PCU_DM_USB21,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain usb30_domain = {
.dm = {
.name = "usb30_domain",
},
.bit = PCU_DM_USB30,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain hsic_domain = {
.dm = {
.name = "hsic_domain",
},
.bit = PCU_DM_HSIC,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain gmac_domain = {
.dm = {
.name = "gmac_domain",
},
.bit = PCU_DM_GMAC,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct zx2967_pm_domain ts_domain = {
.dm = {
.name = "ts_domain",
},
.bit = PCU_DM_TS,
.polarity = PWREN,
.reg_offset = zx296718_offsets,
};
static struct generic_pm_domain *zx296718_pm_domains[] = {
[DM_ZX296718_VOU] = &vou_domain.dm,
[DM_ZX296718_SAPPU] = &sappu_domain.dm,
[DM_ZX296718_VDE] = &vde_domain.dm,
[DM_ZX296718_VCE] = &vce_domain.dm,
[DM_ZX296718_HDE] = &hde_domain.dm,
[DM_ZX296718_VIU] = &viu_domain.dm,
[DM_ZX296718_USB20] = &usb20_domain.dm,
[DM_ZX296718_USB21] = &usb21_domain.dm,
[DM_ZX296718_USB30] = &usb30_domain.dm,
[DM_ZX296718_HSIC] = &hsic_domain.dm,
[DM_ZX296718_GMAC] = &gmac_domain.dm,
[DM_ZX296718_TS] = &ts_domain.dm,
};
static int zx296718_pd_probe(struct platform_device *pdev)
{
return zx2967_pd_probe(pdev,
zx296718_pm_domains,
ARRAY_SIZE(zx296718_pm_domains));
}
static const struct of_device_id zx296718_pm_domain_matches[] = {
{ .compatible = "zte,zx296718-pcu", },
{ },
};
static struct platform_driver zx296718_pd_driver = {
.driver = {
.name = "zx296718-powerdomain",
.of_match_table = zx296718_pm_domain_matches,
},
.probe = zx296718_pd_probe,
};
static int __init zx296718_pd_init(void)
{
return platform_driver_register(&zx296718_pd_driver);
}
subsys_initcall(zx296718_pd_init);

141
drivers/soc/zte/zx2967_pm_domains.c
View File

@ -1,141 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 ZTE Ltd.
*
* Author: Baoyou Xie <baoyou.xie@linaro.org>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include "zx2967_pm_domains.h"
#define PCU_DM_CLKEN(zpd) ((zpd)->reg_offset[REG_CLKEN])
#define PCU_DM_ISOEN(zpd) ((zpd)->reg_offset[REG_ISOEN])
#define PCU_DM_RSTEN(zpd) ((zpd)->reg_offset[REG_RSTEN])
#define PCU_DM_PWREN(zpd) ((zpd)->reg_offset[REG_PWREN])
#define PCU_DM_ACK_SYNC(zpd) ((zpd)->reg_offset[REG_ACK_SYNC])
static void __iomem *pcubase;
static int zx2967_power_on(struct generic_pm_domain *domain)
{
struct zx2967_pm_domain *zpd = (struct zx2967_pm_domain *)domain;
unsigned long loop = 1000;
u32 val;
val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd));
if (zpd->polarity == PWREN)
val |= BIT(zpd->bit);
else
val &= ~BIT(zpd->bit);
writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd));
do {
udelay(1);
val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd))
& BIT(zpd->bit);
} while (--loop && !val);
if (!loop) {
pr_err("Error: %s %s fail\n", __func__, domain->name);
return -EIO;
}
val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd));
val |= BIT(zpd->bit);
writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd));
udelay(5);
val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd));
val &= ~BIT(zpd->bit);
writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd));
udelay(5);
val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd));
val |= BIT(zpd->bit);
writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd));
udelay(5);
pr_debug("poweron %s\n", domain->name);
return 0;
}
static int zx2967_power_off(struct generic_pm_domain *domain)
{
struct zx2967_pm_domain *zpd = (struct zx2967_pm_domain *)domain;
unsigned long loop = 1000;
u32 val;
val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd));
val &= ~BIT(zpd->bit);
writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd));
udelay(5);
val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd));
val |= BIT(zpd->bit);
writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd));
udelay(5);
val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd));
val &= ~BIT(zpd->bit);
writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd));
udelay(5);
val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd));
if (zpd->polarity == PWREN)
val &= ~BIT(zpd->bit);
else
val |= BIT(zpd->bit);
writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd));
do {
udelay(1);
val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd))
& BIT(zpd->bit);
} while (--loop && val);
if (!loop) {
pr_err("Error: %s %s fail\n", __func__, domain->name);
return -EIO;
}
pr_debug("poweroff %s\n", domain->name);
return 0;
}
int zx2967_pd_probe(struct platform_device *pdev,
struct generic_pm_domain **zx_pm_domains,
int domain_num)
{
struct genpd_onecell_data *genpd_data;
struct resource *res;
int i;
genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL);
if (!genpd_data)
return -ENOMEM;
genpd_data->domains = zx_pm_domains;
genpd_data->num_domains = domain_num;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pcubase = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pcubase))
return PTR_ERR(pcubase);
for (i = 0; i < domain_num; ++i) {
zx_pm_domains[i]->power_on = zx2967_power_on;
zx_pm_domains[i]->power_off = zx2967_power_off;
pm_genpd_init(zx_pm_domains[i], NULL, false);
}
of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data);
dev_info(&pdev->dev, "powerdomain init ok\n");
return 0;
}

44
drivers/soc/zte/zx2967_pm_domains.h
View File

@ -1,44 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Header for ZTE's Power Domain Driver support
*
* Copyright (C) 2017 ZTE Ltd.
*
* Author: Baoyou Xie <baoyou.xie@linaro.org>
*/
#ifndef __ZTE_ZX2967_PM_DOMAIN_H
#define __ZTE_ZX2967_PM_DOMAIN_H
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
enum {
REG_CLKEN,
REG_ISOEN,
REG_RSTEN,
REG_PWREN,
REG_PWRDN,
REG_ACK_SYNC,
/* The size of the array - must be last */
REG_ARRAY_SIZE,
};
enum zx2967_power_polarity {
PWREN,
PWRDN,
};
struct zx2967_pm_domain {
struct generic_pm_domain dm;
const u16 bit;
const enum zx2967_power_polarity polarity;
const u16 *reg_offset;
};
int zx2967_pd_probe(struct platform_device *pdev,
struct generic_pm_domain **zx_pm_domains,
int domain_num);
#endif /* __ZTE_ZX2967_PM_DOMAIN_H */