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clk: k210: remove an implicit 64-bit division

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The K210 clock driver depends on SOC_CANAAN, which is only selectable
when !MMU on RISC-V. !MMU is not possible on 32-bit yet, but patches
have been sent for its enabling. The kernel test robot reported this
implicit 64-bit division there.

Replace the implicit division with an explicit one.

Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/linux-riscv/202301201538.zNlqgE4L-lkp@intel.com/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Link: https://lore.kernel.org/r/20230301002657.352637-2-Mr.Bossman075@gmail.com
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Conor Dooley 2023-02-28 19:26:55 -05:00 committed by Stephen Boyd
parent 26243872fe
commit 89dc65a7cc
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/clk-k210.c
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@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw,
f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
return (u64)parent_rate * f / (r * od);
return div_u64((u64)parent_rate * f, r * od);
}
static const struct clk_ops k210_pll_ops = {