mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-30 08:02:30 +00:00
i.MX device tree update with new clocks:
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board device tree support. - Add DSP device tree support for i.MX8QXP SoC. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJdYom7AAoJEFBXWFqHsHzOVG8H/RTfCTmRCBaClVZ031GWl/Q2 2NP+AY1l8UE0NKsvEuoMf/VY1atvFNgDvbm4gV1PW5KOBbgZmB3M32lHvXfqbLOu vACCc8b7JY/8scWUgQBNbE5xAiZjPkLPuIYNJTLmrgVrYkYhtkB/4pwAk9YjVlYt eHF3SWizKmam8vV3yp6KUNKvEYPBiMBfjSHDUvgT0GHUB4SHpPm/ERruTdKxP0Zm c730yvV320XiKvxuErdvNfsw6FWs8Bhp8xCIhvF4Wbm0w4c5ucuqHKSV1v63lbbj GVfdi0cH/eKlugNhfhIH7RsYL5TYjCDwzEyBSnqGCaBW+gnTpRnFkEricgvB+yY= =3nO3 -----END PGP SIGNATURE----- Merge tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX device tree update with new clocks: - A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board device tree support. - Add DSP device tree support for i.MX8QXP SoC. * tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8qxp: Add DSP DT node arm64: dts: imx8mn: Add cpu-freq support arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support arm64: dts: imx8mn-ddr4-evk: Add i2c1 support arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support arm64: dts: imx8mn: Add gpio-ranges property arm64: dts: freescale: Add i.MX8MN dtsi support clk: imx8: Add DSP related clocks clk: imx: Add support for i.MX8MN clock driver clk: imx: Add API for clk unregister when driver probe fail clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage dt-bindings: imx: Add clock binding doc for i.MX8MN Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
89e4acf7a3
15 changed files with 2149 additions and 18 deletions
112
Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
Normal file
112
Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
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@ -0,0 +1,112 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8M Nano Clock Control Module Binding
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maintainers:
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- Anson Huang <Anson.Huang@nxp.com>
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description: |
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NXP i.MX8M Nano clock control module is an integrated clock controller, which
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generates and supplies to all modules.
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properties:
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compatible:
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const: fsl,imx8mn-ccm
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reg:
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maxItems: 1
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clocks:
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items:
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- description: 32k osc
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- description: 24m osc
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- description: ext1 clock input
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- description: ext2 clock input
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- description: ext3 clock input
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- description: ext4 clock input
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clock-names:
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items:
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- const: osc_32k
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- const: osc_24m
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- const: clk_ext1
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- const: clk_ext2
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- const: clk_ext3
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- const: clk_ext4
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
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for the full list of i.MX8M Nano clock IDs.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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examples:
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# Clock Control Module node:
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- |
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clk: clock-controller@30380000 {
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compatible = "fsl,imx8mn-ccm";
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reg = <0x0 0x30380000 0x0 0x10000>;
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#clock-cells = <1>;
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clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
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<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
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clock-names = "osc_32k", "osc_24m", "clk_ext1",
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"clk_ext2", "clk_ext3", "clk_ext4";
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};
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# Required external clocks for Clock Control Module node:
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- |
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osc_32k: clock-osc-32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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};
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osc_24m: clock-osc-24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc_24m";
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};
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clk_ext1: clock-ext1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext1";
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};
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clk_ext2: clock-ext2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext2";
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};
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clk_ext3: clock-ext3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext3";
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};
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clk_ext4: clock-ext4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency= <133000000>;
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clock-output-names = "clk_ext4";
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};
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...
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@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
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|
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348
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
Normal file
348
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
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@ -0,0 +1,348 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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#include "imx8mn.dtsi"
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/ {
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model = "NXP i.MX8MNano DDR4 EVK board";
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compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
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chosen {
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stdout-path = &uart2;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_pmic: pmicirq {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
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MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
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MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
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MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
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MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
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MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
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MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
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MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
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MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
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>;
|
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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fsl,pins = <
|
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MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
|
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MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
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MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
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MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
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MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
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>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
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fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
|
||||
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
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MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
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MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
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MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
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MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
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MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
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MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
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pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
at803x,led-act-blind-workaround;
|
||||
at803x,eee-disabled;
|
||||
at803x,vddio-1p8v;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic@4b {
|
||||
compatible = "rohm,bd71847";
|
||||
reg = <0x4b>;
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 GPIO_ACTIVE_LOW>;
|
||||
rohm,reset-snvs-powered;
|
||||
|
||||
regulators {
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
// BUCK5 in datasheet
|
||||
regulator-name = "BUCK3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
// BUCK6 in datasheet
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
// BUCK7 in datasheet
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
// BUCK8 in datasheet
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "LDO6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
758
arch/arm64/boot/dts/freescale/imx8mn.dtsi
Normal file
758
arch/arm64/boot/dts/freescale/imx8mn.dtsi
Normal file
|
@ -0,0 +1,758 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "imx8mn-pinfunc.h"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,imx8mn";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &ecspi3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
A53_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
nvmem-cells = <&cpu_speed_grade>;
|
||||
nvmem-cell-names = "speed_grade";
|
||||
};
|
||||
|
||||
A53_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
};
|
||||
|
||||
A53_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
};
|
||||
|
||||
A53_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
clock-latency = <61036>;
|
||||
clocks = <&clk IMX8MN_CLK_ARM>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A53_L2>;
|
||||
operating-points-v2 = <&a53_opp_table>;
|
||||
};
|
||||
|
||||
A53_L2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
a53_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <850000>;
|
||||
opp-supported-hw = <0xb00>, <0x7>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-microvolt = <950000>;
|
||||
opp-supported-hw = <0x300>, <0x7>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
opp-supported-hw = <0x100>, <0x3>;
|
||||
clock-latency-ns = <150000>;
|
||||
opp-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
osc_32k: clock-osc-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
osc_24m: clock-osc-24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc_24m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
clk_ext2: clock-ext2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext2";
|
||||
};
|
||||
|
||||
clk_ext3: clock-ext3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext3";
|
||||
};
|
||||
|
||||
clk_ext4: clock-ext4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency= <133000000>;
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <8000000>;
|
||||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x0 0x3e000000>;
|
||||
|
||||
aips1: bus@30000000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30000000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30200000 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 10 30>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30210000 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 40 21>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30220000 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 61 26>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30230000 0x10000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 21 108 11>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x30240000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 119 30>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30280000 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog2: watchdog@30290000 {
|
||||
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x30290000 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: watchdog@302a0000 {
|
||||
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x302a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma3: dma-controller@302b0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
reg = <0x302b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
|
||||
<&clk IMX8MN_CLK_SDMA3_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
sdma2: dma-controller@302c0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
|
||||
<&clk IMX8MN_CLK_SDMA2_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mn-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@30340000 {
|
||||
compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
|
||||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpu_speed_grade: speed-grade@10 {
|
||||
reg = <0x10 4>;
|
||||
};
|
||||
};
|
||||
|
||||
anatop: anatop@30360000 {
|
||||
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
|
||||
"syscon", "simple-bus";
|
||||
reg = <0x30360000 0x10000>;
|
||||
};
|
||||
|
||||
snvs: snvs@30370000 {
|
||||
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
|
||||
reg = <0x30370000 0x10000>;
|
||||
|
||||
snvs_rtc: snvs-rtc-lp {
|
||||
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
||||
regmap = <&snvs>;
|
||||
offset = <0x34>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "snvs-rtc";
|
||||
};
|
||||
|
||||
snvs_pwrkey: snvs-powerkey {
|
||||
compatible = "fsl,sec-v4.0-pwrkey";
|
||||
regmap = <&snvs>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
linux,keycode = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mn-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
src: reset-controller@30390000 {
|
||||
compatible = "fsl,imx8mn-src", "syscon";
|
||||
reg = <0x30390000 0x10000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
aips2: bus@30400000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30400000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pwm1: pwm@30660000 {
|
||||
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30660000 0x10000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
|
||||
<&clk IMX8MN_CLK_PWM1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@30670000 {
|
||||
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30670000 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
|
||||
<&clk IMX8MN_CLK_PWM2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@30680000 {
|
||||
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30680000 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
|
||||
<&clk IMX8MN_CLK_PWM3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@30690000 {
|
||||
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x30690000 0x10000>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
|
||||
<&clk IMX8MN_CLK_PWM4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips3: bus@30800000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30800000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
ecspi1: spi@30820000 {
|
||||
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30820000 0x10000>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
|
||||
<&clk IMX8MN_CLK_ECSPI1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: spi@30830000 {
|
||||
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30830000 0x10000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
|
||||
<&clk IMX8MN_CLK_ECSPI2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi3: spi@30840000 {
|
||||
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30840000 0x10000>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
|
||||
<&clk IMX8MN_CLK_ECSPI3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@30860000 {
|
||||
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30860000 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
|
||||
<&clk IMX8MN_CLK_UART1_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@30880000 {
|
||||
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30880000 0x10000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
|
||||
<&clk IMX8MN_CLK_UART3_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@30890000 {
|
||||
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30890000 0x10000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
|
||||
<&clk IMX8MN_CLK_UART2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a20000 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a30000 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x30a40000 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x30a50000 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@30a60000 {
|
||||
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
|
||||
reg = <0x30a60000 0x10000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
|
||||
<&clk IMX8MN_CLK_UART4_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: mmc@30b50000 {
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b50000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc3: mmc@30b60000 {
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b60000 0x10000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_DUMMY>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
|
||||
<&clk IMX8MN_CLK_SDMA1_ROOT>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x30be0000 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MN_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MN_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MN_CLK_ENET_REF>,
|
||||
<&clk IMX8MN_CLK_ENET_PHY_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
|
||||
<&clk IMX8MN_CLK_ENET_TIMER>,
|
||||
<&clk IMX8MN_CLK_ENET_REF>,
|
||||
<&clk IMX8MN_CLK_ENET_TIMER>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
|
||||
<&clk IMX8MN_SYS_PLL2_100M>,
|
||||
<&clk IMX8MN_SYS_PLL2_125M>;
|
||||
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
|
||||
fsl,num-tx-queues = <3>;
|
||||
fsl,num-rx-queues = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
aips4: bus@32c00000 {
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32c00000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usbotg1: usb@32e40000 {
|
||||
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
|
||||
reg = <0x32e40000 0x200>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
|
||||
clock-names = "usb1_ctrl_root_clk";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
|
||||
<&clk IMX8MN_CLK_USB_CORE_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
|
||||
<&clk IMX8MN_SYS_PLL1_100M>;
|
||||
fsl,usbphy = <&usbphynop1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc1: usbmisc@32e40200 {
|
||||
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
|
||||
#index-cells = <1>;
|
||||
reg = <0x32e40200 0x200>;
|
||||
};
|
||||
|
||||
usbotg2: usb@32e50000 {
|
||||
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
|
||||
reg = <0x32e50000 0x200>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
|
||||
clock-names = "usb1_ctrl_root_clk";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
|
||||
<&clk IMX8MN_CLK_USB_CORE_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
|
||||
<&clk IMX8MN_SYS_PLL1_100M>;
|
||||
fsl,usbphy = <&usbphynop2>;
|
||||
fsl,usbmisc = <&usbmisc2 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc2: usbmisc@32e50200 {
|
||||
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
|
||||
#index-cells = <1>;
|
||||
reg = <0x32e50200 0x200>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
dma_apbh: dma-controller@33000000 {
|
||||
compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
|
||||
reg = <0x33000000 0x2000>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <4>;
|
||||
clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
|
||||
};
|
||||
|
||||
gpmi: nand-controller@33002000 {
|
||||
compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "bch";
|
||||
clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
|
||||
<&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
|
||||
clock-names = "gpmi_io", "gpmi_bch_apb";
|
||||
dmas = <&dma_apbh 0>;
|
||||
dma-names = "rx-tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x38800000 0x10000>,
|
||||
<0x38880000 0xc0000>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
usbphynop1: usbphynop1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
usbphynop2: usbphynop2 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
|
@ -230,3 +230,7 @@ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
|
|||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&adma_dsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -113,6 +113,17 @@ gic: interrupt-controller@51a00000 {
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
dsp_reserved: dsp@92400000 {
|
||||
reg = <0 0x92400000 0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -204,6 +215,27 @@ adma_lpcg: clock-controller@59000000 {
|
|||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
adma_dsp: dsp@596e8000 {
|
||||
compatible = "fsl,imx8qxp-dsp";
|
||||
reg = <0x596e8000 0x88000>;
|
||||
clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
|
||||
<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
|
||||
<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
|
||||
clock-names = "ipg", "ocram", "core";
|
||||
power-domains = <&pd IMX_SC_R_MU_13A>,
|
||||
<&pd IMX_SC_R_MU_13B>,
|
||||
<&pd IMX_SC_R_DSP>,
|
||||
<&pd IMX_SC_R_DSP_RAM>;
|
||||
mbox-names = "txdb0", "txdb1",
|
||||
"rxdb0", "rxdb1";
|
||||
mboxes = <&lsio_mu13 2 0>,
|
||||
<&lsio_mu13 2 1>,
|
||||
<&lsio_mu13 3 0>,
|
||||
<&lsio_mu13 3 1>;
|
||||
memory-region = <&dsp_reserved>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adma_lpuart0: serial@5a060000 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x5a060000 0x1000>;
|
||||
|
|
|
@ -14,6 +14,12 @@ config CLK_IMX8MM
|
|||
help
|
||||
Build the driver for i.MX8MM CCM Clock Driver
|
||||
|
||||
config CLK_IMX8MN
|
||||
bool "IMX8MN CCM Clock Driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
help
|
||||
Build the driver for i.MX8MN CCM Clock Driver
|
||||
|
||||
config CLK_IMX8MQ
|
||||
bool "IMX8MQ CCM Clock Driver"
|
||||
depends on ARCH_MXC && ARM64
|
||||
|
|
|
@ -26,6 +26,7 @@ obj-$(CONFIG_MXC_CLK_SCU) += \
|
|||
clk-lpcg-scu.o
|
||||
|
||||
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
|
||||
obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
|
||||
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
|
||||
obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o
|
||||
|
||||
|
|
|
@ -26,23 +26,6 @@ static u32 share_count_dcss;
|
|||
static u32 share_count_pdm;
|
||||
static u32 share_count_nand;
|
||||
|
||||
#define PLL_1416X_RATE(_rate, _m, _p, _s) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
}
|
||||
|
||||
#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
.kdiv = (_k), \
|
||||
}
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
|
||||
PLL_1416X_RATE(1800000000U, 225, 3, 0),
|
||||
PLL_1416X_RATE(1600000000U, 200, 3, 0),
|
||||
|
|
636
drivers/clk/imx/clk-imx8mn.c
Normal file
636
drivers/clk/imx/clk-imx8mn.c
Normal file
|
@ -0,0 +1,636 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2018-2019 NXP.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
static u32 share_count_sai2;
|
||||
static u32 share_count_sai3;
|
||||
static u32 share_count_sai5;
|
||||
static u32 share_count_sai6;
|
||||
static u32 share_count_sai7;
|
||||
static u32 share_count_disp;
|
||||
static u32 share_count_pdm;
|
||||
static u32 share_count_nand;
|
||||
|
||||
enum {
|
||||
ARM_PLL,
|
||||
GPU_PLL,
|
||||
VPU_PLL,
|
||||
SYS_PLL1,
|
||||
SYS_PLL2,
|
||||
SYS_PLL3,
|
||||
DRAM_PLL,
|
||||
AUDIO_PLL1,
|
||||
AUDIO_PLL2,
|
||||
VIDEO_PLL2,
|
||||
NR_PLLS,
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
|
||||
PLL_1416X_RATE(1800000000U, 225, 3, 0),
|
||||
PLL_1416X_RATE(1600000000U, 200, 3, 0),
|
||||
PLL_1416X_RATE(1200000000U, 300, 3, 1),
|
||||
PLL_1416X_RATE(1000000000U, 250, 3, 1),
|
||||
PLL_1416X_RATE(800000000U, 200, 3, 1),
|
||||
PLL_1416X_RATE(750000000U, 250, 2, 2),
|
||||
PLL_1416X_RATE(700000000U, 350, 3, 2),
|
||||
PLL_1416X_RATE(600000000U, 300, 3, 2),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
|
||||
PLL_1443X_RATE(786432000U, 655, 5, 2, 23593),
|
||||
PLL_1443X_RATE(722534400U, 301, 5, 1, 3670),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_audio_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_audiopll_tbl,
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_video_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_videopll_tbl,
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_dram_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_drampll_tbl,
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_arm_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_gpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_vpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_sys_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
};
|
||||
|
||||
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
|
||||
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
|
||||
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
|
||||
static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
|
||||
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
|
||||
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
|
||||
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
|
||||
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
|
||||
static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
|
||||
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
|
||||
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
||||
|
||||
static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
|
||||
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
"audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
|
||||
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll1_100m",};
|
||||
|
||||
static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
|
||||
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
|
||||
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
|
||||
"clk_ext1", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys1_pll_40m", "audio_pll2_out",
|
||||
"clk_ext1", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
|
||||
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
|
||||
"audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
|
||||
"sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
|
||||
"audio_pll1_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
|
||||
"sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll1_out", "sys_pll1_266m", };
|
||||
|
||||
static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
|
||||
"audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"sys_pll3_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
|
||||
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
|
||||
"video_pll1_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
|
||||
"clk_ext1", "clk_ext2", "clk_ext3",
|
||||
"clk_ext4", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
|
||||
"sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
|
||||
"audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
|
||||
"sys_pll2_250m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys1_pll_400m", "sys_pll1_800m",
|
||||
"sys2_pll_500m", "audio_pll2_out", "sys1_pll_266m",
|
||||
"sys3_pll2_out", "sys1_pll_100m", };
|
||||
|
||||
static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext4", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
"sys_pll2_100m", "sys_pll3_out", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
|
||||
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys3_pll2_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
|
||||
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
|
||||
"sys_pll1_80m", "sys_pll2_166m", };
|
||||
|
||||
static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
|
||||
"sys_pll2_500m", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
"audio_pll2_clk", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
|
||||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m",
|
||||
"sys_pll1_200m", "audio_pll2_clk", "vpu_pll",
|
||||
"sys_pll1_80m", };
|
||||
static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
|
||||
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
|
||||
"video_pll1_out", "osc_32k", };
|
||||
|
||||
static struct clk *clks[IMX8MN_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static int imx8mn_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret;
|
||||
|
||||
clks[IMX8MN_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clks[IMX8MN_CLK_24M] = of_clk_get_by_name(np, "osc_24m");
|
||||
clks[IMX8MN_CLK_32K] = of_clk_get_by_name(np, "osc_32k");
|
||||
clks[IMX8MN_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1");
|
||||
clks[IMX8MN_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2");
|
||||
clks[IMX8MN_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3");
|
||||
clks[IMX8MN_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base)) {
|
||||
ret = -ENOMEM;
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
clks[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
|
||||
clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mn_audio_pll);
|
||||
clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mn_audio_pll);
|
||||
clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mn_video_pll);
|
||||
clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mn_dram_pll);
|
||||
clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mn_gpu_pll);
|
||||
clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mn_vpu_pll);
|
||||
clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mn_arm_pll);
|
||||
clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll);
|
||||
|
||||
/* PLL bypass out */
|
||||
clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* unbypass all the plls */
|
||||
clk_set_parent(clks[IMX8MN_AUDIO_PLL1_BYPASS], clks[IMX8MN_AUDIO_PLL1]);
|
||||
clk_set_parent(clks[IMX8MN_AUDIO_PLL2_BYPASS], clks[IMX8MN_AUDIO_PLL2]);
|
||||
clk_set_parent(clks[IMX8MN_VIDEO_PLL1_BYPASS], clks[IMX8MN_VIDEO_PLL1]);
|
||||
clk_set_parent(clks[IMX8MN_DRAM_PLL_BYPASS], clks[IMX8MN_DRAM_PLL]);
|
||||
clk_set_parent(clks[IMX8MN_GPU_PLL_BYPASS], clks[IMX8MN_GPU_PLL]);
|
||||
clk_set_parent(clks[IMX8MN_VPU_PLL_BYPASS], clks[IMX8MN_VPU_PLL]);
|
||||
clk_set_parent(clks[IMX8MN_ARM_PLL_BYPASS], clks[IMX8MN_ARM_PLL]);
|
||||
clk_set_parent(clks[IMX8MN_SYS_PLL1_BYPASS], clks[IMX8MN_SYS_PLL1]);
|
||||
clk_set_parent(clks[IMX8MN_SYS_PLL2_BYPASS], clks[IMX8MN_SYS_PLL2]);
|
||||
clk_set_parent(clks[IMX8MN_SYS_PLL3_BYPASS], clks[IMX8MN_SYS_PLL3]);
|
||||
|
||||
/* PLL out gate */
|
||||
clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
|
||||
clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
|
||||
clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
|
||||
clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
|
||||
clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 13);
|
||||
clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 13);
|
||||
clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 13);
|
||||
clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 13);
|
||||
clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 13);
|
||||
clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 13);
|
||||
|
||||
/* SYS PLL fixed output */
|
||||
clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
|
||||
clks[IMX8MN_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
|
||||
|
||||
clks[IMX8MN_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
|
||||
clks[IMX8MN_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base))) {
|
||||
ret = PTR_ERR(base);
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
/* CORE */
|
||||
clks[IMX8MN_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
|
||||
clks[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels));
|
||||
clks[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels));
|
||||
clks[IMX8MN_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
|
||||
clks[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
|
||||
clks[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
|
||||
|
||||
clks[IMX8MN_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
clks[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
|
||||
clks[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
|
||||
|
||||
/* BUS */
|
||||
clks[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
|
||||
clks[IMX8MN_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
|
||||
clks[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
|
||||
clks[IMX8MN_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
|
||||
clks[IMX8MN_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
|
||||
clks[IMX8MN_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
|
||||
clks[IMX8MN_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
|
||||
clks[IMX8MN_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
|
||||
clks[IMX8MN_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00);
|
||||
|
||||
clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
|
||||
clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
|
||||
clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
|
||||
clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
|
||||
clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
|
||||
clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
|
||||
clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
|
||||
clks[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
|
||||
clks[IMX8MN_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
|
||||
clks[IMX8MN_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mn_sai3_sels, base + 0xa680);
|
||||
clks[IMX8MN_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mn_sai5_sels, base + 0xa780);
|
||||
clks[IMX8MN_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mn_sai6_sels, base + 0xa800);
|
||||
clks[IMX8MN_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880);
|
||||
clks[IMX8MN_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980);
|
||||
clks[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00);
|
||||
clks[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80);
|
||||
clks[IMX8MN_CLK_NAND] = imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00);
|
||||
clks[IMX8MN_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80);
|
||||
clks[IMX8MN_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00);
|
||||
clks[IMX8MN_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80);
|
||||
clks[IMX8MN_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00);
|
||||
clks[IMX8MN_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80);
|
||||
clks[IMX8MN_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00);
|
||||
clks[IMX8MN_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80);
|
||||
clks[IMX8MN_CLK_UART1] = imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00);
|
||||
clks[IMX8MN_CLK_UART2] = imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80);
|
||||
clks[IMX8MN_CLK_UART3] = imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000);
|
||||
clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080);
|
||||
clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100);
|
||||
clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180);
|
||||
clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280);
|
||||
clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300);
|
||||
clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380);
|
||||
clks[IMX8MN_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
|
||||
clks[IMX8MN_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
|
||||
clks[IMX8MN_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
|
||||
clks[IMX8MN_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
|
||||
clks[IMX8MN_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
|
||||
clks[IMX8MN_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
|
||||
clks[IMX8MN_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mn_clko2_sels, base + 0xba80);
|
||||
clks[IMX8MN_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00);
|
||||
clks[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80);
|
||||
clks[IMX8MN_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00);
|
||||
clks[IMX8MN_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80);
|
||||
clks[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00);
|
||||
clks[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80);
|
||||
clks[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00);
|
||||
clks[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80);
|
||||
clks[IMX8MN_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180);
|
||||
clks[IMX8MN_CLK_PDM] = imx8m_clk_composite("pdm", imx8mn_pdm_sels, base + 0xc200);
|
||||
clks[IMX8MN_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mn_sai7_sels, base + 0xc300);
|
||||
|
||||
clks[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
|
||||
clks[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
|
||||
clks[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
|
||||
clks[IMX8MN_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
|
||||
clks[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
|
||||
clks[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
|
||||
clks[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
|
||||
clks[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
|
||||
clks[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
|
||||
clks[IMX8MN_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
|
||||
clks[IMX8MN_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
|
||||
clks[IMX8MN_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
|
||||
clks[IMX8MN_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
|
||||
clks[IMX8MN_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
|
||||
clks[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
|
||||
clks[IMX8MN_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
|
||||
clks[IMX8MN_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
|
||||
clks[IMX8MN_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
|
||||
clks[IMX8MN_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
|
||||
clks[IMX8MN_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
|
||||
clks[IMX8MN_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
|
||||
clks[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
|
||||
clks[IMX8MN_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
|
||||
clks[IMX8MN_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2);
|
||||
clks[IMX8MN_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
|
||||
clks[IMX8MN_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3);
|
||||
clks[IMX8MN_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
|
||||
clks[IMX8MN_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
clks[IMX8MN_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
clks[IMX8MN_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
clks[IMX8MN_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
clks[IMX8MN_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
clks[IMX8MN_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
clks[IMX8MN_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0);
|
||||
clks[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0);
|
||||
clks[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
clks[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
clks[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
|
||||
clks[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
|
||||
clks[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
|
||||
clks[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
|
||||
clks[IMX8MN_CLK_ASRC_ROOT] = imx_clk_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0);
|
||||
clks[IMX8MN_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MN_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
|
||||
clks[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp);
|
||||
clks[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
|
||||
clks[IMX8MN_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
|
||||
clks[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
|
||||
clks[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
|
||||
clks[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
|
||||
clks[IMX8MN_CLK_SAI7_ROOT] = imx_clk_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
|
||||
|
||||
clks[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
|
||||
clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div",
|
||||
clks[IMX8MN_CLK_A53_DIV],
|
||||
clks[IMX8MN_CLK_A53_SRC],
|
||||
clks[IMX8MN_ARM_PLL_OUT],
|
||||
clks[IMX8MN_CLK_24M]);
|
||||
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to register clks for i.MX8MN\n");
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
unregister_clks:
|
||||
imx_unregister_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id imx8mn_clk_of_match[] = {
|
||||
{ .compatible = "fsl,imx8mn-ccm" },
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match);
|
||||
|
||||
static struct platform_driver imx8mn_clk_driver = {
|
||||
.probe = imx8mn_clocks_probe,
|
||||
.driver = {
|
||||
.name = "imx8mn-ccm",
|
||||
.of_match_table = of_match_ptr(imx8mn_clk_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(imx8mn_clk_driver);
|
|
@ -72,6 +72,11 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
|
|||
{ IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
|
||||
{ IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
|
||||
{ IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
|
||||
|
||||
{ IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
|
||||
{ IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
|
||||
{ IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
|
||||
{ IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
|
||||
};
|
||||
|
||||
static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
|
||||
|
|
|
@ -14,6 +14,14 @@
|
|||
|
||||
DEFINE_SPINLOCK(imx_ccm_lock);
|
||||
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
clk_unregister(clks[i]);
|
||||
}
|
||||
|
||||
void __init imx_mmdc_mask_handshake(void __iomem *ccm_base,
|
||||
unsigned int chn)
|
||||
{
|
||||
|
|
|
@ -12,6 +12,7 @@ void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
|
|||
void imx_register_uart_clocks(struct clk ** const clks[]);
|
||||
void imx_register_uart_clocks_hws(struct clk_hw ** const hws[]);
|
||||
void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count);
|
||||
|
||||
extern void imx_cscmr1_fixup(u32 *val);
|
||||
|
||||
|
@ -153,6 +154,23 @@ enum imx_pllv3_type {
|
|||
struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
|
||||
const char *parent_name, void __iomem *base, u32 div_mask);
|
||||
|
||||
#define PLL_1416X_RATE(_rate, _m, _p, _s) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
}
|
||||
|
||||
#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
|
||||
{ \
|
||||
.rate = (_rate), \
|
||||
.mdiv = (_m), \
|
||||
.pdiv = (_p), \
|
||||
.sdiv = (_s), \
|
||||
.kdiv = (_k), \
|
||||
}
|
||||
|
||||
struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
|
||||
void __iomem *base);
|
||||
|
||||
|
|
|
@ -283,7 +283,11 @@
|
|||
#define IMX_ADMA_LPCG_PWM_IPG_CLK 38
|
||||
#define IMX_ADMA_LPCG_LCD_PIX_CLK 39
|
||||
#define IMX_ADMA_LPCG_LCD_APB_CLK 40
|
||||
#define IMX_ADMA_LPCG_DSP_ADB_CLK 41
|
||||
#define IMX_ADMA_LPCG_DSP_IPG_CLK 42
|
||||
#define IMX_ADMA_LPCG_DSP_CORE_CLK 43
|
||||
#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
|
||||
|
||||
#define IMX_ADMA_LPCG_CLK_END 41
|
||||
#define IMX_ADMA_LPCG_CLK_END 45
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX_H */
|
||||
|
|
215
include/dt-bindings/clock/imx8mn-clock.h
Normal file
215
include/dt-bindings/clock/imx8mn-clock.h
Normal file
|
@ -0,0 +1,215 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8MN_H
|
||||
|
||||
#define IMX8MN_CLK_DUMMY 0
|
||||
#define IMX8MN_CLK_32K 1
|
||||
#define IMX8MN_CLK_24M 2
|
||||
#define IMX8MN_OSC_HDMI_CLK 3
|
||||
#define IMX8MN_CLK_EXT1 4
|
||||
#define IMX8MN_CLK_EXT2 5
|
||||
#define IMX8MN_CLK_EXT3 6
|
||||
#define IMX8MN_CLK_EXT4 7
|
||||
#define IMX8MN_AUDIO_PLL1_REF_SEL 8
|
||||
#define IMX8MN_AUDIO_PLL2_REF_SEL 9
|
||||
#define IMX8MN_VIDEO_PLL1_REF_SEL 10
|
||||
#define IMX8MN_DRAM_PLL_REF_SEL 11
|
||||
#define IMX8MN_GPU_PLL_REF_SEL 12
|
||||
#define IMX8MN_VPU_PLL_REF_SEL 13
|
||||
#define IMX8MN_ARM_PLL_REF_SEL 14
|
||||
#define IMX8MN_SYS_PLL1_REF_SEL 15
|
||||
#define IMX8MN_SYS_PLL2_REF_SEL 16
|
||||
#define IMX8MN_SYS_PLL3_REF_SEL 17
|
||||
#define IMX8MN_AUDIO_PLL1 18
|
||||
#define IMX8MN_AUDIO_PLL2 19
|
||||
#define IMX8MN_VIDEO_PLL1 20
|
||||
#define IMX8MN_DRAM_PLL 21
|
||||
#define IMX8MN_GPU_PLL 22
|
||||
#define IMX8MN_VPU_PLL 23
|
||||
#define IMX8MN_ARM_PLL 24
|
||||
#define IMX8MN_SYS_PLL1 25
|
||||
#define IMX8MN_SYS_PLL2 26
|
||||
#define IMX8MN_SYS_PLL3 27
|
||||
#define IMX8MN_AUDIO_PLL1_BYPASS 28
|
||||
#define IMX8MN_AUDIO_PLL2_BYPASS 29
|
||||
#define IMX8MN_VIDEO_PLL1_BYPASS 30
|
||||
#define IMX8MN_DRAM_PLL_BYPASS 31
|
||||
#define IMX8MN_GPU_PLL_BYPASS 32
|
||||
#define IMX8MN_VPU_PLL_BYPASS 33
|
||||
#define IMX8MN_ARM_PLL_BYPASS 34
|
||||
#define IMX8MN_SYS_PLL1_BYPASS 35
|
||||
#define IMX8MN_SYS_PLL2_BYPASS 36
|
||||
#define IMX8MN_SYS_PLL3_BYPASS 37
|
||||
#define IMX8MN_AUDIO_PLL1_OUT 38
|
||||
#define IMX8MN_AUDIO_PLL2_OUT 39
|
||||
#define IMX8MN_VIDEO_PLL1_OUT 40
|
||||
#define IMX8MN_DRAM_PLL_OUT 41
|
||||
#define IMX8MN_GPU_PLL_OUT 42
|
||||
#define IMX8MN_VPU_PLL_OUT 43
|
||||
#define IMX8MN_ARM_PLL_OUT 44
|
||||
#define IMX8MN_SYS_PLL1_OUT 45
|
||||
#define IMX8MN_SYS_PLL2_OUT 46
|
||||
#define IMX8MN_SYS_PLL3_OUT 47
|
||||
#define IMX8MN_SYS_PLL1_40M 48
|
||||
#define IMX8MN_SYS_PLL1_80M 49
|
||||
#define IMX8MN_SYS_PLL1_100M 50
|
||||
#define IMX8MN_SYS_PLL1_133M 51
|
||||
#define IMX8MN_SYS_PLL1_160M 52
|
||||
#define IMX8MN_SYS_PLL1_200M 53
|
||||
#define IMX8MN_SYS_PLL1_266M 54
|
||||
#define IMX8MN_SYS_PLL1_400M 55
|
||||
#define IMX8MN_SYS_PLL1_800M 56
|
||||
#define IMX8MN_SYS_PLL2_50M 57
|
||||
#define IMX8MN_SYS_PLL2_100M 58
|
||||
#define IMX8MN_SYS_PLL2_125M 59
|
||||
#define IMX8MN_SYS_PLL2_166M 60
|
||||
#define IMX8MN_SYS_PLL2_200M 61
|
||||
#define IMX8MN_SYS_PLL2_250M 62
|
||||
#define IMX8MN_SYS_PLL2_333M 63
|
||||
#define IMX8MN_SYS_PLL2_500M 64
|
||||
#define IMX8MN_SYS_PLL2_1000M 65
|
||||
|
||||
/* CORE CLOCK ROOT */
|
||||
#define IMX8MN_CLK_A53_SRC 66
|
||||
#define IMX8MN_CLK_GPU_CORE_SRC 67
|
||||
#define IMX8MN_CLK_GPU_SHADER_SRC 68
|
||||
#define IMX8MN_CLK_A53_CG 69
|
||||
#define IMX8MN_CLK_GPU_CORE_CG 70
|
||||
#define IMX8MN_CLK_GPU_SHADER_CG 71
|
||||
#define IMX8MN_CLK_A53_DIV 72
|
||||
#define IMX8MN_CLK_GPU_CORE_DIV 73
|
||||
#define IMX8MN_CLK_GPU_SHADER_DIV 74
|
||||
|
||||
/* BUS CLOCK ROOT */
|
||||
#define IMX8MN_CLK_MAIN_AXI 75
|
||||
#define IMX8MN_CLK_ENET_AXI 76
|
||||
#define IMX8MN_CLK_NAND_USDHC_BUS 77
|
||||
#define IMX8MN_CLK_DISP_AXI 78
|
||||
#define IMX8MN_CLK_DISP_APB 79
|
||||
#define IMX8MN_CLK_USB_BUS 80
|
||||
#define IMX8MN_CLK_GPU_AXI 81
|
||||
#define IMX8MN_CLK_GPU_AHB 82
|
||||
#define IMX8MN_CLK_NOC 83
|
||||
#define IMX8MN_CLK_AHB 84
|
||||
#define IMX8MN_CLK_AUDIO_AHB 85
|
||||
|
||||
/* IPG CLOCK ROOT */
|
||||
#define IMX8MN_CLK_IPG_ROOT 86
|
||||
#define IMX8MN_CLK_IPG_AUDIO_ROOT 87
|
||||
|
||||
/* IP */
|
||||
#define IMX8MN_CLK_DRAM_CORE 88
|
||||
#define IMX8MN_CLK_DRAM_ALT 89
|
||||
#define IMX8MN_CLK_DRAM_APB 90
|
||||
#define IMX8MN_CLK_DRAM_ALT_ROOT 91
|
||||
#define IMX8MN_CLK_DISP_PIXEL 92
|
||||
#define IMX8MN_CLK_SAI2 93
|
||||
#define IMX8MN_CLK_SAI3 94
|
||||
#define IMX8MN_CLK_SAI5 95
|
||||
#define IMX8MN_CLK_SAI6 96
|
||||
#define IMX8MN_CLK_SPDIF1 97
|
||||
#define IMX8MN_CLK_ENET_REF 98
|
||||
#define IMX8MN_CLK_ENET_TIMER 99
|
||||
#define IMX8MN_CLK_ENET_PHY_REF 100
|
||||
#define IMX8MN_CLK_NAND 101
|
||||
#define IMX8MN_CLK_QSPI 102
|
||||
#define IMX8MN_CLK_USDHC1 103
|
||||
#define IMX8MN_CLK_USDHC2 104
|
||||
#define IMX8MN_CLK_I2C1 105
|
||||
#define IMX8MN_CLK_I2C2 106
|
||||
#define IMX8MN_CLK_I2C3 107
|
||||
#define IMX8MN_CLK_I2C4 118
|
||||
#define IMX8MN_CLK_UART1 119
|
||||
#define IMX8MN_CLK_UART2 110
|
||||
#define IMX8MN_CLK_UART3 111
|
||||
#define IMX8MN_CLK_UART4 112
|
||||
#define IMX8MN_CLK_USB_CORE_REF 113
|
||||
#define IMX8MN_CLK_USB_PHY_REF 114
|
||||
#define IMX8MN_CLK_ECSPI1 115
|
||||
#define IMX8MN_CLK_ECSPI2 116
|
||||
#define IMX8MN_CLK_PWM1 117
|
||||
#define IMX8MN_CLK_PWM2 118
|
||||
#define IMX8MN_CLK_PWM3 119
|
||||
#define IMX8MN_CLK_PWM4 120
|
||||
#define IMX8MN_CLK_WDOG 121
|
||||
#define IMX8MN_CLK_WRCLK 122
|
||||
#define IMX8MN_CLK_CLKO1 123
|
||||
#define IMX8MN_CLK_CLKO2 124
|
||||
#define IMX8MN_CLK_DSI_CORE 125
|
||||
#define IMX8MN_CLK_DSI_PHY_REF 126
|
||||
#define IMX8MN_CLK_DSI_DBI 127
|
||||
#define IMX8MN_CLK_USDHC3 128
|
||||
#define IMX8MN_CLK_CAMERA_PIXEL 129
|
||||
#define IMX8MN_CLK_CSI1_PHY_REF 130
|
||||
#define IMX8MN_CLK_CSI2_PHY_REF 131
|
||||
#define IMX8MN_CLK_CSI2_ESC 132
|
||||
#define IMX8MN_CLK_ECSPI3 133
|
||||
#define IMX8MN_CLK_PDM 134
|
||||
#define IMX8MN_CLK_SAI7 135
|
||||
|
||||
#define IMX8MN_CLK_ECSPI1_ROOT 136
|
||||
#define IMX8MN_CLK_ECSPI2_ROOT 137
|
||||
#define IMX8MN_CLK_ECSPI3_ROOT 138
|
||||
#define IMX8MN_CLK_ENET1_ROOT 139
|
||||
#define IMX8MN_CLK_GPIO1_ROOT 140
|
||||
#define IMX8MN_CLK_GPIO2_ROOT 141
|
||||
#define IMX8MN_CLK_GPIO3_ROOT 142
|
||||
#define IMX8MN_CLK_GPIO4_ROOT 143
|
||||
#define IMX8MN_CLK_GPIO5_ROOT 144
|
||||
#define IMX8MN_CLK_I2C1_ROOT 145
|
||||
#define IMX8MN_CLK_I2C2_ROOT 146
|
||||
#define IMX8MN_CLK_I2C3_ROOT 147
|
||||
#define IMX8MN_CLK_I2C4_ROOT 148
|
||||
#define IMX8MN_CLK_MU_ROOT 149
|
||||
#define IMX8MN_CLK_OCOTP_ROOT 150
|
||||
#define IMX8MN_CLK_PWM1_ROOT 151
|
||||
#define IMX8MN_CLK_PWM2_ROOT 152
|
||||
#define IMX8MN_CLK_PWM3_ROOT 153
|
||||
#define IMX8MN_CLK_PWM4_ROOT 154
|
||||
#define IMX8MN_CLK_QSPI_ROOT 155
|
||||
#define IMX8MN_CLK_NAND_ROOT 156
|
||||
#define IMX8MN_CLK_SAI2_ROOT 157
|
||||
#define IMX8MN_CLK_SAI2_IPG 158
|
||||
#define IMX8MN_CLK_SAI3_ROOT 159
|
||||
#define IMX8MN_CLK_SAI3_IPG 160
|
||||
#define IMX8MN_CLK_SAI5_ROOT 161
|
||||
#define IMX8MN_CLK_SAI5_IPG 162
|
||||
#define IMX8MN_CLK_SAI6_ROOT 163
|
||||
#define IMX8MN_CLK_SAI6_IPG 164
|
||||
#define IMX8MN_CLK_SAI7_ROOT 165
|
||||
#define IMX8MN_CLK_SAI7_IPG 166
|
||||
#define IMX8MN_CLK_SDMA1_ROOT 167
|
||||
#define IMX8MN_CLK_SDMA2_ROOT 168
|
||||
#define IMX8MN_CLK_UART1_ROOT 169
|
||||
#define IMX8MN_CLK_UART2_ROOT 170
|
||||
#define IMX8MN_CLK_UART3_ROOT 171
|
||||
#define IMX8MN_CLK_UART4_ROOT 172
|
||||
#define IMX8MN_CLK_USB1_CTRL_ROOT 173
|
||||
#define IMX8MN_CLK_USDHC1_ROOT 174
|
||||
#define IMX8MN_CLK_USDHC2_ROOT 175
|
||||
#define IMX8MN_CLK_WDOG1_ROOT 176
|
||||
#define IMX8MN_CLK_WDOG2_ROOT 177
|
||||
#define IMX8MN_CLK_WDOG3_ROOT 178
|
||||
#define IMX8MN_CLK_GPU_BUS_ROOT 179
|
||||
#define IMX8MN_CLK_ASRC_ROOT 180
|
||||
#define IMX8MN_CLK_GPU3D_ROOT 181
|
||||
#define IMX8MN_CLK_PDM_ROOT 182
|
||||
#define IMX8MN_CLK_PDM_IPG 183
|
||||
#define IMX8MN_CLK_DISP_AXI_ROOT 184
|
||||
#define IMX8MN_CLK_DISP_APB_ROOT 185
|
||||
#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
|
||||
#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
|
||||
#define IMX8MN_CLK_USDHC3_ROOT 188
|
||||
#define IMX8MN_CLK_SDMA3_ROOT 189
|
||||
#define IMX8MN_CLK_TMU_ROOT 190
|
||||
#define IMX8MN_CLK_ARM 191
|
||||
#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
|
||||
#define IMX8MN_CLK_GPU_CORE_ROOT 193
|
||||
|
||||
#define IMX8MN_CLK_END 194
|
||||
|
||||
#endif
|
Loading…
Reference in a new issue