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dt-bindings: clk: vc5: Fix example 

The example properties do not match the binding. Fix them, and prohibit
undocumented properties in clock nodes to prevent this from happening in
the future.

Fixes: 45c940184b ("dt-bindings: clk: versaclock5: convert to yaml")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20210607190546.2616259-1-sean.anderson@seco.com
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Sean Anderson 2021-06-07 15:05:46 -04:00 committed by Rob Herring
parent cdbbe6ce26
commit 89f8a707d0
1 changed files with 4 additions and 3 deletions
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7
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
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@ -86,6 +86,7 @@ patternProperties:
description: The Slew rate control for CMOS single-ended.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 80, 85, 90, 100 ]
additionalProperties: false
required:
- compatible
@ -141,13 +142,13 @@ examples:
clock-names = "xin";
OUT1 {
idt,drive-mode = <VC5_CMOSD>;
idt,voltage-microvolts = <1800000>;
idt,mode = <VC5_CMOSD>;
idt,voltage-microvolt = <1800000>;
idt,slew-percent = <80>;
};
OUT4 {
idt,drive-mode = <VC5_LVDS>;
idt,mode = <VC5_LVDS>;
};
};
};