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dt-bindings: clk: vc5: Fix example
The example properties do not match the binding. Fix them, and prohibit
undocumented properties in clock nodes to prevent this from happening in
the future.
Fixes: 45c940184b
("dt-bindings: clk: versaclock5: convert to yaml")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20210607190546.2616259-1-sean.anderson@seco.com
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
parent
cdbbe6ce26
commit
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1 changed files with 4 additions and 3 deletions
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@ -86,6 +86,7 @@ patternProperties:
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description: The Slew rate control for CMOS single-ended.
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description: The Slew rate control for CMOS single-ended.
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$ref: /schemas/types.yaml#/definitions/uint32
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 80, 85, 90, 100 ]
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enum: [ 80, 85, 90, 100 ]
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additionalProperties: false
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required:
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required:
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- compatible
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- compatible
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@ -141,13 +142,13 @@ examples:
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clock-names = "xin";
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clock-names = "xin";
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OUT1 {
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OUT1 {
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idt,drive-mode = <VC5_CMOSD>;
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idt,mode = <VC5_CMOSD>;
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idt,voltage-microvolts = <1800000>;
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idt,voltage-microvolt = <1800000>;
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idt,slew-percent = <80>;
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idt,slew-percent = <80>;
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};
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};
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OUT4 {
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OUT4 {
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idt,drive-mode = <VC5_LVDS>;
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idt,mode = <VC5_LVDS>;
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};
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};
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};
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};
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};
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};
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