mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 19:00:25 +00:00
Raw NAND controller drivers:
* Intel: Fix an error handling path in 'ebu_dma_start()' * Tango: Remove the driver * Marvell: Convert comma to semicolon * MXC: Convert comma to semicolon * Qcom: Add support for Qcom SMEM parser Related MTD changes: * parsers: Add Qcom SMEM parser -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAmAYQpEACgkQJWrqGEe9 VoQ94gf+K9XjYPbA6mOezHSp4P7RHS6qJVs5BByW//E8i6r7GxC8wFEgjmAxD2E0 /W7ZlZaKYElug/iqLKwo9VE0lcRMEBBrkWpGKzr3uNWZcBsjnXY73h5PEFxYBDbN kPlRv1UGpJ5vuxAzsK5IvHfxGpom76ASfh5oKejdW4bLf60b80trhvJZ9SyShCN/ kB0+yQ91I2jiH/a8mAOmuIkOgPutImjnAEbFh2NLTheqk859ylXCZuNObTNT1/XH G+9/1luFlaRVHabEJgB1qdoSBlI9rrmu9ZiReNniGjPxmfTo/ipidPlNJGDdRCki 0SNUeAYJWbHkEnZ7iNCQjT51KL393A== =obwS -----END PGP SIGNATURE----- Merge tag 'nand/for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next Raw NAND controller drivers: * Intel: Fix an error handling path in 'ebu_dma_start()' * Tango: Remove the driver * Marvell: Convert comma to semicolon * MXC: Convert comma to semicolon * Qcom: Add support for Qcom SMEM parser Related MTD changes: * parsers: Add Qcom SMEM parser
This commit is contained in:
commit
89fb650008
11 changed files with 221 additions and 740 deletions
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@ -0,0 +1,33 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/partitions/qcom,smem-part.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SMEM NAND flash partition parser binding
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description: |
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The Qualcomm SoCs supporting the NAND controller interface features a Shared
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Memory (SMEM) based partition table scheme. The maximum partitions supported
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varies between partition table revisions. V3 supports maximum 16 partitions
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and V4 supports 48 partitions.
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properties:
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compatible:
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const: qcom,smem-part
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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flash {
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partitions {
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compatible = "qcom,smem-part";
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};
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};
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@ -102,13 +102,6 @@ config MTD_NAND_S3C2410_CLKSTOP
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when the is NAND chip selected or released, but will save
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approximately 5mA of power when there is nothing happening.
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config MTD_NAND_TANGO
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tristate "Tango NAND controller"
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depends on ARCH_TANGO || COMPILE_TEST
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depends on HAS_IOMEM
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help
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Enables the NAND Flash controller on Tango chips.
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config MTD_NAND_SHARPSL
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tristate "Sharp SL Series (C7xx + others) NAND controller"
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depends on ARCH_PXA || COMPILE_TEST
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|
|
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@ -10,7 +10,6 @@ obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o
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obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o
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obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
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obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
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obj-$(CONFIG_MTD_NAND_TANGO) += tango_nand.o
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obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
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obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
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obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o
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|
|
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@ -318,8 +318,10 @@ static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir,
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}
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tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags);
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if (!tx)
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return -ENXIO;
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if (!tx) {
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ret = -ENXIO;
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goto err_unmap;
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}
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tx->callback = callback;
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tx->callback_param = ebu_host;
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|
|
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@ -2396,7 +2396,7 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
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* be greater than that to be sure tCCS delay is respected.
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*/
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nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
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period_ns) - 2,
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period_ns) - 2;
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nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
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period_ns);
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|
|
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@ -1731,7 +1731,7 @@ static int mxcnd_probe(struct platform_device *pdev)
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this->legacy.chip_delay = 5;
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nand_set_controller_data(this, host);
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nand_set_flash_node(this, pdev->dev.of_node),
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nand_set_flash_node(this, pdev->dev.of_node);
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this->legacy.dev_ready = mxc_nand_dev_ready;
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this->legacy.cmdfunc = mxc_nand_command;
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this->legacy.read_byte = mxc_nand_read_byte;
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|
|
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@ -2821,6 +2821,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
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return 0;
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}
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static const char * const probes[] = { "qcomsmem", NULL };
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static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
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struct qcom_nand_host *host,
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struct device_node *dn)
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@ -2884,7 +2886,7 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
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}
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}
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ret = mtd_device_register(mtd, NULL, 0);
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ret = mtd_device_parse_register(mtd, probes, NULL, NULL, 0);
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if (ret)
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nand_cleanup(chip);
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|
|
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@ -1,727 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2016 Sigma Designs
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/clk.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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/* Offsets relative to chip->base */
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#define PBUS_CMD 0
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#define PBUS_ADDR 4
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#define PBUS_DATA 8
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/* Offsets relative to reg_base */
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#define NFC_STATUS 0x00
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#define NFC_FLASH_CMD 0x04
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#define NFC_DEVICE_CFG 0x08
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#define NFC_TIMING1 0x0c
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#define NFC_TIMING2 0x10
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#define NFC_XFER_CFG 0x14
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#define NFC_PKT_0_CFG 0x18
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#define NFC_PKT_N_CFG 0x1c
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#define NFC_BB_CFG 0x20
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#define NFC_ADDR_PAGE 0x24
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#define NFC_ADDR_OFFSET 0x28
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#define NFC_XFER_STATUS 0x2c
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/* NFC_STATUS values */
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#define CMD_READY BIT(31)
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/* NFC_FLASH_CMD values */
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#define NFC_READ 1
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#define NFC_WRITE 2
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/* NFC_XFER_STATUS values */
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#define PAGE_IS_EMPTY BIT(16)
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/* Offsets relative to mem_base */
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#define METADATA 0x000
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#define ERROR_REPORT 0x1c0
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/*
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* Error reports are split in two bytes:
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* byte 0 for the first packet in the page (PKT_0)
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* byte 1 for other packets in the page (PKT_N, for N > 0)
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* ERR_COUNT_PKT_N is the max error count over all but the first packet.
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*/
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#define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f)
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#define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f)
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#define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0)
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#define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0)
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/* Offsets relative to pbus_base */
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#define PBUS_CS_CTRL 0x83c
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#define PBUS_PAD_MODE 0x8f0
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/* PBUS_CS_CTRL values */
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#define PBUS_IORDY BIT(31)
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/*
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* PBUS_PAD_MODE values
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* In raw mode, the driver communicates directly with the NAND chips.
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* In NFC mode, the NAND Flash controller manages the communication.
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* We use NFC mode for read and write; raw mode for everything else.
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*/
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#define MODE_RAW 0
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#define MODE_NFC BIT(31)
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#define METADATA_SIZE 4
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#define BBM_SIZE 6
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#define FIELD_ORDER 15
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#define MAX_CS 4
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struct tango_nfc {
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struct nand_controller hw;
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void __iomem *reg_base;
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void __iomem *mem_base;
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void __iomem *pbus_base;
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struct tango_chip *chips[MAX_CS];
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struct dma_chan *chan;
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int freq_kHz;
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};
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#define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw)
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struct tango_chip {
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struct nand_chip nand_chip;
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void __iomem *base;
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u32 timing1;
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u32 timing2;
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u32 xfer_cfg;
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u32 pkt_0_cfg;
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u32 pkt_n_cfg;
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u32 bb_cfg;
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};
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#define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip)
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#define XFER_CFG(cs, page_count, steps, metadata_size) \
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((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size))
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#define PKT_CFG(size, strength) ((size) << 16 | (strength))
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#define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size))
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#define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3))
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static void tango_select_target(struct nand_chip *chip, unsigned int cs)
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{
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struct tango_nfc *nfc = to_tango_nfc(chip->controller);
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struct tango_chip *tchip = to_tango_chip(chip);
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writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1);
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writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2);
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writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG);
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writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG);
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writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG);
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writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG);
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}
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static int tango_waitrdy(struct nand_chip *chip, unsigned int timeout_ms)
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{
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struct tango_nfc *nfc = to_tango_nfc(chip->controller);
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u32 status;
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return readl_relaxed_poll_timeout(nfc->pbus_base + PBUS_CS_CTRL,
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status, status & PBUS_IORDY, 20,
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timeout_ms);
|
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}
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static int tango_exec_instr(struct nand_chip *chip,
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const struct nand_op_instr *instr)
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{
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struct tango_chip *tchip = to_tango_chip(chip);
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unsigned int i;
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|
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switch (instr->type) {
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case NAND_OP_CMD_INSTR:
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writeb_relaxed(instr->ctx.cmd.opcode, tchip->base + PBUS_CMD);
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return 0;
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case NAND_OP_ADDR_INSTR:
|
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for (i = 0; i < instr->ctx.addr.naddrs; i++)
|
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writeb_relaxed(instr->ctx.addr.addrs[i],
|
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tchip->base + PBUS_ADDR);
|
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return 0;
|
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case NAND_OP_DATA_IN_INSTR:
|
||||
ioread8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.in,
|
||||
instr->ctx.data.len);
|
||||
return 0;
|
||||
case NAND_OP_DATA_OUT_INSTR:
|
||||
iowrite8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.out,
|
||||
instr->ctx.data.len);
|
||||
return 0;
|
||||
case NAND_OP_WAITRDY_INSTR:
|
||||
return tango_waitrdy(chip,
|
||||
instr->ctx.waitrdy.timeout_ms);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int tango_exec_op(struct nand_chip *chip,
|
||||
const struct nand_operation *op,
|
||||
bool check_only)
|
||||
{
|
||||
unsigned int i;
|
||||
int ret = 0;
|
||||
|
||||
if (check_only)
|
||||
return 0;
|
||||
|
||||
tango_select_target(chip, op->cs);
|
||||
for (i = 0; i < op->ninstrs; i++) {
|
||||
ret = tango_exec_instr(chip, &op->instrs[i]);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* The controller does not check for bitflips in erased pages,
|
||||
* therefore software must check instead.
|
||||
*/
|
||||
static int check_erased_page(struct nand_chip *chip, u8 *buf)
|
||||
{
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
u8 *meta = chip->oob_poi + BBM_SIZE;
|
||||
u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE;
|
||||
const int ecc_size = chip->ecc.bytes;
|
||||
const int pkt_size = chip->ecc.size;
|
||||
int i, res, meta_len, bitflips = 0;
|
||||
|
||||
for (i = 0; i < chip->ecc.steps; ++i) {
|
||||
meta_len = i ? 0 : METADATA_SIZE;
|
||||
res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
|
||||
meta, meta_len,
|
||||
chip->ecc.strength);
|
||||
if (res < 0)
|
||||
mtd->ecc_stats.failed++;
|
||||
else
|
||||
mtd->ecc_stats.corrected += res;
|
||||
|
||||
bitflips = max(res, bitflips);
|
||||
buf += pkt_size;
|
||||
ecc += ecc_size;
|
||||
}
|
||||
|
||||
return bitflips;
|
||||
}
|
||||
|
||||
static int decode_error_report(struct nand_chip *chip)
|
||||
{
|
||||
u32 status, res;
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
|
||||
|
||||
status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS);
|
||||
if (status & PAGE_IS_EMPTY)
|
||||
return 0;
|
||||
|
||||
res = readl_relaxed(nfc->mem_base + ERROR_REPORT);
|
||||
|
||||
if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res))
|
||||
return -EBADMSG;
|
||||
|
||||
/* ERR_COUNT_PKT_N is max, not sum, but that's all we have */
|
||||
mtd->ecc_stats.corrected +=
|
||||
ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res);
|
||||
|
||||
return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res));
|
||||
}
|
||||
|
||||
static void tango_dma_callback(void *arg)
|
||||
{
|
||||
complete(arg);
|
||||
}
|
||||
|
||||
static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd,
|
||||
const void *buf, int len, int page)
|
||||
{
|
||||
void __iomem *addr = nfc->reg_base + NFC_STATUS;
|
||||
struct dma_chan *chan = nfc->chan;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
enum dma_transfer_direction tdir;
|
||||
struct scatterlist sg;
|
||||
struct completion tx_done;
|
||||
int err = -EIO;
|
||||
u32 res, val;
|
||||
|
||||
sg_init_one(&sg, buf, len);
|
||||
if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1)
|
||||
return -EIO;
|
||||
|
||||
tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
|
||||
desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT);
|
||||
if (!desc)
|
||||
goto dma_unmap;
|
||||
|
||||
desc->callback = tango_dma_callback;
|
||||
desc->callback_param = &tx_done;
|
||||
init_completion(&tx_done);
|
||||
|
||||
writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE);
|
||||
|
||||
writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE);
|
||||
writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET);
|
||||
writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD);
|
||||
|
||||
dmaengine_submit(desc);
|
||||
dma_async_issue_pending(chan);
|
||||
|
||||
res = wait_for_completion_timeout(&tx_done, HZ);
|
||||
if (res > 0)
|
||||
err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000);
|
||||
|
||||
writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
|
||||
|
||||
dma_unmap:
|
||||
dma_unmap_sg(chan->device->dev, &sg, 1, dir);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int tango_read_page(struct nand_chip *chip, u8 *buf,
|
||||
int oob_required, int page)
|
||||
{
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
|
||||
int err, res, len = mtd->writesize;
|
||||
|
||||
tango_select_target(chip, chip->cur_cs);
|
||||
if (oob_required)
|
||||
chip->ecc.read_oob(chip, page);
|
||||
|
||||
err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
res = decode_error_report(chip);
|
||||
if (res < 0) {
|
||||
chip->ecc.read_oob_raw(chip, page);
|
||||
res = check_erased_page(chip, buf);
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static int tango_write_page(struct nand_chip *chip, const u8 *buf,
|
||||
int oob_required, int page)
|
||||
{
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
|
||||
const struct nand_sdr_timings *timings;
|
||||
int err, len = mtd->writesize;
|
||||
u8 status;
|
||||
|
||||
/* Calling tango_write_oob() would send PAGEPROG twice */
|
||||
if (oob_required)
|
||||
return -ENOTSUPP;
|
||||
|
||||
tango_select_target(chip, chip->cur_cs);
|
||||
writel_relaxed(0xffffffff, nfc->mem_base + METADATA);
|
||||
err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
timings = nand_get_sdr_timings(nand_get_interface_config(chip));
|
||||
err = tango_waitrdy(chip, PSEC_TO_MSEC(timings->tR_max));
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = nand_status_op(chip, &status);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return (status & NAND_STATUS_FAIL) ? -EIO : 0;
|
||||
}
|
||||
|
||||
static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos)
|
||||
{
|
||||
*pos += len;
|
||||
|
||||
if (!*buf) {
|
||||
/* skip over "len" bytes */
|
||||
nand_change_read_column_op(chip, *pos, NULL, 0, false);
|
||||
} else {
|
||||
struct tango_chip *tchip = to_tango_chip(chip);
|
||||
|
||||
ioread8_rep(tchip->base + PBUS_DATA, *buf, len);
|
||||
*buf += len;
|
||||
}
|
||||
}
|
||||
|
||||
static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos)
|
||||
{
|
||||
*pos += len;
|
||||
|
||||
if (!*buf) {
|
||||
/* skip over "len" bytes */
|
||||
nand_change_write_column_op(chip, *pos, NULL, 0, false);
|
||||
} else {
|
||||
struct tango_chip *tchip = to_tango_chip(chip);
|
||||
|
||||
iowrite8_rep(tchip->base + PBUS_DATA, *buf, len);
|
||||
*buf += len;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Physical page layout (not drawn to scale)
|
||||
*
|
||||
* NB: Bad Block Marker area splits PKT_N in two (N1, N2).
|
||||
*
|
||||
* +---+-----------------+-------+-----+-----------+-----+----+-------+
|
||||
* | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N |
|
||||
* +---+-----------------+-------+-----+-----------+-----+----+-------+
|
||||
*
|
||||
* Logical page layout:
|
||||
*
|
||||
* +-----+---+-------+-----+-------+
|
||||
* oob = | BBM | M | ECC_0 | ... | ECC_N |
|
||||
* +-----+---+-------+-----+-------+
|
||||
*
|
||||
* +-----------------+-----+-----------------+
|
||||
* buf = | PKT_0 | ... | PKT_N |
|
||||
* +-----------------+-----+-----------------+
|
||||
*/
|
||||
static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob)
|
||||
{
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
u8 *oob_orig = oob;
|
||||
const int page_size = mtd->writesize;
|
||||
const int ecc_size = chip->ecc.bytes;
|
||||
const int pkt_size = chip->ecc.size;
|
||||
int pos = 0; /* position within physical page */
|
||||
int rem = page_size; /* bytes remaining until BBM area */
|
||||
|
||||
if (oob)
|
||||
oob += BBM_SIZE;
|
||||
|
||||
aux_read(chip, &oob, METADATA_SIZE, &pos);
|
||||
|
||||
while (rem > pkt_size) {
|
||||
aux_read(chip, &buf, pkt_size, &pos);
|
||||
aux_read(chip, &oob, ecc_size, &pos);
|
||||
rem = page_size - pos;
|
||||
}
|
||||
|
||||
aux_read(chip, &buf, rem, &pos);
|
||||
aux_read(chip, &oob_orig, BBM_SIZE, &pos);
|
||||
aux_read(chip, &buf, pkt_size - rem, &pos);
|
||||
aux_read(chip, &oob, ecc_size, &pos);
|
||||
}
|
||||
|
||||
static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
|
||||
{
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
const u8 *oob_orig = oob;
|
||||
const int page_size = mtd->writesize;
|
||||
const int ecc_size = chip->ecc.bytes;
|
||||
const int pkt_size = chip->ecc.size;
|
||||
int pos = 0; /* position within physical page */
|
||||
int rem = page_size; /* bytes remaining until BBM area */
|
||||
|
||||
if (oob)
|
||||
oob += BBM_SIZE;
|
||||
|
||||
aux_write(chip, &oob, METADATA_SIZE, &pos);
|
||||
|
||||
while (rem > pkt_size) {
|
||||
aux_write(chip, &buf, pkt_size, &pos);
|
||||
aux_write(chip, &oob, ecc_size, &pos);
|
||||
rem = page_size - pos;
|
||||
}
|
||||
|
||||
aux_write(chip, &buf, rem, &pos);
|
||||
aux_write(chip, &oob_orig, BBM_SIZE, &pos);
|
||||
aux_write(chip, &buf, pkt_size - rem, &pos);
|
||||
aux_write(chip, &oob, ecc_size, &pos);
|
||||
}
|
||||
|
||||
static int tango_read_page_raw(struct nand_chip *chip, u8 *buf,
|
||||
int oob_required, int page)
|
||||
{
|
||||
tango_select_target(chip, chip->cur_cs);
|
||||
nand_read_page_op(chip, page, 0, NULL, 0);
|
||||
raw_read(chip, buf, chip->oob_poi);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf,
|
||||
int oob_required, int page)
|
||||
{
|
||||
tango_select_target(chip, chip->cur_cs);
|
||||
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
|
||||
raw_write(chip, buf, chip->oob_poi);
|
||||
return nand_prog_page_end_op(chip);
|
||||
}
|
||||
|
||||
static int tango_read_oob(struct nand_chip *chip, int page)
|
||||
{
|
||||
tango_select_target(chip, chip->cur_cs);
|
||||
nand_read_page_op(chip, page, 0, NULL, 0);
|
||||
raw_read(chip, NULL, chip->oob_poi);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tango_write_oob(struct nand_chip *chip, int page)
|
||||
{
|
||||
tango_select_target(chip, chip->cur_cs);
|
||||
nand_prog_page_begin_op(chip, page, 0, NULL, 0);
|
||||
raw_write(chip, NULL, chip->oob_poi);
|
||||
return nand_prog_page_end_op(chip);
|
||||
}
|
||||
|
||||
static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
||||
|
||||
if (idx >= ecc->steps)
|
||||
return -ERANGE;
|
||||
|
||||
res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx;
|
||||
res->length = ecc->bytes;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
|
||||
{
|
||||
return -ERANGE; /* no free space in spare area */
|
||||
}
|
||||
|
||||
static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = {
|
||||
.ecc = oob_ecc,
|
||||
.free = oob_free,
|
||||
};
|
||||
|
||||
static u32 to_ticks(int kHz, int ps)
|
||||
{
|
||||
return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC);
|
||||
}
|
||||
|
||||
static int tango_set_timings(struct nand_chip *chip, int csline,
|
||||
const struct nand_interface_config *conf)
|
||||
{
|
||||
const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
|
||||
struct tango_nfc *nfc = to_tango_nfc(chip->controller);
|
||||
struct tango_chip *tchip = to_tango_chip(chip);
|
||||
u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr;
|
||||
int kHz = nfc->freq_kHz;
|
||||
|
||||
if (IS_ERR(sdr))
|
||||
return PTR_ERR(sdr);
|
||||
|
||||
if (csline == NAND_DATA_IFACE_CHECK_ONLY)
|
||||
return 0;
|
||||
|
||||
Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max);
|
||||
Textw = to_ticks(kHz, sdr->tWB_max);
|
||||
Twc = to_ticks(kHz, sdr->tWC_min);
|
||||
Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min);
|
||||
|
||||
Tacc = to_ticks(kHz, sdr->tREA_max);
|
||||
Thold = to_ticks(kHz, sdr->tREH_min);
|
||||
Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min);
|
||||
Textr = to_ticks(kHz, sdr->tRHZ_max);
|
||||
|
||||
tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw);
|
||||
tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tango_attach_chip(struct nand_chip *chip)
|
||||
{
|
||||
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
||||
|
||||
ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
|
||||
ecc->algo = NAND_ECC_ALGO_BCH;
|
||||
ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE);
|
||||
|
||||
ecc->read_page_raw = tango_read_page_raw;
|
||||
ecc->write_page_raw = tango_write_page_raw;
|
||||
ecc->read_page = tango_read_page;
|
||||
ecc->write_page = tango_write_page;
|
||||
ecc->read_oob = tango_read_oob;
|
||||
ecc->write_oob = tango_write_oob;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct nand_controller_ops tango_controller_ops = {
|
||||
.attach_chip = tango_attach_chip,
|
||||
.setup_interface = tango_set_timings,
|
||||
.exec_op = tango_exec_op,
|
||||
};
|
||||
|
||||
static int chip_init(struct device *dev, struct device_node *np)
|
||||
{
|
||||
u32 cs;
|
||||
int err, res;
|
||||
struct mtd_info *mtd;
|
||||
struct nand_chip *chip;
|
||||
struct tango_chip *tchip;
|
||||
struct nand_ecc_ctrl *ecc;
|
||||
struct tango_nfc *nfc = dev_get_drvdata(dev);
|
||||
|
||||
tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL);
|
||||
if (!tchip)
|
||||
return -ENOMEM;
|
||||
|
||||
res = of_property_count_u32_elems(np, "reg");
|
||||
if (res < 0)
|
||||
return res;
|
||||
|
||||
if (res != 1)
|
||||
return -ENOTSUPP; /* Multi-CS chips are not supported */
|
||||
|
||||
err = of_property_read_u32_index(np, "reg", 0, &cs);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (cs >= MAX_CS)
|
||||
return -EINVAL;
|
||||
|
||||
chip = &tchip->nand_chip;
|
||||
ecc = &chip->ecc;
|
||||
mtd = nand_to_mtd(chip);
|
||||
|
||||
chip->options = NAND_USES_DMA |
|
||||
NAND_NO_SUBPAGE_WRITE |
|
||||
NAND_WAIT_TCCS;
|
||||
chip->controller = &nfc->hw;
|
||||
tchip->base = nfc->pbus_base + (cs * 256);
|
||||
|
||||
nand_set_flash_node(chip, np);
|
||||
mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops);
|
||||
mtd->dev.parent = dev;
|
||||
|
||||
err = nand_scan(chip, 1);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE);
|
||||
tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength);
|
||||
tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength);
|
||||
tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE);
|
||||
|
||||
err = mtd_device_register(mtd, NULL, 0);
|
||||
if (err) {
|
||||
nand_cleanup(chip);
|
||||
return err;
|
||||
}
|
||||
|
||||
nfc->chips[cs] = tchip;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tango_nand_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tango_nfc *nfc = platform_get_drvdata(pdev);
|
||||
struct nand_chip *chip;
|
||||
int cs, ret;
|
||||
|
||||
dma_release_channel(nfc->chan);
|
||||
|
||||
for (cs = 0; cs < MAX_CS; ++cs) {
|
||||
if (nfc->chips[cs]) {
|
||||
chip = &nfc->chips[cs]->nand_chip;
|
||||
ret = mtd_device_unregister(nand_to_mtd(chip));
|
||||
WARN_ON(ret);
|
||||
nand_cleanup(chip);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tango_nand_probe(struct platform_device *pdev)
|
||||
{
|
||||
int err;
|
||||
struct clk *clk;
|
||||
struct resource *res;
|
||||
struct tango_nfc *nfc;
|
||||
struct device_node *np;
|
||||
|
||||
nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
|
||||
if (!nfc)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
nfc->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(nfc->reg_base))
|
||||
return PTR_ERR(nfc->reg_base);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
nfc->mem_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(nfc->mem_base))
|
||||
return PTR_ERR(nfc->mem_base);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||||
nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(nfc->pbus_base))
|
||||
return PTR_ERR(nfc->pbus_base);
|
||||
|
||||
writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
|
||||
|
||||
clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
nfc->chan = dma_request_chan(&pdev->dev, "rxtx");
|
||||
if (IS_ERR(nfc->chan))
|
||||
return PTR_ERR(nfc->chan);
|
||||
|
||||
platform_set_drvdata(pdev, nfc);
|
||||
nand_controller_init(&nfc->hw);
|
||||
nfc->hw.ops = &tango_controller_ops;
|
||||
nfc->freq_kHz = clk_get_rate(clk) / 1000;
|
||||
|
||||
for_each_child_of_node(pdev->dev.of_node, np) {
|
||||
err = chip_init(&pdev->dev, np);
|
||||
if (err) {
|
||||
tango_nand_remove(pdev);
|
||||
of_node_put(np);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id tango_nand_ids[] = {
|
||||
{ .compatible = "sigma,smp8758-nand" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tango_nand_ids);
|
||||
|
||||
static struct platform_driver tango_nand_driver = {
|
||||
.probe = tango_nand_probe,
|
||||
.remove = tango_nand_remove,
|
||||
.driver = {
|
||||
.name = "tango-nand",
|
||||
.of_match_table = tango_nand_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(tango_nand_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Sigma Designs");
|
||||
MODULE_DESCRIPTION("Tango4 NAND Flash controller driver");
|
|
@ -160,3 +160,11 @@ config MTD_REDBOOT_PARTS_READONLY
|
|||
'FIS directory' images, enable this option.
|
||||
|
||||
endif # MTD_REDBOOT_PARTS
|
||||
|
||||
config MTD_QCOMSMEM_PARTS
|
||||
tristate "Qualcomm SMEM NAND flash partition parser"
|
||||
depends on MTD_NAND_QCOM || COMPILE_TEST
|
||||
depends on QCOM_SMEM
|
||||
help
|
||||
This provides support for parsing partitions from Shared Memory (SMEM)
|
||||
for NAND flash on Qualcomm platforms.
|
||||
|
|
|
@ -9,3 +9,4 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
|
|||
obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o
|
||||
obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o
|
||||
obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
|
||||
obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o
|
||||
|
|
170
drivers/mtd/parsers/qcomsmempart.c
Normal file
170
drivers/mtd/parsers/qcomsmempart.c
Normal file
|
@ -0,0 +1,170 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Qualcomm SMEM NAND flash partition parser
|
||||
*
|
||||
* Copyright (C) 2020, Linaro Ltd.
|
||||
*/
|
||||
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/soc/qcom/smem.h>
|
||||
|
||||
#define SMEM_AARM_PARTITION_TABLE 9
|
||||
#define SMEM_APPS 0
|
||||
|
||||
#define SMEM_FLASH_PART_MAGIC1 0x55ee73aa
|
||||
#define SMEM_FLASH_PART_MAGIC2 0xe35ebddb
|
||||
#define SMEM_FLASH_PTABLE_V3 3
|
||||
#define SMEM_FLASH_PTABLE_V4 4
|
||||
#define SMEM_FLASH_PTABLE_MAX_PARTS_V3 16
|
||||
#define SMEM_FLASH_PTABLE_MAX_PARTS_V4 48
|
||||
#define SMEM_FLASH_PTABLE_HDR_LEN (4 * sizeof(u32))
|
||||
#define SMEM_FLASH_PTABLE_NAME_SIZE 16
|
||||
|
||||
/**
|
||||
* struct smem_flash_pentry - SMEM Flash partition entry
|
||||
* @name: Name of the partition
|
||||
* @offset: Offset in blocks
|
||||
* @length: Length of the partition in blocks
|
||||
* @attr: Flags for this partition
|
||||
*/
|
||||
struct smem_flash_pentry {
|
||||
char name[SMEM_FLASH_PTABLE_NAME_SIZE];
|
||||
__le32 offset;
|
||||
__le32 length;
|
||||
u8 attr;
|
||||
} __packed __aligned(4);
|
||||
|
||||
/**
|
||||
* struct smem_flash_ptable - SMEM Flash partition table
|
||||
* @magic1: Partition table Magic 1
|
||||
* @magic2: Partition table Magic 2
|
||||
* @version: Partition table version
|
||||
* @numparts: Number of partitions in this ptable
|
||||
* @pentry: Flash partition entries belonging to this ptable
|
||||
*/
|
||||
struct smem_flash_ptable {
|
||||
__le32 magic1;
|
||||
__le32 magic2;
|
||||
__le32 version;
|
||||
__le32 numparts;
|
||||
struct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4];
|
||||
} __packed __aligned(4);
|
||||
|
||||
static int parse_qcomsmem_part(struct mtd_info *mtd,
|
||||
const struct mtd_partition **pparts,
|
||||
struct mtd_part_parser_data *data)
|
||||
{
|
||||
struct smem_flash_pentry *pentry;
|
||||
struct smem_flash_ptable *ptable;
|
||||
size_t len = SMEM_FLASH_PTABLE_HDR_LEN;
|
||||
struct mtd_partition *parts;
|
||||
int ret, i, numparts;
|
||||
char *name, *c;
|
||||
|
||||
pr_debug("Parsing partition table info from SMEM\n");
|
||||
ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);
|
||||
if (IS_ERR(ptable)) {
|
||||
pr_err("Error reading partition table header\n");
|
||||
return PTR_ERR(ptable);
|
||||
}
|
||||
|
||||
/* Verify ptable magic */
|
||||
if (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 ||
|
||||
le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) {
|
||||
pr_err("Partition table magic verification failed\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Ensure that # of partitions is less than the max we have allocated */
|
||||
numparts = le32_to_cpu(ptable->numparts);
|
||||
if (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) {
|
||||
pr_err("Partition numbers exceed the max limit\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Find out length of partition data based on table version */
|
||||
if (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) {
|
||||
len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 *
|
||||
sizeof(struct smem_flash_pentry);
|
||||
} else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) {
|
||||
len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 *
|
||||
sizeof(struct smem_flash_pentry);
|
||||
} else {
|
||||
pr_err("Unknown ptable version (%d)", le32_to_cpu(ptable->version));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Now that the partition table header has been parsed, verified
|
||||
* and the length of the partition table calculated, read the
|
||||
* complete partition table
|
||||
*/
|
||||
ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);
|
||||
if (IS_ERR_OR_NULL(ptable)) {
|
||||
pr_err("Error reading partition table\n");
|
||||
return PTR_ERR(ptable);
|
||||
}
|
||||
|
||||
parts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL);
|
||||
if (!parts)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < numparts; i++) {
|
||||
pentry = &ptable->pentry[i];
|
||||
if (pentry->name[0] == '\0')
|
||||
continue;
|
||||
|
||||
name = kstrdup(pentry->name, GFP_KERNEL);
|
||||
if (!name) {
|
||||
ret = -ENOMEM;
|
||||
goto out_free_parts;
|
||||
}
|
||||
|
||||
/* Convert name to lower case */
|
||||
for (c = name; *c != '\0'; c++)
|
||||
*c = tolower(*c);
|
||||
|
||||
parts[i].name = name;
|
||||
parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize;
|
||||
parts[i].mask_flags = pentry->attr;
|
||||
parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize;
|
||||
pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n",
|
||||
i, pentry->name, le32_to_cpu(pentry->offset),
|
||||
le32_to_cpu(pentry->length), pentry->attr);
|
||||
}
|
||||
|
||||
pr_debug("SMEM partition table found: ver: %d len: %d\n",
|
||||
le32_to_cpu(ptable->version), numparts);
|
||||
*pparts = parts;
|
||||
|
||||
return numparts;
|
||||
|
||||
out_free_parts:
|
||||
while (--i >= 0)
|
||||
kfree(parts[i].name);
|
||||
kfree(parts);
|
||||
*pparts = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id qcomsmem_of_match_table[] = {
|
||||
{ .compatible = "qcom,smem-part" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table);
|
||||
|
||||
static struct mtd_part_parser mtd_parser_qcomsmem = {
|
||||
.parse_fn = parse_qcomsmem_part,
|
||||
.name = "qcomsmem",
|
||||
.of_match_table = qcomsmem_of_match_table,
|
||||
};
|
||||
module_mtd_part_parser(mtd_parser_qcomsmem);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
|
||||
MODULE_DESCRIPTION("Qualcomm SMEM NAND flash partition parser");
|
Loading…
Reference in a new issue