mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 01:10:04 +00:00
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "radeon, i915 and nouveau fixes, all fixes for regressions or black screens, or possible oopses" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon: lower the ref * post PLL maximum drm/radeon: check that we have a clock before PLL setup drm/radeon: drm/radeon: add missing radeon_semaphore_free to error path drm/radeon: Fix num_banks calculation for SI agp: info leak in agpioc_info_wrap() drm/gm107/gr: bump attrib cb size quite a bit drm/nouveau: fix another lock unbalance in nouveau_crtc_page_flip drm/nouveau/bios: fix shadowing from PROM on big-endian systems drm/nouveau/acpi: allow non-optimus setups to load vbios from acpi drm/radeon/dp: check for errors in dpcd reads drm/radeon: avoid high jitter with small frac divs drm/radeon: check buffer relocation offset drm/radeon: use pflip irq on R600+ v2 drm/radeon/uvd: use lower clocks on old UVD to boot v2 drm/i915: don't try DP_LINK_BW_5_4 on HSW ULX drm/i915: Sanitize the enable_ppgtt module option once drm/i915: Break encoder->crtc link separately in intel_sanitize_crtc()
This commit is contained in:
commit
8a207d3e84
25 changed files with 294 additions and 87 deletions
|
@ -1954,6 +1954,9 @@ struct drm_i915_cmd_table {
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#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
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#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
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((dev)->pdev->device & 0x00F0) == 0x0020)
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/* ULX machines are also considered ULT. */
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#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
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(dev)->pdev->device == 0x0A1E)
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#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
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/*
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|
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@ -34,25 +34,35 @@ static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
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bool intel_enable_ppgtt(struct drm_device *dev, bool full)
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{
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if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
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if (i915.enable_ppgtt == 0)
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return false;
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if (i915.enable_ppgtt == 1 && full)
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return false;
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return true;
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}
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static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
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{
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if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
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return 0;
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if (enable_ppgtt == 1)
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return 1;
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if (enable_ppgtt == 2 && HAS_PPGTT(dev))
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return 2;
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#ifdef CONFIG_INTEL_IOMMU
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/* Disable ppgtt on SNB if VT-d is on. */
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if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
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DRM_INFO("Disabling PPGTT because VT-d is on\n");
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return false;
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return 0;
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}
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#endif
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/* Full ppgtt disabled by default for now due to issues. */
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if (full)
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return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2);
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else
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return HAS_ALIASING_PPGTT(dev);
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return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
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}
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#define GEN6_PPGTT_PD_ENTRIES 512
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@ -2031,6 +2041,14 @@ int i915_gem_gtt_init(struct drm_device *dev)
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gtt->base.total >> 20);
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DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
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DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
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/*
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* i915.enable_ppgtt is read-only, so do an early pass to validate the
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* user's requested state against the hardware/driver capabilities. We
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* do this now so that we can print out any log messages once rather
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* than every time we check intel_enable_ppgtt().
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*/
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i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
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DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
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return 0;
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}
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@ -11395,15 +11395,6 @@ void intel_modeset_init(struct drm_device *dev)
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}
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}
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static void
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intel_connector_break_all_links(struct intel_connector *connector)
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{
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connector->base.dpms = DRM_MODE_DPMS_OFF;
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connector->base.encoder = NULL;
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connector->encoder->connectors_active = false;
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connector->encoder->base.crtc = NULL;
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}
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static void intel_enable_pipe_a(struct drm_device *dev)
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{
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struct intel_connector *connector;
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@ -11485,8 +11476,17 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
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if (connector->encoder->base.crtc != &crtc->base)
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continue;
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intel_connector_break_all_links(connector);
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connector->base.dpms = DRM_MODE_DPMS_OFF;
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connector->base.encoder = NULL;
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}
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/* multiple connectors may have the same encoder:
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* handle them and break crtc link separately */
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list_for_each_entry(connector, &dev->mode_config.connector_list,
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base.head)
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if (connector->encoder->base.crtc == &crtc->base) {
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connector->encoder->base.crtc = NULL;
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connector->encoder->connectors_active = false;
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}
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WARN_ON(crtc->active);
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crtc->base.enabled = false;
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@ -11568,6 +11568,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
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drm_get_encoder_name(&encoder->base));
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encoder->disable(encoder);
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}
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encoder->base.crtc = NULL;
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encoder->connectors_active = false;
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/* Inconsistent output/port/pipe state happens presumably due to
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* a bug in one of the get_hw_state functions. Or someplace else
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@ -11578,8 +11580,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
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base.head) {
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if (connector->encoder != encoder)
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continue;
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intel_connector_break_all_links(connector);
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connector->base.dpms = DRM_MODE_DPMS_OFF;
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connector->base.encoder = NULL;
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}
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}
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/* Enabled encoders without active connectors will be fixed in
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|
|
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@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
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case DP_LINK_BW_2_7:
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break;
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case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
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if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
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if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
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INTEL_INFO(dev)->gen >= 8) &&
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intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
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max_link_bw = DP_LINK_BW_5_4;
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else
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|
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@ -863,7 +863,7 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
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{
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mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
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mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
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mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
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mmio_data(0x200000, 0x1000, NV_MEM_ACCESS_RW);
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mmio_list(0x40800c, 0x00000000, 8, 1);
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mmio_list(0x408010, 0x80000000, 0, 0);
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@ -877,6 +877,8 @@ gm107_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
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mmio_list(0x418e24, 0x00000000, 8, 0);
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mmio_list(0x418e28, 0x80000030, 0, 0);
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mmio_list(0x4064c8, 0x018002c0, 0, 0);
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mmio_list(0x418810, 0x80000000, 12, 2);
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mmio_list(0x419848, 0x10000000, 12, 2);
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mmio_list(0x419c2c, 0x10000000, 12, 2);
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@ -168,7 +168,8 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
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*/
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i = 16;
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do {
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if ((nv_rd32(bios, 0x300000) & 0xffff) == 0xaa55)
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u32 data = le32_to_cpu(nv_rd32(bios, 0x300000)) & 0xffff;
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if (data == 0xaa55)
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break;
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} while (i--);
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@ -176,14 +177,15 @@ nouveau_bios_shadow_prom(struct nouveau_bios *bios)
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goto out;
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/* read entire bios image to system memory */
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bios->size = ((nv_rd32(bios, 0x300000) >> 16) & 0xff) * 512;
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bios->size = (le32_to_cpu(nv_rd32(bios, 0x300000)) >> 16) & 0xff;
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bios->size = bios->size * 512;
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if (!bios->size)
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goto out;
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bios->data = kmalloc(bios->size, GFP_KERNEL);
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if (bios->data) {
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for (i = 0; i < bios->size; i+=4)
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nv_wo32(bios, i, nv_rd32(bios, 0x300000 + i));
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for (i = 0; i < bios->size; i += 4)
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((u32 *)bios->data)[i/4] = nv_rd32(bios, 0x300000 + i);
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}
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/* check the PCI record header */
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@ -389,9 +389,6 @@ bool nouveau_acpi_rom_supported(struct pci_dev *pdev)
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acpi_status status;
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acpi_handle dhandle, rom_handle;
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if (!nouveau_dsm_priv.dsm_detected && !nouveau_dsm_priv.optimus_detected)
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return false;
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dhandle = ACPI_HANDLE(&pdev->dev);
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if (!dhandle)
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return false;
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@ -764,9 +764,9 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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}
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ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence);
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mutex_unlock(&chan->cli->mutex);
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if (ret)
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goto fail_unreserve;
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mutex_unlock(&chan->cli->mutex);
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/* Update the crtc struct and cleanup */
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crtc->primary->fb = fb;
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|
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@ -1177,27 +1177,43 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
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/* Set NUM_BANKS. */
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if (rdev->family >= CHIP_TAHITI) {
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unsigned tileb, index, num_banks, tile_split_bytes;
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unsigned index, num_banks;
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/* Calculate the macrotile mode index. */
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tile_split_bytes = 64 << tile_split;
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tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
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tileb = min(tile_split_bytes, tileb);
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if (rdev->family >= CHIP_BONAIRE) {
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unsigned tileb, tile_split_bytes;
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for (index = 0; tileb > 64; index++) {
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tileb >>= 1;
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}
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/* Calculate the macrotile mode index. */
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tile_split_bytes = 64 << tile_split;
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tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
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tileb = min(tile_split_bytes, tileb);
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if (index >= 16) {
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DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
|
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target_fb->bits_per_pixel, tile_split);
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return -EINVAL;
|
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}
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for (index = 0; tileb > 64; index++)
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tileb >>= 1;
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|
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if (index >= 16) {
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DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
|
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target_fb->bits_per_pixel, tile_split);
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return -EINVAL;
|
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}
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|
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if (rdev->family >= CHIP_BONAIRE)
|
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num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
|
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else
|
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} else {
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switch (target_fb->bits_per_pixel) {
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case 8:
|
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index = 10;
|
||||
break;
|
||||
case 16:
|
||||
index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
|
||||
break;
|
||||
default:
|
||||
case 32:
|
||||
index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
|
||||
break;
|
||||
}
|
||||
|
||||
num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
|
||||
}
|
||||
|
||||
fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
|
||||
} else {
|
||||
/* NI and older. */
|
||||
|
@ -1885,6 +1901,9 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
|
|||
(ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
|
||||
is_tvcv = true;
|
||||
|
||||
if (!radeon_crtc->adjusted_clock)
|
||||
return -EINVAL;
|
||||
|
||||
atombios_crtc_set_pll(crtc, adjusted_mode);
|
||||
|
||||
if (ASIC_IS_DCE4(rdev))
|
||||
|
|
|
@ -366,11 +366,11 @@ static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
|
|||
if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
|
||||
return;
|
||||
|
||||
if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3))
|
||||
if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
|
||||
DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
|
||||
buf[0], buf[1], buf[2]);
|
||||
|
||||
if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3))
|
||||
if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
|
||||
DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
|
||||
buf[0], buf[1], buf[2]);
|
||||
}
|
||||
|
@ -419,21 +419,23 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
|
|||
|
||||
if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
|
||||
/* DP bridge chips */
|
||||
drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
|
||||
DP_EDP_CONFIGURATION_CAP, &tmp);
|
||||
if (tmp & 1)
|
||||
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
|
||||
else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
|
||||
(dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
|
||||
panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
|
||||
else
|
||||
panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
|
||||
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
|
||||
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
|
||||
if (tmp & 1)
|
||||
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
|
||||
else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
|
||||
(dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
|
||||
panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
|
||||
else
|
||||
panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
|
||||
}
|
||||
} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
|
||||
/* eDP */
|
||||
drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
|
||||
DP_EDP_CONFIGURATION_CAP, &tmp);
|
||||
if (tmp & 1)
|
||||
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
|
||||
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
|
||||
DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
|
||||
if (tmp & 1)
|
||||
panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
|
||||
}
|
||||
}
|
||||
|
||||
return panel_mode;
|
||||
|
@ -809,11 +811,15 @@ void radeon_dp_link_train(struct drm_encoder *encoder,
|
|||
else
|
||||
dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
|
||||
|
||||
drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp);
|
||||
if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
|
||||
dp_info.tp3_supported = true;
|
||||
else
|
||||
if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
|
||||
== 1) {
|
||||
if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
|
||||
dp_info.tp3_supported = true;
|
||||
else
|
||||
dp_info.tp3_supported = false;
|
||||
} else {
|
||||
dp_info.tp3_supported = false;
|
||||
}
|
||||
|
||||
memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
|
||||
dp_info.rdev = rdev;
|
||||
|
|
|
@ -3702,6 +3702,7 @@ int cik_copy_cpdma(struct radeon_device *rdev,
|
|||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
@ -6693,6 +6694,19 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
|
|||
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
||||
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
||||
}
|
||||
/* pflip */
|
||||
if (rdev->num_crtc >= 2) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
|
||||
}
|
||||
if (rdev->num_crtc >= 4) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
|
||||
}
|
||||
if (rdev->num_crtc >= 6) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
|
||||
}
|
||||
|
||||
/* dac hotplug */
|
||||
WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
|
||||
|
@ -7049,6 +7063,25 @@ int cik_irq_set(struct radeon_device *rdev)
|
|||
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
|
||||
}
|
||||
|
||||
if (rdev->num_crtc >= 2) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
}
|
||||
if (rdev->num_crtc >= 4) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
}
|
||||
if (rdev->num_crtc >= 6) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
}
|
||||
|
||||
WREG32(DC_HPD1_INT_CONTROL, hpd1);
|
||||
WREG32(DC_HPD2_INT_CONTROL, hpd2);
|
||||
WREG32(DC_HPD3_INT_CONTROL, hpd3);
|
||||
|
@ -7085,6 +7118,29 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
|
|||
rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
|
||||
rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
|
||||
|
||||
rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
|
||||
EVERGREEN_CRTC0_REGISTER_OFFSET);
|
||||
rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
|
||||
EVERGREEN_CRTC1_REGISTER_OFFSET);
|
||||
if (rdev->num_crtc >= 4) {
|
||||
rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
|
||||
EVERGREEN_CRTC2_REGISTER_OFFSET);
|
||||
rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
|
||||
EVERGREEN_CRTC3_REGISTER_OFFSET);
|
||||
}
|
||||
if (rdev->num_crtc >= 6) {
|
||||
rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
|
||||
EVERGREEN_CRTC4_REGISTER_OFFSET);
|
||||
rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
|
||||
EVERGREEN_CRTC5_REGISTER_OFFSET);
|
||||
}
|
||||
|
||||
if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
|
||||
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_CLEAR);
|
||||
if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
|
||||
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_CLEAR);
|
||||
if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
|
||||
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
|
||||
if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
|
||||
|
@ -7095,6 +7151,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
|
|||
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
|
||||
|
||||
if (rdev->num_crtc >= 4) {
|
||||
if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
|
||||
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_CLEAR);
|
||||
if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
|
||||
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_CLEAR);
|
||||
if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
|
||||
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
|
||||
if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
|
||||
|
@ -7106,6 +7168,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
if (rdev->num_crtc >= 6) {
|
||||
if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
|
||||
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_CLEAR);
|
||||
if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
|
||||
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_CLEAR);
|
||||
if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
|
||||
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
|
||||
if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
|
||||
|
@ -7457,6 +7525,15 @@ int cik_irq_process(struct radeon_device *rdev)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case 8: /* D1 page flip */
|
||||
case 10: /* D2 page flip */
|
||||
case 12: /* D3 page flip */
|
||||
case 14: /* D4 page flip */
|
||||
case 16: /* D5 page flip */
|
||||
case 18: /* D6 page flip */
|
||||
DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
|
||||
radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
|
||||
break;
|
||||
case 42: /* HPD hotplug */
|
||||
switch (src_data) {
|
||||
case 0:
|
||||
|
|
|
@ -562,6 +562,7 @@ int cik_copy_dma(struct radeon_device *rdev,
|
|||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
@ -888,6 +888,15 @@
|
|||
# define DC_HPD6_RX_INTERRUPT (1 << 18)
|
||||
#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
|
||||
|
||||
/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
|
||||
#define GRPH_INT_STATUS 0x6858
|
||||
# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
|
||||
# define GRPH_PFLIP_INT_CLEAR (1 << 8)
|
||||
/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
|
||||
#define GRPH_INT_CONTROL 0x685c
|
||||
# define GRPH_PFLIP_INT_MASK (1 << 0)
|
||||
# define GRPH_PFLIP_INT_TYPE (1 << 8)
|
||||
|
||||
#define DAC_AUTODETECT_INT_CONTROL 0x67c8
|
||||
|
||||
#define DC_HPD1_INT_STATUS 0x601c
|
||||
|
|
|
@ -4371,7 +4371,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
|
|||
u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
|
||||
u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
|
||||
u32 grbm_int_cntl = 0;
|
||||
u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
|
||||
u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
|
||||
u32 dma_cntl, dma_cntl1 = 0;
|
||||
u32 thermal_int = 0;
|
||||
|
@ -4554,15 +4553,21 @@ int evergreen_irq_set(struct radeon_device *rdev)
|
|||
WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
|
||||
}
|
||||
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
if (rdev->num_crtc >= 4) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
}
|
||||
if (rdev->num_crtc >= 6) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
}
|
||||
|
||||
WREG32(DC_HPD1_INT_CONTROL, hpd1);
|
||||
|
@ -4951,6 +4956,15 @@ int evergreen_irq_process(struct radeon_device *rdev)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case 8: /* D1 page flip */
|
||||
case 10: /* D2 page flip */
|
||||
case 12: /* D3 page flip */
|
||||
case 14: /* D4 page flip */
|
||||
case 16: /* D5 page flip */
|
||||
case 18: /* D6 page flip */
|
||||
DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
|
||||
radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
|
||||
break;
|
||||
case 42: /* HPD hotplug */
|
||||
switch (src_data) {
|
||||
case 0:
|
||||
|
|
|
@ -151,6 +151,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
|
|||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
@ -2839,6 +2839,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
|
|||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
@ -3505,7 +3506,6 @@ int r600_irq_set(struct radeon_device *rdev)
|
|||
u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
|
||||
u32 grbm_int_cntl = 0;
|
||||
u32 hdmi0, hdmi1;
|
||||
u32 d1grph = 0, d2grph = 0;
|
||||
u32 dma_cntl;
|
||||
u32 thermal_int = 0;
|
||||
|
||||
|
@ -3614,8 +3614,8 @@ int r600_irq_set(struct radeon_device *rdev)
|
|||
WREG32(CP_INT_CNTL, cp_int_cntl);
|
||||
WREG32(DMA_CNTL, dma_cntl);
|
||||
WREG32(DxMODE_INT_MASK, mode_int);
|
||||
WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
|
||||
WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
|
||||
WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
|
||||
WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRBM_INT_CNTL, grbm_int_cntl);
|
||||
if (ASIC_IS_DCE3(rdev)) {
|
||||
WREG32(DC_HPD1_INT_CONTROL, hpd1);
|
||||
|
@ -3918,6 +3918,14 @@ int r600_irq_process(struct radeon_device *rdev)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case 9: /* D1 pflip */
|
||||
DRM_DEBUG("IH: D1 flip\n");
|
||||
radeon_crtc_handle_flip(rdev, 0);
|
||||
break;
|
||||
case 11: /* D2 pflip */
|
||||
DRM_DEBUG("IH: D2 flip\n");
|
||||
radeon_crtc_handle_flip(rdev, 1);
|
||||
break;
|
||||
case 19: /* HPD/DAC hotplug */
|
||||
switch (src_data) {
|
||||
case 0:
|
||||
|
|
|
@ -489,6 +489,7 @@ int r600_copy_dma(struct radeon_device *rdev,
|
|||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
@ -730,6 +730,12 @@ struct cik_irq_stat_regs {
|
|||
u32 disp_int_cont4;
|
||||
u32 disp_int_cont5;
|
||||
u32 disp_int_cont6;
|
||||
u32 d1grph_int;
|
||||
u32 d2grph_int;
|
||||
u32 d3grph_int;
|
||||
u32 d4grph_int;
|
||||
u32 d5grph_int;
|
||||
u32 d6grph_int;
|
||||
};
|
||||
|
||||
union radeon_irq_stat_regs {
|
||||
|
|
|
@ -284,6 +284,10 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
|
|||
u32 update_pending;
|
||||
int vpos, hpos;
|
||||
|
||||
/* can happen during initialization */
|
||||
if (radeon_crtc == NULL)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&rdev->ddev->event_lock, flags);
|
||||
work = radeon_crtc->unpin_work;
|
||||
if (work == NULL ||
|
||||
|
@ -826,14 +830,14 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
|
|||
|
||||
/* make sure nominator is large enough */
|
||||
if (*nom < nom_min) {
|
||||
tmp = (nom_min + *nom - 1) / *nom;
|
||||
tmp = DIV_ROUND_UP(nom_min, *nom);
|
||||
*nom *= tmp;
|
||||
*den *= tmp;
|
||||
}
|
||||
|
||||
/* make sure the denominator is large enough */
|
||||
if (*den < den_min) {
|
||||
tmp = (den_min + *den - 1) / *den;
|
||||
tmp = DIV_ROUND_UP(den_min, *den);
|
||||
*nom *= tmp;
|
||||
*den *= tmp;
|
||||
}
|
||||
|
@ -858,7 +862,7 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
|
|||
unsigned *fb_div, unsigned *ref_div)
|
||||
{
|
||||
/* limit reference * post divider to a maximum */
|
||||
ref_div_max = min(210 / post_div, ref_div_max);
|
||||
ref_div_max = min(128 / post_div, ref_div_max);
|
||||
|
||||
/* get matching reference and feedback divider */
|
||||
*ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
|
||||
|
@ -993,6 +997,16 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
|
|||
/* this also makes sure that the reference divider is large enough */
|
||||
avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
|
||||
|
||||
/* avoid high jitter with small fractional dividers */
|
||||
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
|
||||
fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
|
||||
if (fb_div < fb_div_min) {
|
||||
unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
|
||||
fb_div *= tmp;
|
||||
ref_div *= tmp;
|
||||
}
|
||||
}
|
||||
|
||||
/* and finally save the result */
|
||||
if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
|
||||
*fb_div_p = fb_div / 10;
|
||||
|
|
|
@ -465,6 +465,10 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
|
|||
cmd = radeon_get_ib_value(p, p->idx) >> 1;
|
||||
|
||||
if (cmd < 0x4) {
|
||||
if (end <= start) {
|
||||
DRM_ERROR("invalid reloc offset %X!\n", offset);
|
||||
return -EINVAL;
|
||||
}
|
||||
if ((end - start) < buf_sizes[cmd]) {
|
||||
DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
|
||||
(unsigned)(end - start), buf_sizes[cmd]);
|
||||
|
|
|
@ -86,6 +86,7 @@ int rv770_copy_dma(struct radeon_device *rdev,
|
|||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
@ -5780,7 +5780,6 @@ int si_irq_set(struct radeon_device *rdev)
|
|||
u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
|
||||
u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
|
||||
u32 grbm_int_cntl = 0;
|
||||
u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
|
||||
u32 dma_cntl, dma_cntl1;
|
||||
u32 thermal_int = 0;
|
||||
|
||||
|
@ -5919,16 +5918,22 @@ int si_irq_set(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
if (rdev->num_crtc >= 2) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
}
|
||||
if (rdev->num_crtc >= 4) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
}
|
||||
if (rdev->num_crtc >= 6) {
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
|
||||
GRPH_PFLIP_INT_MASK);
|
||||
}
|
||||
|
||||
if (!ASIC_IS_NODCE(rdev)) {
|
||||
|
@ -6292,6 +6297,15 @@ int si_irq_process(struct radeon_device *rdev)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case 8: /* D1 page flip */
|
||||
case 10: /* D2 page flip */
|
||||
case 12: /* D3 page flip */
|
||||
case 14: /* D4 page flip */
|
||||
case 16: /* D5 page flip */
|
||||
case 18: /* D6 page flip */
|
||||
DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
|
||||
radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
|
||||
break;
|
||||
case 42: /* HPD hotplug */
|
||||
switch (src_data) {
|
||||
case 0:
|
||||
|
|
|
@ -213,6 +213,7 @@ int si_copy_dma(struct radeon_device *rdev,
|
|||
r = radeon_fence_emit(rdev, fence, ring->idx);
|
||||
if (r) {
|
||||
radeon_ring_unlock_undo(rdev, ring);
|
||||
radeon_semaphore_free(rdev, &sem, NULL);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
@ -83,7 +83,10 @@ int uvd_v1_0_init(struct radeon_device *rdev)
|
|||
int r;
|
||||
|
||||
/* raise clocks while booting up the VCPU */
|
||||
radeon_set_uvd_clocks(rdev, 53300, 40000);
|
||||
if (rdev->family < CHIP_RV740)
|
||||
radeon_set_uvd_clocks(rdev, 10000, 10000);
|
||||
else
|
||||
radeon_set_uvd_clocks(rdev, 53300, 40000);
|
||||
|
||||
r = uvd_v1_0_start(rdev);
|
||||
if (r)
|
||||
|
@ -407,7 +410,10 @@ int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
struct radeon_fence *fence = NULL;
|
||||
int r;
|
||||
|
||||
r = radeon_set_uvd_clocks(rdev, 53300, 40000);
|
||||
if (rdev->family < CHIP_RV740)
|
||||
r = radeon_set_uvd_clocks(rdev, 10000, 10000);
|
||||
else
|
||||
r = radeon_set_uvd_clocks(rdev, 53300, 40000);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
|
||||
return r;
|
||||
|
|
|
@ -191,8 +191,8 @@
|
|||
INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
|
||||
INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
|
||||
INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
|
||||
|
|
Loading…
Reference in a new issue