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Qualcomm ARM64 DT updates for 5.12

Browse source 
This introduces initial support for the new SM8350 platform, aka
 Snapdragon 888, and the MTP device for this.
 
 It adds PCIe, audio, display, GPU, HDMI watchdog, LLCC and PMIC ADC
 support to the SM8250 platform and RB5 in particular, as well as improve
 the definition of CPUs, thermal zones and fixes a few smaller issues.
 
 It introduces new Devicetree files for the Alcatel Idol 3, ASUS Zenfone
 2 Laser and BQ Aquaris X5, based on the MSM8916 platform.
 
 It contains an overhaul of the existing MSM8992 and MSM8994 platform
 files and introduces RPM power domains and SMP2P nodes. It adds
 touchscreen, additional regulators, microSD card support and adds the
 Sony Mobile Ivy, Karin, Suzuran and Satsuki devices. It joins the common
 parts of the Lumia 950 and 950XL and extend these with support for
 sensors, NFC, bluetooth, audio, microSD and Type-C mux pins.
 
 It introduces support for the OnePlus6 and 6t, adds the missing higher
 frequences for the SDM850 laptops, adds CPU cluster idle support on
 SM8150  and a few tweaks to the SC7180 platform.
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Merge tag 'qcom-arm64-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DT updates for 5.12

This introduces initial support for the new SM8350 platform, aka
Snapdragon 888, and the MTP device for this.

It adds PCIe, audio, display, GPU, HDMI watchdog, LLCC and PMIC ADC
support to the SM8250 platform and RB5 in particular, as well as improve
the definition of CPUs, thermal zones and fixes a few smaller issues.

It introduces new Devicetree files for the Alcatel Idol 3, ASUS Zenfone
2 Laser and BQ Aquaris X5, based on the MSM8916 platform.

It contains an overhaul of the existing MSM8992 and MSM8994 platform
files and introduces RPM power domains and SMP2P nodes. It adds
touchscreen, additional regulators, microSD card support and adds the
Sony Mobile Ivy, Karin, Suzuran and Satsuki devices. It joins the common
parts of the Lumia 950 and 950XL and extend these with support for
sensors, NFC, bluetooth, audio, microSD and Type-C mux pins.

It introduces support for the OnePlus6 and 6t, adds the missing higher
frequences for the SDM850 laptops, adds CPU cluster idle support on
SM8150  and a few tweaks to the SC7180 platform.

* tag 'qcom-arm64-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (100 commits)
  arm64: dts: qcom: msm8998: Use rpmpd definitions for opp table levels
  arm64: dts: qcom: msm8996: Add missing device_type under pcie[01]
  arm64: dts: qcom: sc7180: Add support for gpu fuse
  arm64: dts: qcom: msm8998: Disable some components by default
  arm64: dts: qcom: msm8998: Add capacity-dmips-mhz to CPU cores
  arm64: dts: qcom: msm8998: Add I2C pinctrl and fix BLSP2_I2C naming
  arm64: dts: qcom: msm8998: Add DMA to I2C hosts
  arm64: dts: qcom: msm8998: Merge in msm8998-pins.dtsi to msm8998.dtsi
  arm64: dts: msm8916: Fix reserved and rfsa nodes unit address
  arm64: dts: qcom: msm8994-octagon: Add AD7147 and APDS9930 sensors
  arm64: dts: qcom: msm8994-octagon: Add TAS2553 codec
  arm64: dts: qcom: msm8994-octagon: Add sensors on blsp1_i2c5
  arm64: dts: qcom: msm8994-octagon: Add NXP NFC node
  arm64: dts: qcom: msm8994-octagon: Add FM Radio and DDR regulator nodes
  arm64: dts: qcom: msm8994-octagon: Configure PON keys
  arm64: dts: qcom: msm8994-octagon: Configure Lattice iCE40 FPGA
  arm64: dts: qcom: msm8994-octagon: Add uSD card and disable HS400 on eMMC
  arm64: dts: qcom: msm8994-octagon: Configure HD3SS460 Type-C mux pins
  arm64: dts: qcom: msm8994-octagon: Add QCA6174 bluetooth
  arm64: dts: qcom: msm8994-octagon: Configure regulators
  ...

Link: https://lore.kernel.org/r/20210204052043.388621-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-02-09 17:53:44 +01:00
commit 8a2b1ec170
57 changed files with 6499 additions and 1348 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/cpus.yaml
View file

@ -169,6 +169,7 @@ properties:
- qcom,kryo385
- qcom,kryo468
- qcom,kryo485
- qcom,kryo685
- qcom,scorpion
enable-method:

6
Documentation/devicetree/bindings/arm/qcom.yaml
View file

@ -41,6 +41,7 @@ description: |
sdm660
sdm845
sm8250
sm8350
The 'board' element must be one of the following strings:
@ -178,6 +179,11 @@ properties:
- qcom,sm8250-mtp
- const: qcom,sm8250
- items:
- enum:
- qcom,sm8350-mtp
- const: qcom,sm8350
additionalProperties: true
...

2
Documentation/devicetree/bindings/firmware/qcom,scm.txt
View file

@ -22,6 +22,8 @@ Required properties:
* "qcom,scm-sc7180"
* "qcom,scm-sdm845"
* "qcom,scm-sm8150"
* "qcom,scm-sm8250"
* "qcom,scm-sm8350"
and:
* "qcom,scm"
- clocks: Specifies clocks needed by the SCM interface, if any:

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View file

@ -59,6 +59,8 @@ patternProperties:
description: Aeroflex Gaisler AB
"^al,.*":
description: Annapurna Labs
"^alcatel,.*":
description: Alcatel
"^allegro,.*":
description: Allegro DVT
"^allo,.*":

15
arch/arm64/boot/dts/qcom/Makefile
View file

@ -1,19 +1,27 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-cityman.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-octagon-cityman.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
@ -43,9 +51,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb

4
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file

@ -301,6 +301,10 @@ &lpass {
status = "okay";
};
&mdss {
status = "okay";
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;

23
arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
/dts-v1/;
/* As the names may imply, there is quite a bunch of duplication there. */
#include "msm8994-sony-xperia-kitakami-karin.dts"
/ {
model = "Sony Xperia Z4 Tablet (Wi-Fi)";
compatible = "sony,karin_windy", "qcom,apq8094";
/*
* This model uses the APQ variant of MSM8994 (APQ8094).
* The v1/v2/v2.1 story (from kitakami.dtsi) also applies here.
*/
qcom,msm-id = <253 0x20000>, <253 0x20001>;
};
/delete-node/ &pm8994_l1;
/delete-node/ &pm8994_l19;

291
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts Normal file
View file

@ -0,0 +1,291 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Alcatel OneTouch Idol 3 (4.7)";
compatible = "alcatel,idol347", "qcom,msm8916";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_default>;
label = "GPIO Buttons";
volume-up {
label = "Volume Up";
gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
};
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&msmgpio 69 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
};
&blsp1_uart2 {
status = "okay";
};
&blsp_i2c5 {
status = "okay";
magnetometer@c {
compatible = "asahi-kasei,ak09911";
reg = <0x0c>;
vdd-supply = <&pm8916_l17>;
vid-supply = <&pm8916_l6>;
reset-gpios = <&msmgpio 8 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&mag_reset_default>;
mount-matrix = "0", "1", "0",
"-1", "0", "0",
"0", "0", "1";
};
accelerometer@f {
compatible = "kionix,kxtj21009";
reg = <0x0f>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
interrupt-parent = <&msmgpio>;
interrupts = <31 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&accel_int_default>;
mount-matrix = "-1", "0", "0",
"0", "1", "0",
"0", "0", "-1";
};
proximity@48 {
compatible = "sensortek,stk3310";
reg = <0x48>;
interrupt-parent = <&msmgpio>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&proximity_int_default>;
};
gyroscope@68 {
compatible = "bosch,bmg160";
reg = <0x68>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
interrupt-parent = <&msmgpio>;
interrupts = <97 IRQ_TYPE_EDGE_RISING>,
<98 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&gyro_int_default>;
};
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
};
&pm8916_vib {
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
};
&sdhc_2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>;
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
};
&usb_hs_phy {
extcon = <&usb_id>;
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;
vdd_l7-supply = <&pm8916_s4>;
s3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
};
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2100000>;
};
l1 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
l4 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l8 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2900000>;
};
l9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l10 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2800000>;
};
l11 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
l18 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
};
&msmgpio {
accel_int_default: accel-int-default {
pins = "gpio31";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_keys_default: gpio-keys-default {
pins = "gpio107";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
gyro_int_default: gyro-int-default {
pins = "gpio97", "gpio98";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
mag_reset_default: mag-reset-default {
pins = "gpio8";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
proximity_int_default: proximity-int-default {
pins = "gpio12";
function = "gpio";
drive-strength = <6>;
bias-pull-up;
};
usb_id_default: usb-id-default {
pins = "gpio69";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};

195
arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts Normal file
View file

@ -0,0 +1,195 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Asus Zenfone 2 Laser";
compatible = "asus,z00l", "qcom,msm8916";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_default>;
label = "GPIO Buttons";
volume-up {
label = "Volume Up";
gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <15>;
};
volume-down {
label = "Volume Down";
gpios = <&msmgpio 117 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <15>;
};
};
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&msmgpio 110 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
};
&blsp1_uart2 {
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
};
&usb_hs_phy {
extcon = <&usb_id>;
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;
vdd_l7-supply = <&pm8916_s4>;
s3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
};
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2100000>;
};
l1 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
l4 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l8 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2900000>;
};
l9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l10 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2800000>;
};
l11 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
l18 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
};
&msmgpio {
gpio_keys_default: gpio-keys-default {
pins = "gpio107", "gpio117";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
usb_id_default: usb-id-default {
pins = "gpio110";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};

267
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts Normal file
View file

@ -0,0 +1,267 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "BQ Aquaris X5 (Longcheer L8910)";
compatible = "longcheer,l8910", "qcom,msm8916";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_default>;
label = "GPIO Buttons";
volume-up {
label = "Volume Up";
gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
gpios = <&msmgpio 17 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_WHITE>;
default-state = "off";
function = LED_FUNCTION_KBD_BACKLIGHT;
pinctrl-names = "default";
pinctrl-0 = <&button_backlight_default>;
};
};
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
};
&blsp_i2c3 {
status = "okay";
magnetometer@d {
compatible = "asahi-kasei,ak09911";
reg = <0x0d>;
vdd-supply = <&pm8916_l17>;
vid-supply = <&pm8916_l6>;
reset-gpios = <&msmgpio 111 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&mag_reset_default>;
};
imu@68 {
compatible = "bosch,bmi160";
reg = <0x68>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l6>;
mount-matrix = "0", "1", "0",
"-1", "0", "0",
"0", "0", "1";
};
};
&blsp1_uart2 {
status = "okay";
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
};
&pm8916_vib {
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
};
&sdhc_2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>;
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
};
&usb_hs_phy {
extcon = <&usb_id>;
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;
vdd_l7-supply = <&pm8916_s4>;
s3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
};
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2100000>;
};
l1 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
l4 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l8 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2900000>;
};
l9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l10 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2800000>;
};
l11 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
l18 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
};
&msmgpio {
button_backlight_default: button-backlight-default {
pins = "gpio17";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
gpio_keys_default: gpio-keys-default {
pins = "gpio107";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
mag_reset_default: mag-reset-default {
pins = "gpio111";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
usb_id_default: usb-id-default {
pins = "gpio110";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};

16
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
View file

@ -220,6 +220,22 @@ i2c2_sleep: i2c2-sleep {
bias-disable;
};
i2c3_default: i2c3-default {
pins = "gpio10", "gpio11";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
i2c3_sleep: i2c3-sleep {
pins = "gpio10", "gpio11";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
i2c4_default: i2c4-default {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";

10
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
View file

@ -106,6 +106,9 @@ accelerometer: accelerometer@10 {
interrupt-parent = <&msmgpio>;
interrupts = <115 IRQ_TYPE_EDGE_RISING>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l5>;
pinctrl-names = "default";
pinctrl-0 = <&accel_int_default>;
};
@ -113,6 +116,9 @@ accelerometer: accelerometer@10 {
magnetometer@12 {
compatible = "bosch,bmc150_magn";
reg = <0x12>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l5>;
};
};
@ -126,6 +132,10 @@ &dsi0 {
pinctrl-1 = <&mdss_sleep>;
};
&mdss {
status = "okay";
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;

2
arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
View file

@ -38,7 +38,7 @@ touchscreen@48 {
&pronto {
iris {
compatible = "qcom,wcn3680";
compatible = "qcom,wcn3660b";
};
};

20
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file

@ -56,7 +56,7 @@ tz@86500000 {
no-map;
};
reserved@8668000 {
reserved@86680000 {
reg = <0x0 0x86680000 0x0 0x80000>;
no-map;
};
@ -69,7 +69,7 @@ rmtfs@86700000 {
qcom,client-id = <1>;
};
rfsa@867e00000 {
rfsa@867e0000 {
reg = <0x0 0x867e0000 0x0 0x20000>;
no-map;
};
@ -913,6 +913,7 @@ tcsr: syscon@1937000 {
};
mdss: mdss@1a00000 {
status = "disabled";
compatible = "qcom,mdss";
reg = <0x01a00000 0x1000>,
<0x01ac8000 0x3000>;
@ -1528,6 +1529,21 @@ blsp_spi2: spi@78b6000 {
status = "disabled";
};
blsp_i2c3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x500>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c3_default>;
pinctrl-1 = <&i2c3_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_spi3: spi@78b7000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b7000 0x500>;

41
arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
View file

@ -6,6 +6,8 @@
/dts-v1/;
#include "msm8992.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
/ {
model = "LG Nexus 5X";
@ -44,7 +46,7 @@ &blsp1_uart2 {
};
&rpm_requests {
pm8994-regulators {
pm8994_regulators: pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
vdd_l1-supply = <&pm8994_s1>;
@ -53,15 +55,17 @@ pm8994-regulators {
vdd_l4_27_31-supply = <&pm8994_s3>;
vdd_l5_7-supply = <&pm8994_s3>;
vdd_l6_12_32-supply = <&pm8994_s5>;
vdd_l8_16_30-supply = <&vreg_vph_pwr>;
vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
vdd_l8_16_30-supply = <&vph_pwr>;
vdd_l9_10_18_22-supply = <&vph_pwr>;
vdd_l13_19_23_24-supply = <&vph_pwr>;
vdd_l14_15-supply = <&pm8994_s5>;
vdd_l17_29-supply = <&vreg_vph_pwr>;
vdd_l20_21-supply = <&vreg_vph_pwr>;
vdd_l17_29-supply = <&vph_pwr>;
vdd_l20_21-supply = <&vph_pwr>;
vdd_l25-supply = <&pm8994_s5>;
vdd_lvs1_2 = <&pm8994_s4>;
/* S1, S2, S6 and S12 are managed by RPMPD */
pm8994_s1: s1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
@ -93,6 +97,8 @@ pm8994_s7: s7 {
regulator-max-microvolt = <1000000>;
};
/* S8, S9, S10 and S11 - SPMI-managed VDD_APC */
pm8994_l1: l1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
@ -113,18 +119,14 @@ pm8994_l4: l4 {
regulator-max-microvolt = <1225000>;
};
pm8994_l5: l5 {
/* TODO */
};
/* L5 is inaccessible from RPM */
pm8994_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_l7: l7 {
/* TODO */
};
/* L7 is inaccessible from RPM */
pm8994_l8: l8 {
regulator-min-microvolt = <1800000>;
@ -266,9 +268,22 @@ pm8994_l32: l32 {
*/
};
};
pmi8994_regulators: pmi8994-regulators {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_bst_byp-supply = <&vph_pwr>;
pmi8994_s1: s1 {};
/* S2 & S3 - VDD_GFX */
pmi8994_bby: boost-bypass {};
};
};
&sdhc_1 {
&sdhc1 {
status = "okay";
mmc-hs400-1_8v;

15
arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dts Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
* Copyright (c) 2020, Gustave Monce <gustave.monce@outlook.com>
*/
/dts-v1/;
#include "msm8992.dtsi"
#include "msm8994-msft-lumia-octagon.dtsi"
/ {
model = "Microsoft Lumia 950";
compatible = "microsoft,talkman", "qcom,msm8992";
};

67
arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts
View file

@ -1,67 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
/dts-v1/;
#include "msm8992.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
/ {
model = "Microsoft Lumia 950";
compatible = "microsoft,talkman", "qcom,msm8992";
/* Most Lumia 950 users use GRUB to load their kernels,
* hence there is no need for msm-id and friends.
*/
/* This enables graphical output via bootloader-enabled display.
* acpi=no is required due to WP platforms having ACPI support, but
* only for Windows-based OSes.
*/
chosen {
bootargs = "earlycon=efifb console=efifb acpi=no";
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
};
&blsp_i2c1 {
status = "okay";
rmi4-i2c-dev@4b {
compatible = "syna,rmi4-i2c";
reg = <0x4b>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&tlmm>;
interrupts = <77 IRQ_TYPE_EDGE_FALLING>;
rmi4-f01@1 {
reg = <0x01>;
syna,nosleep-mode = <1>;
};
rmi4-f12@12 {
reg = <0x12>;
syna,sensor-type = <1>;
syna,clip-x-low = <0>;
syna,clip-x-high = <1440>;
syna,clip-y-low = <0>;
syna,clip-y-high = <2560>;
};
};
};
&sdhc_1 {
status = "okay";
mmc-hs200-1_8v;
};

122
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
View file

@ -70,21 +70,6 @@ ramoops@dfc00000 {
pmsg-size = <0x20000>;
};
continuous_splash: framebuffer@3401000{
reg = <0x0 0x3401000 0x0 0x2200000>;
no-map;
};
dfps_data_mem: dfps_data_mem@3400000 {
reg = <0x0 0x3400000 0x0 0x1000>;
no-map;
};
peripheral_region: peripheral_region@7400000 {
reg = <0x0 0x7400000 0x0 0x1c00000>;
no-map;
};
modem_region: modem_region@9000000 {
reg = <0x0 0x9000000 0x0 0x5a00000>;
no-map;
@ -97,43 +82,49 @@ tzapp: modem_region@ea00000 {
};
};
&blsp_i2c2 {
&blsp1_i2c2 {
status = "okay";
/* Atmel or Synaptics touchscreen */
};
&blsp_i2c5 {
status = "okay";
/* Silabs si4705 FM transmitter */
};
&blsp_i2c6 {
status = "okay";
/* NCI NFC,
* TI USB320 Type-C controller,
* Pericom 30216a USB (de)mux switch
*/
};
&blsp_i2c7 {
status = "okay";
/* cm36686 proximity and ambient light sensor */
};
&blsp_i2c13 {
&blsp1_i2c5 {
status = "okay";
/* ST lsm6db0 gyro/accelerometer */
};
&blsp1_i2c6 {
status = "okay";
/*
* NXP NCI NFC,
* TI USB320 Type-C controller,
* Pericom 30216a USB (de)mux switch
*/
};
&blsp2_i2c1 {
status = "okay";
/* cm36686 proximity and ambient light sensor */
};
&blsp2_i2c5 {
status = "okay";
/* Silabs si4705 FM transmitter */
};
&blsp2_uart2 {
status = "okay";
};
&peripheral_region {
reg = <0x0 0x7400000 0x0 0x1c00000>;
no-map;
};
&rpm_requests {
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
@ -144,24 +135,16 @@ pm8994-regulators {
vdd_l4_27_31-supply = <&pm8994_s3>;
vdd_l5_7-supply = <&pm8994_s3>;
vdd_l6_12_32-supply = <&pm8994_s5>;
vdd_l8_16_30-supply = <&vreg_vph_pwr>;
vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
vdd_l8_16_30-supply = <&vph_pwr>;
vdd_l9_10_18_22-supply = <&vph_pwr>;
vdd_l13_19_23_24-supply = <&vph_pwr>;
vdd_l14_15-supply = <&pm8994_s5>;
vdd_l17_29-supply = <&vreg_vph_pwr>;
vdd_l20_21-supply = <&vreg_vph_pwr>;
vdd_l17_29-supply = <&vph_pwr>;
vdd_l20_21-supply = <&vph_pwr>;
vdd_l25-supply = <&pm8994_s5>;
vdd_lvs1_2 = <&pm8994_s4>;
pm8994_s1: s1 {
/* unused */
status = "disabled";
};
pm8994_s2: s2 {
/* unused */
status = "disabled";
};
/* S1, S2, S6 and S12 are managed by RPMPD */
pm8994_s3: s3 {
regulator-min-microvolt = <1300000>;
@ -186,6 +169,8 @@ pm8994_s7: s7 {
regulator-max-microvolt = <1000000>;
};
/* S8, S9, S10 and S11 - SPMI-managed VDD_APC */
pm8994_l1: l1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
@ -206,20 +191,14 @@ pm8994_l4: l4 {
regulator-max-microvolt = <1225000>;
};
pm8994_l5: l5 {
/* unused */
status = "disabled";
};
/* L5 is inaccessible from RPM */
pm8994_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_l7: l7 {
/* unused */
status = "disabled";
};
/* L7 is inaccessible from RPM */
pm8994_l8: l8 {
regulator-min-microvolt = <1800000>;
@ -352,10 +331,31 @@ pm8994_l32: l32 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_lvs1: lvs1 {};
pm8994_lvs2: lvs2 {};
};
pmi8994_regulators: pmi8994-regulators {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_bst_byp-supply = <&vph_pwr>;
pmi8994_s1: s1 {
regulator-min-microvolt = <1025000>;
regulator-max-microvolt = <1025000>;
};
/* S2 & S3 - VDD_GFX */
pmi8994_bby: boost-bypass {
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3600000>;
};
};
};
&sdhc_1 {
&sdhc1 {
status = "okay";
mmc-hs400-1_8v;

743
arch/arm64/boot/dts/qcom/msm8992.dtsi
View file

@ -2,738 +2,29 @@
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
#include "msm8994.dtsi"
/ {
interrupt-parent = <&intc>;
/* 8992 only features 2 A57 cores. */
/delete-node/ &CPU6;
/delete-node/ &CPU7;
/delete-node/ &cpu6_map;
/delete-node/ &cpu7_map;
#address-cells = <2>;
#size-cells = <2>;
&rpmcc {
compatible = "qcom,rpmcc-msm8992";
};
chosen { };
&tcsr_mutex {
compatible = "qcom,sfpb-mutex";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
next-level-cache = <&L2_1>;
enable-method = "psci";
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
next-level-cache = <&L2_1>;
enable-method = "psci";
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
};
};
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
firmware {
scm {
compatible = "qcom,scm-msm8994", "qcom,scm";
};
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-0.2";
method = "hvc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_region: smem@6a00000 {
reg = <0x0 0x6a00000 0x0 0x200000>;
no-map;
};
};
sfpb_mutex: hwmutex {
compatible = "qcom,sfpb-mutex";
syscon = <&sfpb_mutex_regs 0x0 0x100>;
#hwlock-cells = <1>;
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
hwlocks = <&sfpb_mutex 3>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xf9000000 0x1000>,
<0xf9002000 0x1000>;
};
apcs: mailbox@f900d000 {
compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
reg = <0xf900d000 0x2000>;
#mbox-cells = <1>;
};
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xf9020000 0x1000>;
frame@f9021000 {
frame-number = <0>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
};
usb3: usb@f92f8800 {
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
reg = <0xf92f8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo";
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
power-domains = <&gcc USB30_GDSC>;
qcom,select-utmi-as-pipe-clk;
dwc3@f9200000 {
compatible = "snps,dwc3";
reg = <0xf9200000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
maximum-speed = "high-speed";
dr_mode = "peripheral";
};
};
sdhc_1: sdhci@f9824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
&sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
&sdc1_rclk_off>;
regulator-always-on;
bus-width = <8>;
non-removable;
status = "disabled";
};
sdhc_2: sdhci@f98a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
<&gcc GCC_SDCC2_AHB_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
cd-gpios = <&tlmm 100 0>;
bus-width = <4>;
status = "disabled";
};
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
status = "disabled";
};
blsp_i2c1: i2c@f9923000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c2: i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_default>;
pinctrl-1 = <&i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
/* Somebody was very creative with their numbering scheme downstream... */
blsp_i2c13: i2c@f9927000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9927000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c13_default>;
pinctrl-1 = <&i2c13_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c6: i2c@f9928000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9928000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>;
pinctrl-1 = <&i2c6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_uart2: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart2_default>;
pinctrl-1 = <&blsp2_uart2_sleep>;
status = "disabled";
};
blsp_i2c7: i2c@f9963000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9963000 0x500>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c7_default>;
pinctrl-1 = <&i2c7_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c5: i2c@f9967000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9967000 0x500>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_default>;
pinctrl-1 = <&i2c5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
rpm_msg_ram: memory@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
spmi_bus: spmi@fc4c0000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xfc4cf000 0x1000>,
<0xfc4cb000 0x1000>,
<0xfc4ca000 0x1000>;
reg-names = "core", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
sfpb_mutex_regs: syscon@fd484000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "syscon";
reg = <0xfd484000 0x400>;
};
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 146>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
blsp1_uart2_default: blsp1-uart2-default {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
blsp1_uart2_sleep: blsp1-uart2-sleep {
function = "gpio";
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-pull-down;
};
blsp2_uart2_default: blsp2-uart2-default {
function = "blsp_uart8";
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <16>;
bias-disable;
};
blsp2_uart2_sleep: blsp2-uart2-sleep {
function = "gpio";
pins = "gpio45", "gpio46", "gpio47", "gpio48";
drive-strength = <2>;
bias-pull-down;
};
sdc1_clk_on: clk-on {
pins = "sdc1_clk";
bias-disable;
drive-strength = <6>;
};
sdc1_clk_off: clk-off {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
sdc1_cmd_on: cmd-on {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <6>;
};
sdc1_cmd_off: cmd-off {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
sdc1_data_on: data-on {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <6>;
};
sdc1_data_off: data-off {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
sdc1_rclk_on: rclk-on {
pins = "sdc1_rclk";
bias-pull-down;
};
sdc1_rclk_off: rclk-off {
pins = "sdc1_rclk";
bias-pull-down;
};
i2c1_default: i2c1-default {
function = "blsp_i2c1";
pins = "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
i2c1_sleep: i2c1-sleep {
function = "gpio";
pins = "gpio2", "gpio3";
drive-strength = <2>;
bias-disable;
};
i2c2_default: i2c2-default {
function = "blsp_i2c2";
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
i2c2_sleep: i2c2-sleep {
function = "gpio";
pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
i2c5_default: i2c5-default {
/* Don't be fooled! Nobody knows the reason why though... */
function = "blsp_i2c11";
pins = "gpio83", "gpio84";
drive-strength = <2>;
bias-disable;
};
i2c5_sleep: i2c5-sleep {
function = "gpio";
pins = "gpio83", "gpio84";
drive-strength = <2>;
bias-disable;
};
i2c6_default: i2c6-default {
function = "blsp_i2c6";
pins = "gpio28", "gpio27";
drive-strength = <2>;
bias-disable;
};
i2c6_sleep: i2c6-sleep {
function = "gpio";
pins = "gpio28", "gpio27";
drive-strength = <2>;
bias-disable;
};
i2c7_default: i2c7-default {
function = "blsp_i2c7";
pins = "gpio43", "gpio44";
drive-strength = <2>;
bias-disable;
};
i2c7_sleep: i2c7-sleep {
function = "gpio";
pins = "gpio43", "gpio44";
drive-strength = <2>;
bias-disable;
};
i2c13_default: i2c13-default {
/* Not a typo either. */
function = "blsp_i2c5";
pins = "gpio23", "gpio24";
drive-strength = <2>;
bias-disable;
};
i2c13_sleep: i2c13-sleep {
function = "gpio";
pins = "gpio23", "gpio24";
drive-strength = <2>;
bias-disable;
};
sdc2_clk_on: sdc2-clk-on {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
sdc2_clk_off: sdc2-clk-off {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
sdc2_cmd_on: sdc2-cmd-on {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
sdc2_cmd_off: sdc2-cmd-off {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
sdc2_data_on: sdc2-data-on {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sdc2_data_off: sdc2-data-off {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
};
};
smd_rpm: smd {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
qcom,local-pid = <0>;
qcom,remote-pid = <6>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8994";
qcom,smd-channels = "rpm_requests";
rpmcc: rpmcc {
compatible = "qcom,rpmcc-msm8992";
#clock-cells = <1>;
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
&timer {
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
vreg_vph_pwr: vreg-vph-pwr {
compatible = "regulator-fixed";
status = "okay";
regulator-name = "vph-pwr";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
};
&tlmm {
compatible = "qcom,msm8992-pinctrl";
};

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arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts
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@ -1,73 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
*/
/dts-v1/;
#include "msm8994.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
/ {
model = "Microsoft Lumia 950 XL";
compatible = "microsoft,cityman", "qcom,msm8994";
/*
* Most Lumia 950XL users use GRUB to load their kernels,
* hence there is no need for msm-id and friends.
*/
/*
* This enables graphical output via bootloader-enabled display.
* acpi=no is required due to WP platforms having ACPI support, but
* only for Windows-based OSes.
*/
chosen {
bootargs = "earlycon=efifb console=efifb acpi=no";
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
};
&blsp_i2c1 {
status = "okay";
rmi4-i2c-dev@4b {
compatible = "syna,rmi4-i2c";
reg = <0x4b>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&tlmm>;
interrupts = <77 IRQ_TYPE_EDGE_FALLING>;
rmi4-f01@1 {
reg = <0x01>;
syna,nosleep-mode = <1>;
};
rmi4-f12@12 {
reg = <0x12>;
syna,sensor-type = <1>;
syna,clip-x-low = <0>;
syna,clip-x-high = <1440>;
syna,clip-y-low = <0>;
syna,clip-y-high = <2660>;
};
};
};
&blsp1_uart2 {
status = "okay";
};
&blsp2_uart2 {
status = "okay";
};
&sdhc1 {
status = "okay";
};

15
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
* Copyright (c) 2020, Gustave Monce <gustave.monce@outlook.com>
*/
/dts-v1/;
#include "msm8994.dtsi"
#include "msm8994-msft-lumia-octagon.dtsi"
/ {
model = "Microsoft Lumia 950 XL";
compatible = "microsoft,cityman", "qcom,msm8994";
};

909
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Common Board Device Tree for
* Microsoft Mobile MSM8994 Octagon Platforms
*
* Copyright (c) 2020, Konrad Dybcio
* Copyright (c) 2020, Gustave Monce <gustave.monce@outlook.com>
*/
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/*
* Delete all generic (msm8994.dtsi) reserved
* memory mappings which are different in this device.
*/
/delete-node/ &adsp_mem;
/delete-node/ &audio_mem;
/delete-node/ &cont_splash_mem;
/delete-node/ &mba_mem;
/delete-node/ &mpss_mem;
/delete-node/ &peripheral_region;
/delete-node/ &rmtfs_mem;
/delete-node/ &smem_mem;
/ {
/*
* Most Lumia 950/XL users use GRUB to load their kernels,
* hence there is no need for msm-id and friends.
*/
/*
* This enables graphical output via bootloader-enabled display.
* acpi=no is required due to WP platforms having ACPI support, but
* only for Windows-based OSes.
*/
chosen {
bootargs = "earlycon=efifb console=efifb acpi=no";
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
clocks {
compatible = "simple-bus";
divclk4: divclk4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "divclk4";
pinctrl-names = "default";
pinctrl-0 = <&divclk4_pin_a>;
};
};
gpio-keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
autorepeat;
volupkey {
label = "Volume Up";
gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
debounce-interval = <15>;
};
camsnapkey {
label = "Camera Snapshot";
gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_CAMERA>;
wakeup-source;
debounce-interval = <15>;
};
camfocuskey {
label = "Camera Focus";
gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
debounce-interval = <15>;
};
};
gpio-hall-sensor {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&hall_front_default &hall_back_default>;
label = "GPIO Hall Effect Sensor";
hall-front-sensor {
label = "Hall Effect Front Sensor";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
linux,can-disable;
};
hall-back-sensor {
label = "Hall Effect Back Sensor";
gpios = <&tlmm 75 GPIO_ACTIVE_HIGH>;
linux,input-type = <EV_SW>;
linux,code = <SW_MACHINE_COVER>;
linux,can-disable;
};
};
reserved-memory {
/*
* This device being a WP platform has a very different
* memory layout than other Android based devices.
* This memory layout is directly copied from the original
* device UEFI firmware, and adapted based on observations
* using JTAG for the Qualcomm Peripheral Image regions.
*/
uefi_mem: memory@200000 {
reg = <0 0x200000 0 0x100000>;
no-map;
};
mppark_mem: memory@300000 {
reg = <0 0x300000 0 0x80000>;
no-map;
};
fbpt_mem: memory@380000 {
reg = <0 0x380000 0 0x1000>;
no-map;
};
dbg2_mem: memory@381000 {
reg = <0 0x381000 0 0x4000>;
no-map;
};
capsule_mem: memory@385000 {
reg = <0 0x385000 0 0x1000>;
no-map;
};
tpmctrl_mem: memory@386000 {
reg = <0 0x386000 0 0x3000>;
no-map;
};
uefiinfo_mem: memory@389000 {
reg = <0 0x389000 0 0x1000>;
no-map;
};
reset_mem: memory@389000 {
reg = <0 0x389000 0 0x1000>;
no-map;
};
resuncached_mem: memory@38e000 {
reg = <0 0x38e000 0 0x72000>;
no-map;
};
disp_mem: memory@400000 {
reg = <0 0x400000 0 0x800000>;
no-map;
};
uefistack_mem: memory@c00000 {
reg = <0 0xc00000 0 0x40000>;
no-map;
};
cpuvect_mem: memory@c40000 {
reg = <0 0xc40000 0 0x10000>;
no-map;
};
rescached_mem: memory@400000 {
reg = <0 0xc50000 0 0xb0000>;
no-map;
};
tzapps_mem: memory@6500000 {
reg = <0 0x6500000 0 0x500000>;
no-map;
};
smem_mem: memory@6a00000 {
reg = <0 0x6a00000 0 0x200000>;
no-map;
};
hyp_mem: memory@6c00000 {
reg = <0 0x6c00000 0 0x100000>;
no-map;
};
tz_mem: memory@6d00000 {
reg = <0 0x6d00000 0 0x160000>;
no-map;
};
rfsa_adsp_mem: memory@6e60000 {
reg = <0 0x6e60000 0 0x10000>;
no-map;
};
rfsa_mpss_mem: memory@6e70000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0x6e70000 0 0x10000>;
no-map;
qcom,client-id = <1>;
};
/*
* Value obtained from the device original ACPI DSDT table
* MPSS_EFS / SBL
*/
mba_mem: memory@6e80000 {
reg = <0 0x6e80000 0 0x180000>;
no-map;
};
/*
* Peripheral Image loader region begin!
* The region reserved for pil is 0x7000000-0xef00000
*/
mpss_mem: memory@7000000 {
reg = <0 0x7000000 0 0x5a00000>;
no-map;
};
adsp_mem: memory@ca00000 {
reg = <0 0xca00000 0 0x1800000>;
no-map;
};
venus_mem: memory@e200000 {
reg = <0 0xe200000 0 0x500000>;
no-map;
};
pil_metadata_mem: memory@e700000 {
reg = <0 0xe700000 0 0x4000>;
no-map;
};
memory@e704000 {
reg = <0 0xe704000 0 0x7fc000>;
no-map;
};
/* Peripheral Image loader region end */
cnss_mem: memory@ef00000 {
reg = <0 0xef00000 0 0x300000>;
no-map;
};
};
};
&blsp1_i2c1 {
status = "okay";
rmi4-i2c-dev@4b {
compatible = "syna,rmi4-i2c";
reg = <0x4b>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&tlmm>;
interrupts = <77 IRQ_TYPE_EDGE_FALLING>;
rmi4-f01@1 {
reg = <0x01>;
syna,nosleep-mode = <1>;
};
rmi4-f12@12 {
reg = <0x12>;
syna,sensor-type = <1>;
syna,clip-x-low = <0>;
syna,clip-x-high = <1440>;
syna,clip-y-low = <0>;
syna,clip-y-high = <2560>;
};
};
};
&blsp1_i2c2 {
status = "okay";
/*
* This device uses the Texas Instruments TAS2553, however the TAS2552 driver
* seems to work here. In the future a proper driver might need to
* be written for this device.
*/
tas2553: tas2553@40 {
compatible = "ti,tas2552";
reg = <0x40>;
vbat-supply = <&vph_pwr>;
iovdd-supply = <&vreg_s4a_1p8>;
avdd-supply = <&vreg_s4a_1p8>;
enable-gpio = <&pm8994_gpios 12 GPIO_ACTIVE_HIGH>;
};
};
&blsp1_i2c5 {
status = "okay";
ak09912: magnetometer@c {
compatible = "asahi-kasei,ak09912";
reg = <0xc>;
interrupt-parent = <&tlmm>;
interrupts = <26 IRQ_TYPE_EDGE_RISING>;
vdd-supply = <&vreg_l18a_2p85>;
vid-supply = <&vreg_lvs2a_1p8>;
};
zpa2326: barometer@5c {
compatible = "murata,zpa2326";
reg = <0x5c>;
interrupt-parent = <&tlmm>;
interrupts = <74 IRQ_TYPE_EDGE_RISING>;
vdd-supply = <&vreg_lvs2a_1p8>;
};
mpu6050: accelerometer@68 {
compatible = "invensense,mpu6500";
reg = <0x68>;
interrupt-parent = <&tlmm>;
interrupts = <64 IRQ_TYPE_EDGE_RISING>;
vdd-supply = <&vreg_lvs2a_1p8>;
vddio-supply = <&vreg_lvs2a_1p8>;
};
};
&blsp1_i2c6 {
status = "okay";
pn547: pn547@28 {
compatible = "nxp,pn544-i2c";
reg = <0x28>;
interrupt-parent = <&tlmm>;
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
enable-gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
};
};
&blsp1_uart2 {
status = "okay";
};
&blsp2_i2c1 {
status = "okay";
sideinteraction: ad7147_captouch@2c {
compatible = "ad,ad7147_captouch";
reg = <0x2c>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&grip_default>;
pinctrl-1 = <&grip_sleep>;
interrupts = <&tlmm 96 IRQ_TYPE_EDGE_FALLING>;
button_num = <8>;
touchpad_num = <0>;
wheel_num = <0>;
slider_num = <0>;
vcc-supply = <&vreg_l18a_2p85>;
};
/*
* The QPDS-T900/QPDS-T930 is a customized part built for Nokia
* by Avago. It is very similar to the Avago APDS-9930 with some
* minor differences. In the future a proper driver might need to
* be written for this device. For now this works fine.
*/
qpdst900: qpdst900@39 {
compatible = "avago,apds9930";
reg = <0x39>;
interrupt-parent = <&tlmm>;
interrupts = <40 IRQ_TYPE_EDGE_FALLING>;
};
};
&blsp2_i2c5 {
status = "okay";
fm_radio: si4705@11 {
compatible = "silabs,si470x";
reg = <0x11>;
interrupt-parent = <&tlmm>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&tlmm 93 GPIO_ACTIVE_HIGH>;
};
vreg_lpddr_1p1: fan53526a@6c {
compatible = "fcs,fan53526";
reg = <0x6c>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vph_pwr>;
fcs,suspend-voltage-selector = <1>;
regulator-always-on; /* Turning off DDR power doesn't sound good. */
};
/* ANX7816 HDMI bridge (needs MDSS HDMI) */
};
&blsp2_spi4 {
status = "okay";
/*
* This device is a Lattice UC120 USB-C PD PHY.
* It is actually a Lattice iCE40 FPGA pre-programmed by
* the device firmware with a specific bitstream
* enabling USB Type C PHY functionality.
* Communication is done via a proprietary protocol over SPI.
*
* TODO: Once a proper driver is available, replace this.
*/
uc120: ice5lp2k@0 {
compatible = "lattice,ice40-fpga-mgr";
reg = <0>;
spi-max-frequency = <5000000>;
cdone-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pmi8994_gpios 4 GPIO_ACTIVE_LOW>;
};
};
&blsp2_uart2 {
status = "okay";
qca6174_bt: bluetooth {
compatible = "qcom,qca6174-bt";
enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
clocks = <&divclk4>;
};
};
&pm8994_gpios {
bt_en_gpios: bt_en_gpios {
pinconf {
pins = "gpio19";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
power-source = <PM8994_GPIO_S4>;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
bias-pull-down;
};
};
divclk4_pin_a: divclk4 {
pinconf {
pins = "gpio18";
function = PMIC_GPIO_FUNC_FUNC2;
power-source = <PM8994_GPIO_S4>;
bias-disable;
};
};
};
&pm8994_pon {
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0 8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
linux,code = <KEY_POWER>;
};
volwnkey {
compatible = "qcom,pm8941-resin";
interrupts = <0 8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
&pmi8994_gpios {
pinctrl-0 = <&hd3ss460_pol &hd3ss460_amsel &hd3ss460_en>;
pinctrl-names = "default";
/*
* This device uses a TI HD3SS460 Type-C MUX
* As this device has no driver currently,
* the configuration for USB Face Up is set-up here.
*
* TODO: remove once a driver is available
* TODO: add VBUS GPIO 5
*/
hd3ss460_pol: pol_low {
pins = "gpio8";
drive-strength = <3>;
bias-pull-down;
};
hd3ss460_amsel: amsel_high {
pins = "gpio9";
drive-strength = <1>;
bias-pull-up;
};
hd3ss460_en: en_high {
pins = "gpio10";
drive-strength = <1>;
bias-pull-up;
};
};
&pmi8994_spmi_regulators {
vdd_gfx: s2@1700 {
reg = <0x1700 0x100>;
regulator-min-microvolt = <980000>;
regulator-max-microvolt = <980000>;
};
};
&rpm_requests {
/* These values were taken from the original firmware ACPI tables */
pm8994_regulators: pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_l1-supply = <&vreg_s1b_1p0>;
vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
vdd_l3_l11-supply = <&vreg_s3a_1p3>;
vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
vdd_l5_l7-supply = <&vreg_s5a_2p15>;
vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
vdd_l8_l16_l30-supply = <&vph_pwr>;
vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>;
vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>;
vdd_l14_l15-supply = <&vreg_s5a_2p15>;
vdd_l17_l29-supply = <&vph_pwr_bbyp>;
vdd_l20_l21-supply = <&vph_pwr_bbyp>;
vdd_l25-supply = <&vreg_s5a_2p15>;
vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
/* S1, S2, S6 and S12 are managed by RPMPD */
vreg_s3a_1p3: s3 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-allow-set-load;
regulator-system-load = <300000>;
};
vreg_s4a_1p8: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
regulator-always-on;
regulator-system-load = <325000>;
};
vreg_s5a_2p15: s5 {
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
regulator-allow-set-load;
regulator-system-load = <325000>;
};
vreg_s7a_1p0: s7 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
/*
* S8 - SPMI-managed VDD_APC0
* S9, S10 and S11 (the main one) - SPMI-managed VDD_APC1
*/
vreg_l1a_1p0: l1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l2a_1p25: l2 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-allow-set-load;
regulator-system-load = <4160>;
};
vreg_l3a_1p2: l3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <80000>;
};
vreg_l4a_1p225: l4 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
/* L5 is inaccessible from RPM */
vreg_l6a_1p8: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
regulator-system-load = <1000>;
};
/* L7 is inaccessible from RPM */
vreg_l8a_1p8: l8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l10a_1p8: l10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l11a_1p2: l11 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <35000>;
};
vreg_l12a_1p8: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <50000>;
};
vreg_l13a_2p95: l13 {
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <22000>;
};
vreg_l14a_1p8: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <52000>;
};
vreg_l15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l16a_2p7: l16 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
vreg_l17a_2p7: l17 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <300000>;
};
vreg_l18a_2p85: l18 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <600000>;
};
vreg_l19a_3p3: l19 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <500000>;
};
vreg_l20a_2p95: l20 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-set-load;
regulator-system-load = <570000>;
};
vreg_l21a_2p95: l21 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <800000>;
};
vreg_l22a_3p0: l22 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <150000>;
};
vreg_l23a_2p8: l23 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <80000>;
};
vreg_l24a_3p075: l24 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3150000>;
regulator-allow-set-load;
regulator-system-load = <5800>;
};
vreg_l25a_1p1: l25 {
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <80000>;
};
vreg_l26a_1p0: l26 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l27a_1p05: l27 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <500000>;
};
vreg_l28a_1p0: l28 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <26000>;
};
vreg_l29a_2p8: l29 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <80000>;
};
vreg_l30a_1p8: l30 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <2500>;
};
vreg_l31a_1p2: l31 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <600000>;
};
vreg_l32a_1p8: l32 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs1a_1p8: lvs1 { };
vreg_lvs2a_1p8: lvs2 { };
};
pmi8994_regulators: pmi8994-regulators {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_bst_byp-supply = <&vph_pwr>;
vreg_s1b_1p0: s1 {
regulator-min-microvolt = <1025000>;
regulator-max-microvolt = <1025000>;
};
/* S2 & S3 - VDD_GFX */
vph_pwr_bbyp: boost-bypass {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
};
&sdhc1 {
status = "okay";
/*
* This device is shipped with HS400 capabable eMMCs
* However various brands have been used in various product batches,
* including a Samsung eMMC (BGND3R) which features a quirk with HS400.
* Set the speed to HS200 as a safety measure.
*/
mmc-hs200-1_8v;
};
&sdhc2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
cd-gpios = <&pm8994_gpios 8 GPIO_ACTIVE_LOW>;
};
&tlmm {
grip_default: grip-default {
pins = "gpio39";
function = "gpio";
drive-strength = <6>;
bias-pull-down;
};
grip_sleep: grip-sleep {
pins = "gpio39";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
hall_front_default: hall-front-default {
pins = "gpio42";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
hall_back_default: hall-back-default {
pins = "gpio75";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};

26
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts Normal file
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@ -0,0 +1,26 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
/dts-v1/;
#include "msm8994-sony-xperia-kitakami.dtsi"
/ {
model = "Sony Xperia Z3+/Z4";
compatible = "sony,ivy-row", "qcom,msm8994";
};
&pm8994_l3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
&pm8994_l17 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
/delete-node/ &pm8994_l19;
/delete-node/ &pm8994_l32;

45
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts Normal file
View file

@ -0,0 +1,45 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
/dts-v1/;
#include "msm8994-sony-xperia-kitakami.dtsi"
/ {
model = "Sony Xperia Z4 Tablet (LTE)";
compatible = "sony,karin-row", "qcom,msm8994";
};
&blsp2_i2c5 {
/*
* TI LP8557 backlight driver @ 2c
* AD AD7146 touch controller @ 2f
* sii8620 HDMI/MHL bridge @ 72 (kitakami-common)
*/
};
&pm8994_l3 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
&pm8994_l17 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
&pm8994_l22 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
};
&pm8994_l25 {
regulator-min-microvolt = <1037500>;
regulator-max-microvolt = <1037500>;
};
/delete-node/ &pm8994_l32;
/* Z4 tablets use a different touchscreen. */
/delete-node/ &touchscreen;

18
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts Normal file
View file

@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
/dts-v1/;
#include "msm8994-sony-xperia-kitakami.dtsi"
/ {
model = "Sony Xperia Z5 Premium";
compatible = "sony,satsuki-row", "qcom,msm8994";
};
&pm8994_l14 {
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1850000>;
};

4
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
/dts-v1/;
@ -11,3 +11,5 @@ / {
model = "Sony Xperia Z5";
compatible = "sony,sumire-row", "qcom,msm8994";
};
/delete-node/ &pm8994_l19;

20
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts Normal file
View file

@ -0,0 +1,20 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
/dts-v1/;
#include "msm8994-sony-xperia-kitakami.dtsi"
/ {
model = "Sony Xperia Z5 Compact";
compatible = "sony,suzuran-row", "qcom,msm8994";
};
&pm8994_l14 {
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
};
/delete-node/ &pm8994_l19;

457
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Konrad Dybcio
* Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
#include "msm8994.dtsi"
@ -11,8 +11,17 @@
/ {
/* required for bootloader to select correct board */
qcom,msm-id = <0xcf 0x20001>;
/*
* We support MSM8994 v2 (0x20000) and v2.1 (0x20001).
* The V1 chip (0x0 and 0x10000) is significantly different
* and requires driver-side changes (including CPR, be warned!!).
* Besides that, it's very rare.
*/
qcom,msm-id = <207 0x20000>, <207 0x20001>;
/* We only use pm8994+pmi8994. */
qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>;
/* This property is shared across all kitakami devices. */
qcom,board-id = <8 0>;
/* Kitakami firmware doesn't support PSCI */
@ -63,53 +72,29 @@ button@3 {
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* This is for getting crash logs using Android downstream kernels */
ramoops@1fe00000 {
compatible = "ramoops";
reg = <0x0 0x1fe00000 0x0 0x200000>;
reg = <0 0x1fe00000 0 0x200000>;
console-size = <0x100000>;
record-size = <0x10000>;
ftrace-size = <0x10000>;
pmsg-size = <0x80000>;
};
continuous_splash: framebuffer@3401000{
reg = <0x0 0x3401000 0x0 0x2200000>;
no-map;
};
dfps_data_mem: dfps_data_mem@3400000 {
reg = <0x0 0x3400000 0x0 0x1000>;
no-map;
};
peripheral_region: peripheral_region@7400000 {
reg = <0x0 0x7400000 0x0 0x1c00000>;
no-map;
};
modem_region: modem_region@9000000 {
reg = <0x0 0x9000000 0x0 0x5a00000>;
no-map;
};
tzapp: modem_region@ea00000 {
reg = <0x0 0xea00000 0x0 0x1900000>;
no-map;
};
fb_region: fb_region@40000000 {
reg = <0x00 0x40000000 0x00 0x1000000>;
reg = <0 0x40000000 0 0x1000000>;
no-map;
};
tzapp: memory@c7800000 {
reg = <0 0xc7800000 0 0x1900000>;
no-map;
};
};
};
&blsp_spi0 {
&blsp1_spi1 {
status = "okay";
/* FPC fingerprint reader */
@ -117,94 +102,330 @@ &blsp_spi0 {
/* I2C1 is disabled on this board */
&blsp_i2c2 {
&blsp1_i2c2 {
status = "okay";
clock-frequency = <355000>;
/* NXP NFC */
/* NXP PN547 NFC */
};
&blsp_i2c4 {
&blsp1_i2c4 {
status = "okay";
clock-frequency = <355000>;
/* Empty but active */
};
&blsp_i2c5 {
&blsp1_i2c6 {
status = "okay";
clock-frequency = <355000>;
/* SMB1357 charger and sii8620 HDMI/MHL bridge */
};
touchscreen: rmi4-i2c-dev@2c {
compatible = "syna,rmi4-i2c";
reg = <0x2c>;
#address-cells = <1>;
#size-cells = <0>;
&blsp_i2c6 {
status = "okay";
interrupt-parent = <&tlmm>;
interrupts = <42 IRQ_TYPE_EDGE_FALLING>;
/* Synaptics touchscreen */
pinctrl-names = "default";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
vdd-supply = <&pm8994_l22>;
vio-supply = <&pm8994_s4>;
syna,reset-delay-ms = <220>;
syna,startup-delay-ms = <220>;
rmi4-f01@1 {
reg = <0x01>;
syna,nosleep-mode = <1>;
};
rmi4-f11@11 {
reg = <0x11>;
syna,sensor-type = <1>;
};
};
};
&blsp1_uart2 {
status = "okay";
};
&blsp2_i2c5 {
status = "okay";
clock-frequency = <355000>;
/* sii8620 HDMI/MHL bridge */
};
&blsp2_uart2 {
status = "okay";
};
/*
* Kitakami bootloader only turns cont_splash on when it detects
* specific downstream MDSS/backlight nodes in the active DTB.
* One way to use that framebuffer is to load a secondary instance of
* LK with the downstream DTB appended and then, only from there, load
* mainline Linux.
*/
&cont_splash_mem {
reg = <0 0x3401000 0 0x2200000>;
};
&pmi8994_spmi_regulators {
/*
* Yeah, this one *is* managed by RPMPD, but also needs
* to be hacked up as a-o due to the GPU device only accepting a single
* power domain.. which still isn't enough and forces us to bind
* OXILI_CX and OXILI_GX together!
*/
vdd_gfx: s2@1700 {
reg = <0x1700 0x100>;
regulator-name = "VDD_GFX";
regulator-min-microvolt = <980000>;
regulator-max-microvolt = <980000>;
/* hack until we rig up the gpu consumer */
regulator-always-on;
};
};
&rpm_requests {
pm8994_regulators: pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
vdd_l1-supply = <&pm8994_s1>;
vdd_l2_26_28-supply = <&pm8994_s3>;
vdd_l3_11-supply = <&pm8994_s3>;
vdd_l4_27_31-supply = <&pm8994_s3>;
vdd_l5_7-supply = <&pm8994_s3>;
vdd_l6_12_32-supply = <&pm8994_s5>;
vdd_l8_16_30-supply = <&vreg_vph_pwr>;
vdd_l9_10_18_22-supply = <&vreg_vph_pwr>;
vdd_l13_19_23_24-supply = <&vreg_vph_pwr>;
vdd_l14_15-supply = <&pm8994_s5>;
vdd_l17_29-supply = <&vreg_vph_pwr>;
vdd_l20_21-supply = <&vreg_vph_pwr>;
vdd_l25-supply = <&pm8994_s5>;
vdd_lvs1_2 = <&pm8994_s4>;
pm8994_s1: s1 {};
pm8994_s2: s2 {};
pm8994_s3: s3 {};
pm8994_s4: s4 {};
pm8994_s5: s5 {};
pm8994_s6: s6 {};
pm8994_s7: s7 {};
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_l1-supply = <&pmi8994_s1>;
vdd_l2_l26_l28-supply = <&pm8994_s3>;
vdd_l3_l11-supply = <&pm8994_s3>;
vdd_l4_l27_l31-supply = <&pm8994_s3>;
vdd_l5_l7-supply = <&pm8994_s5>;
vdd_l6_l12_l32-supply = <&pm8994_s5>;
vdd_l8_l16_l30-supply = <&vph_pwr>;
vdd_l9_l10_l18_l22-supply = <&pmi8994_bby>;
vdd_l13_l19_l23_l24-supply = <&pmi8994_bby>;
vdd_l14_l15-supply = <&pm8994_s5>;
vdd_l17_l29-supply = <&pmi8994_bby>;
vdd_l20_l21-supply = <&pmi8994_bby>;
vdd_l25-supply = <&pm8994_s3>;
vdd_lvs1_lvs2-supply = <&pm8994_s4>;
pm8994_l1: l1 {};
pm8994_l2: l2 {};
pm8994_l3: l3 {};
pm8994_l4: l4 {};
pm8994_l6: l6 {};
pm8994_l8: l8 {};
pm8994_l9: l9 {};
pm8994_l10: l10 {};
pm8994_l11: l11 {};
pm8994_l12: l12 {};
pm8994_l13: l13 {};
pm8994_l14: l14 {};
pm8994_l15: l15 {};
pm8994_l16: l16 {};
pm8994_l17: l17 {};
pm8994_l18: l18 {};
pm8994_l19: l19 {};
pm8994_l20: l20 {};
pm8994_l21: l21 {};
pm8994_l22: l22 {};
pm8994_l23: l23 {};
pm8994_l24: l24 {};
pm8994_l25: l25 {};
pm8994_l26: l26 {};
pm8994_l27: l27 {};
pm8994_l28: l28 {};
pm8994_l29: l29 {};
pm8994_l30: l30 {};
pm8994_l31: l31 {};
pm8994_l32: l32 {};
/* S1, S2, S6 and S12 are managed by RPMPD */
pm8994_s3: s3 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
pm8994_s4: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
regulator-always-on;
regulator-system-load = <325000>;
};
pm8994_s5: s5 {
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
};
pm8994_s7: s7 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
/*
* S8 - SPMI-managed VDD_APC0
* S9, S10 and S11 (the main one) - SPMI-managed VDD_APC1
*/
pm8994_l1: l1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
pm8994_l2: l2 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
};
pm8994_l3: l3 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
pm8994_l4: l4 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
/* L5 is inaccessible from RPM */
pm8994_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
/* L7 is inaccessible from RPM */
pm8994_l8: l8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_l9: l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_l10: l10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_l11: l11 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8994_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
};
pm8994_l13: l13 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8994_l14: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
};
pm8994_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_l16: l16 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
pm8994_l17: l17 {
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
};
pm8994_l18: l18 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
pm8994_l19: l19 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
pm8994_l20: l20 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-set-load;
regulator-system-load = <570000>;
};
pm8994_l21: l21 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <800000>;
};
pm8994_l22: l22 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
pm8994_l23: l23 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
pm8994_l24: l24 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3150000>;
};
pm8994_l25: l25 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
pm8994_l26: l26 {
regulator-min-microvolt = <987500>;
regulator-max-microvolt = <987500>;
};
pm8994_l27: l27 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
pm8994_l28: l28 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
};
pm8994_l29: l29 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
pm8994_l30: l30 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_l31: l31 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
};
pm8994_l32: l32 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8994_lvs1: lvs1 {};
pm8994_lvs2: lvs2 {};
@ -213,22 +434,34 @@ pm8994_regulators: pm8994-regulators {
pmi8994_regulators: pmi8994-regulators {
compatible = "qcom,rpm-pmi8994-regulators";
pmi8994_s1: s1 {};
pmi8994_s2: s2 {};
pmi8994_s3: s3 {};
pmi8994_bby: boost-bypass {};
vdd_s1-supply = <&vph_pwr>;
vdd_bst_byp-supply = <&vph_pwr>;
pmi8994_s1: s1 {
regulator-min-microvolt = <1025000>;
regulator-max-microvolt = <1025000>;
};
/* S2 & S3 - VDD_GFX */
pmi8994_bby: boost-bypass {
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3600000>;
};
};
};
&sdhc1 {
/* There is an issue with the eMMC causing permanent
/*
* There is an issue with the eMMC causing permanent
* damage to the card if a quirk isn't addressed.
* Until it's fixed, disable the MMC so as not to brick
* devices.
*/
status = "disabled";
/* Downstream pushes 2.95V to the sdhci device,
/*
* Downstream pushes 2.95V to the sdhci device,
* but upstream driver REALLY wants to make vmmc 1.8v
* cause of the hs400-1_8v mode. MMC works fine without
* that regulator, so let's not use it for now.
@ -238,3 +471,27 @@ &sdhc1 {
* vqmmc-supply = <&pm8994_s4>;
*/
};
&sdhc2 {
status = "okay";
cd-gpios = <&tlmm 100 0>;
vmmc-supply = <&pm8994_l21>;
vqmmc-supply = <&pm8994_l13>;
};
&tlmm {
ts_int_active: ts-int-active {
pins = "gpio42";
drive-strength = <2>;
bias-disable;
input-enable;
};
ts_reset_active: ts-reset-active {
pins = "gpio109";
drive-strength = <2>;
bias-disable;
output-low;
};
};

331
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file

@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
#include <dt-bindings/power/qcom-rpmpd.h>
/ {
interrupt-parent = <&intc>;
@ -131,11 +132,11 @@ core1 {
cpu = <&CPU5>;
};
core2 {
cpu6_map: core2 {
cpu = <&CPU6>;
};
core3 {
cpu7_map: core3 {
cpu = <&CPU7>;
};
};
@ -154,6 +155,12 @@ memory {
reg = <0 0 0 0>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x80>;
#hwlock-cells = <1>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
@ -169,8 +176,51 @@ reserved-memory {
#size-cells = <2>;
ranges;
dfps_data_mem: dfps_data_mem@3400000 {
reg = <0 0x03400000 0 0x1000>;
no-map;
};
cont_splash_mem: memory@3800000 {
reg = <0 0x03800000 0 0x2400000>;
no-map;
};
smem_mem: smem_region@6a00000 {
reg = <0x0 0x6a00000 0x0 0x200000>;
reg = <0 0x06a00000 0 0x200000>;
no-map;
};
mpss_mem: memory@7000000 {
reg = <0 0x07000000 0 0x5a00000>;
no-map;
};
peripheral_region: memory@ca00000 {
reg = <0 0x0ca00000 0 0x1f00000>;
no-map;
};
rmtfs_mem: memory@c6400000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0xc6400000 0 0x180000>;
no-map;
qcom,client-id = <1>;
};
mba_mem: memory@c6700000 {
reg = <0 0xc6700000 0 0x100000>;
no-map;
};
audio_mem: memory@c7000000 {
reg = <0 0xc7000000 0 0x800000>;
no-map;
};
adsp_mem: memory@c9400000 {
reg = <0 0xc9400000 0 0x3f00000>;
no-map;
};
};
@ -192,6 +242,35 @@ rpmcc: rpmcc {
compatible = "qcom,rpmcc-msm8994";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8994-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <1>;
};
rpmpd_opp_svs_krait: opp2 {
opp-level = <2>;
};
rpmpd_opp_svs_soc: opp3 {
opp-level = <3>;
};
rpmpd_opp_nom: opp4 {
opp-level = <4>;
};
rpmpd_opp_turbo: opp5 {
opp-level = <5>;
};
rpmpd_opp_super_turbo: opp6 {
opp-level = <6>;
};
};
};
};
};
};
@ -203,6 +282,55 @@ smem {
hwlocks = <&tcsr_mutex 3>;
};
smp2p-lpass {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc {
#address-cells = <1>;
@ -385,7 +513,7 @@ blsp1_uart2: serial@f991e000 {
status = "disabled";
};
blsp_i2c1: i2c@f9923000 {
blsp1_i2c1: i2c@f9923000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@ -393,6 +521,8 @@ blsp_i2c1: i2c@f9923000 {
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
@ -401,7 +531,7 @@ blsp_i2c1: i2c@f9923000 {
status = "disabled";
};
blsp_spi0: spi@f9923000 {
blsp1_spi1: spi@f9923000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@ -412,21 +542,21 @@ blsp_spi0: spi@f9923000 {
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_spi0_default>;
pinctrl-1 = <&blsp1_spi0_sleep>;
pinctrl-0 = <&blsp1_spi1_default>;
pinctrl-1 = <&blsp1_spi1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp_i2c2: i2c@f9924000 {
blsp1_i2c2: i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <355000>;
clock-frequency = <400000>;
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
@ -439,14 +569,16 @@ blsp_i2c2: i2c@f9924000 {
/* I2C3 doesn't exist */
blsp_i2c4: i2c@f9926000 {
blsp1_i2c4: i2c@f9926000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9926000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <355000>;
clock-frequency = <400000>;
dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_default>;
pinctrl-1 = <&i2c4_sleep>;
@ -455,6 +587,42 @@ blsp_i2c4: i2c@f9926000 {
status = "disabled";
};
blsp1_i2c5: i2c@f9927000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9927000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_default>;
pinctrl-1 = <&i2c5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c6: i2c@f9928000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9928000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>;
pinctrl-1 = <&i2c6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_dma: dma-controller@f9944000 {
compatible = "qcom,bam-v1.7.0";
reg = <0xf9944000 0x19000>;
@ -468,32 +636,10 @@ blsp2_dma: dma-controller@f9944000 {
qcom,num-ees = <4>;
};
/* According to downstream kernels, i2c6
* comes before i2c5 address-wise...
*/
blsp_i2c6: i2c@f9928000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9928000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <355000>;
dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>;
pinctrl-1 = <&i2c6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_uart2: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
@ -505,7 +651,43 @@ blsp2_uart2: serial@f995e000 {
status = "disabled";
};
blsp_i2c5: i2c@f9967000 {
blsp2_i2c1: i2c@f9963000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9963000 0x500>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c7_default>;
pinctrl-1 = <&i2c7_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_spi4: spi@f9966000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0xf9966000 0x500>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
spi-max-frequency = <19200000>;
dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_spi10_default>;
pinctrl-1 = <&blsp2_spi10_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_i2c5: i2c@f9967000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9967000 0x500>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
@ -516,8 +698,8 @@ blsp_i2c5: i2c@f9967000 {
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_default>;
pinctrl-1 = <&i2c5_sleep>;
pinctrl-0 = <&i2c11_default>;
pinctrl-1 = <&i2c11_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -588,16 +770,18 @@ blsp1_uart2_sleep: blsp1-uart2-sleep {
blsp2_uart2_default: blsp2-uart2-default {
function = "blsp_uart8";
pins = "gpio45", "gpio46";
drive-strength = <2>;
pins = "gpio45", "gpio46",
"gpio47", "gpio48";
drive-strength = <16>;
bias-disable;
};
blsp2_uart2_sleep: blsp2-uart2-sleep {
function = "gpio";
pins = "gpio45", "gpio46";
pins = "gpio45", "gpio46",
"gpio47", "gpio48";
drive-strength = <2>;
bias-pull-down;
bias-disable;
};
i2c1_default: i2c1-default {
@ -671,7 +855,56 @@ i2c6_sleep: i2c6-sleep {
bias-disable;
};
blsp1_spi0_default: blsp1-spi0-default {
i2c7_default: i2c7-default {
function = "blsp_i2c7";
pins = "gpio44", "gpio43";
drive-strength = <2>;
bias-disable;
};
i2c7_sleep: i2c7-sleep {
function = "gpio";
pins = "gpio44", "gpio43";
drive-strength = <2>;
bias-disable;
};
blsp2_spi10_default: blsp2-spi10-default {
default {
function = "blsp_spi10";
pins = "gpio53", "gpio54", "gpio55";
drive-strength = <10>;
bias-pull-down;
};
cs {
function = "gpio";
pins = "gpio55";
drive-strength = <2>;
bias-disable;
};
};
blsp2_spi10_sleep: blsp2-spi10-sleep {
pins = "gpio53", "gpio54", "gpio55";
drive-strength = <2>;
bias-disable;
};
i2c11_default: i2c11-default {
function = "blsp_i2c11";
pins = "gpio83", "gpio84";
drive-strength = <2>;
bias-disable;
};
i2c11_sleep: i2c11-sleep {
function = "gpio";
pins = "gpio83", "gpio84";
drive-strength = <2>;
bias-disable;
};
blsp1_spi1_default: blsp1-spi1-default {
default {
function = "blsp_spi1";
pins = "gpio0", "gpio1", "gpio3";
@ -686,7 +919,7 @@ cs {
};
};
blsp1_spi0_sleep: blsp1-spi0-sleep {
blsp1_spi1_sleep: blsp1-spi1-sleep {
pins = "gpio0", "gpio1", "gpio3";
drive-strength = <2>;
bias-disable;
@ -776,13 +1009,7 @@ sdc2_data_off: sdc2-data-off {
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x80>;
#hwlock-cells = <1>;
};
timer {
timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 0xff08>,
<GIC_PPI 3 0xff08>,
@ -790,9 +1017,9 @@ timer {
<GIC_PPI 1 0xff08>;
};
vreg_vph_pwr: vreg-vph-pwr {
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph-pwr";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;

4
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file

@ -750,6 +750,8 @@ pcie0: pcie@600000 {
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
device_type = "pci";
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
@ -802,6 +804,8 @@ pcie1: pcie@608000 {
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
device_type = "pci";
interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;

16
arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi
View file

@ -74,6 +74,14 @@ &CPU7 {
cpu-idle-states = <&BIG_CPU_SLEEP_1>;
};
&pcie0 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pm8005_lsid1 {
pm8005-regulators {
compatible = "qcom,pm8005-regulators";
@ -295,6 +303,14 @@ &sdhc2 {
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
};
&ufshc {
status = "okay";
};
&ufsphy {
status = "okay";
};
&usb3 {
status = "okay";
};

10
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
View file

@ -106,6 +106,14 @@ &funnel5 {
// status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pm8005_lsid1 {
pm8005-regulators {
compatible = "qcom,pm8005-regulators";
@ -345,6 +353,7 @@ &stm {
};
&ufshc {
status = "okay";
vcc-supply = <&vreg_l20a_2p95>;
vccq-supply = <&vreg_l26a_1p2>;
vccq2-supply = <&vreg_s4a_1p8>;
@ -354,6 +363,7 @@ &ufshc {
};
&ufsphy {
status = "okay";
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l2a_1p2>;
vddp-ref-clk-supply = <&vreg_l26a_1p2>;

108
arch/arm64/boot/dts/qcom/msm8998-pins.dtsi
View file

@ -1,108 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
&tlmm {
sdc2_clk_on: sdc2_clk_on {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <16>; /* 16 mA */
};
};
sdc2_clk_off: sdc2_clk_off {
config {
pins = "sdc2_clk";
bias-disable; /* NO pull */
drive-strength = <2>; /* 2 mA */
};
};
sdc2_cmd_on: sdc2_cmd_on {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <10>; /* 10 mA */
};
};
sdc2_cmd_off: sdc2_cmd_off {
config {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 mA */
};
};
sdc2_data_on: sdc2_data_on {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <10>; /* 10 mA */
};
};
sdc2_data_off: sdc2_data_off {
config {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 mA */
};
};
sdc2_cd_on: sdc2_cd_on {
mux {
pins = "gpio95";
function = "gpio";
};
config {
pins = "gpio95";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 mA */
};
};
sdc2_cd_off: sdc2_cd_off {
mux {
pins = "gpio95";
function = "gpio";
};
config {
pins = "gpio95";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 mA */
};
};
blsp1_uart3_on: blsp1_uart3_on {
tx {
pins = "gpio45";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
rx {
pins = "gpio46";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
cts {
pins = "gpio47";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
rfr {
pins = "gpio48";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
};
};

393
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file

@ -133,6 +133,7 @@ CPU0: cpu@0 {
compatible = "qcom,kryo280";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
@ -152,6 +153,7 @@ CPU1: cpu@1 {
compatible = "qcom,kryo280";
reg = <0x0 0x1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
@ -167,6 +169,7 @@ CPU2: cpu@2 {
compatible = "qcom,kryo280";
reg = <0x0 0x2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
@ -182,6 +185,7 @@ CPU3: cpu@3 {
compatible = "qcom,kryo280";
reg = <0x0 0x3>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
@ -197,6 +201,7 @@ CPU4: cpu@100 {
compatible = "qcom,kryo280";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
@ -216,6 +221,7 @@ CPU5: cpu@101 {
compatible = "qcom,kryo280";
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
@ -231,6 +237,7 @@ CPU6: cpu@102 {
compatible = "qcom,kryo280";
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
@ -246,6 +253,7 @@ CPU7: cpu@103 {
compatible = "qcom,kryo280";
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
@ -379,43 +387,43 @@ rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <16>;
opp-level = <RPM_SMD_LEVEL_RETENTION>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <32>;
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <48>;
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <64>;
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp5 {
opp-level = <128>;
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <192>;
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp7 {
opp-level = <256>;
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <320>;
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <384>;
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_turbo_plus: opp10 {
opp-level = <512>;
opp-level = <RPM_SMD_LEVEL_BINNING>;
};
};
};
@ -937,6 +945,7 @@ pcie0: pci@1c00000 {
num-lanes = <1>;
phys = <&pciephy>;
phy-names = "pciephy";
status = "disabled";
ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
<0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
@ -962,11 +971,12 @@ pcie0: pci@1c00000 {
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
};
phy@1c06000 {
pcie_phy: phy@1c06000 {
compatible = "qcom,msm8998-qmp-pcie-phy";
reg = <0x01c06000 0x18c>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
@ -999,6 +1009,7 @@ ufshc: ufshc@1da4000 {
phy-names = "ufsphy";
lanes-per-direction = <2>;
power-domains = <&gcc UFS_GDSC>;
status = "disabled";
#reset-cells = <1>;
clock-names =
@ -1038,6 +1049,7 @@ ufsphy: phy@1da7000 {
reg = <0x01da7000 0x18c>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
clock-names =
@ -1073,6 +1085,278 @@ tlmm: pinctrl@3400000 {
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
sdc2_clk_on: sdc2_clk_on {
config {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
};
sdc2_clk_off: sdc2_clk_off {
config {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
};
sdc2_cmd_on: sdc2_cmd_on {
config {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
};
sdc2_cmd_off: sdc2_cmd_off {
config {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_data_on: sdc2_data_on {
config {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
sdc2_data_off: sdc2_data_off {
config {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_cd_on: sdc2_cd_on {
mux {
pins = "gpio95";
function = "gpio";
};
config {
pins = "gpio95";
bias-pull-up;
drive-strength = <2>;
};
};
sdc2_cd_off: sdc2_cd_off {
mux {
pins = "gpio95";
function = "gpio";
};
config {
pins = "gpio95";
bias-pull-up;
drive-strength = <2>;
};
};
blsp1_uart3_on: blsp1_uart3_on {
tx {
pins = "gpio45";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
rx {
pins = "gpio46";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
cts {
pins = "gpio47";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
rfr {
pins = "gpio48";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
};
blsp1_i2c1_default: blsp1-i2c1-default {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c1_sleep: blsp1-i2c1-sleep {
pins = "gpio2", "gpio3";
function = "blsp_i2c1";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c2_default: blsp1-i2c2-default {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c2_sleep: blsp1-i2c2-sleep {
pins = "gpio32", "gpio33";
function = "blsp_i2c2";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c3_default: blsp1-i2c3-default {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c3_sleep: blsp1-i2c3-sleep {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c4_default: blsp1-i2c4-default {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c4_sleep: blsp1-i2c4-sleep {
pins = "gpio10", "gpio11";
function = "blsp_i2c4";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c5_default: blsp1-i2c5-default {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c5_sleep: blsp1-i2c5-sleep {
pins = "gpio87", "gpio88";
function = "blsp_i2c5";
drive-strength = <2>;
bias-pull-up;
};
blsp1_i2c6_default: blsp1-i2c6-default {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c6_sleep: blsp1-i2c6-sleep {
pins = "gpio43", "gpio44";
function = "blsp_i2c6";
drive-strength = <2>;
bias-pull-up;
};
/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
blsp2_i2c1_default: blsp2-i2c1-default {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c1_sleep: blsp2-i2c1-sleep {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c2_default: blsp2-i2c2-default {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c2_sleep: blsp2-i2c2-sleep {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c3_default: blsp2-i2c3-default {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c3_sleep: blsp2-i2c3-sleep {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c4_default: blsp2-i2c4-default {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c4_sleep: blsp2-i2c4-sleep {
pins = "gpio67", "gpio68";
function = "blsp_i2c10";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c5_default: blsp2-i2c5-default {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c5_sleep: blsp2-i2c5-sleep {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
bias-pull-up;
};
blsp2_i2c6_default: blsp2-i2c6-default {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c6_sleep: blsp2-i2c6-sleep {
pins = "gpio83", "gpio84";
function = "blsp_i2c12";
drive-strength = <2>;
bias-pull-up;
};
};
remoteproc_mss: remoteproc@4080000 {
@ -1789,6 +2073,11 @@ blsp1_i2c1: i2c@c175000 {
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c1_default>;
pinctrl-1 = <&blsp1_i2c1_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1804,6 +2093,11 @@ blsp1_i2c2: i2c@c176000 {
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c2_default>;
pinctrl-1 = <&blsp1_i2c2_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1819,6 +2113,11 @@ blsp1_i2c3: i2c@c177000 {
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c3_default>;
pinctrl-1 = <&blsp1_i2c3_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1834,6 +2133,11 @@ blsp1_i2c4: i2c@c178000 {
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c4_default>;
pinctrl-1 = <&blsp1_i2c4_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1849,6 +2153,11 @@ blsp1_i2c5: i2c@c179000 {
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c5_default>;
pinctrl-1 = <&blsp1_i2c5_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1864,6 +2173,11 @@ blsp1_i2c6: i2c@c17a000 {
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c6_default>;
pinctrl-1 = <&blsp1_i2c6_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1871,6 +2185,19 @@ blsp1_i2c6: i2c@c17a000 {
#size-cells = <0>;
};
blsp2_dma: dma@c184000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0c184000 0x25000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <18>;
qcom,num-ees = <4>;
};
blsp2_uart1: serial@c1b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0c1b0000 0x1000>;
@ -1881,7 +2208,7 @@ blsp2_uart1: serial@c1b0000 {
status = "disabled";
};
blsp2_i2c0: i2c@c1b5000 {
blsp2_i2c1: i2c@c1b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b5000 0x600>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
@ -1889,6 +2216,11 @@ blsp2_i2c0: i2c@c1b5000 {
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1896,7 +2228,7 @@ blsp2_i2c0: i2c@c1b5000 {
#size-cells = <0>;
};
blsp2_i2c1: i2c@c1b6000 {
blsp2_i2c2: i2c@c1b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b6000 0x600>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
@ -1904,6 +2236,11 @@ blsp2_i2c1: i2c@c1b6000 {
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c2_default>;
pinctrl-1 = <&blsp2_i2c2_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1911,7 +2248,7 @@ blsp2_i2c1: i2c@c1b6000 {
#size-cells = <0>;
};
blsp2_i2c2: i2c@c1b7000 {
blsp2_i2c3: i2c@c1b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b7000 0x600>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
@ -1919,6 +2256,11 @@ blsp2_i2c2: i2c@c1b7000 {
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c3_default>;
pinctrl-1 = <&blsp2_i2c3_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1926,7 +2268,7 @@ blsp2_i2c2: i2c@c1b7000 {
#size-cells = <0>;
};
blsp2_i2c3: i2c@c1b8000 {
blsp2_i2c4: i2c@c1b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b8000 0x600>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
@ -1934,6 +2276,11 @@ blsp2_i2c3: i2c@c1b8000 {
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c4_default>;
pinctrl-1 = <&blsp2_i2c4_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1941,7 +2288,7 @@ blsp2_i2c3: i2c@c1b8000 {
#size-cells = <0>;
};
blsp2_i2c4: i2c@c1b9000 {
blsp2_i2c5: i2c@c1b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b9000 0x600>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
@ -1949,6 +2296,11 @@ blsp2_i2c4: i2c@c1b9000 {
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c5_default>;
pinctrl-1 = <&blsp2_i2c5_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -1956,7 +2308,7 @@ blsp2_i2c4: i2c@c1b9000 {
#size-cells = <0>;
};
blsp2_i2c5: i2c@c1ba000 {
blsp2_i2c6: i2c@c1ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1ba000 0x600>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@ -1964,6 +2316,11 @@ blsp2_i2c5: i2c@c1ba000 {
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c6_default>;
pinctrl-1 = <&blsp2_i2c6_sleep>;
clock-frequency = <400000>;
status = "disabled";
@ -2110,5 +2467,3 @@ wifi: wifi@18800000 {
};
};
};
#include "msm8998-pins.dtsi"

12
arch/arm64/boot/dts/qcom/pm8150.dtsi
View file

@ -11,7 +11,7 @@
/ {
thermal-zones {
pm8150 {
pm8150-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
@ -97,6 +97,16 @@ die-temp@6 {
};
};
pm8150_adc_tm: adc-tm@3500 {
compatible = "qcom,spmi-adc-tm5";
reg = <0x3500>;
interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pm8150_rtc: rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>;

12
arch/arm64/boot/dts/qcom/pm8150b.dtsi
View file

@ -10,7 +10,7 @@
/ {
thermal-zones {
pm8150b {
pm8150b-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
@ -95,6 +95,16 @@ chg-temp@9 {
};
};
pm8150b_adc_tm: adc-tm@3500 {
compatible = "qcom,spmi-adc-tm5";
reg = <0x3500>;
interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pm8150b_gpios: gpio@c000 {
compatible = "qcom,pm8150b-gpio";
reg = <0xc000>;

12
arch/arm64/boot/dts/qcom/pm8150l.dtsi
View file

@ -10,7 +10,7 @@
/ {
thermal-zones {
pm8150l {
pm8150l-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
@ -89,6 +89,16 @@ die-temp@6 {
};
};
pm8150l_adc_tm: adc-tm@3500 {
compatible = "qcom,spmi-adc-tm5";
reg = <0x3500>;
interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pm8150l_gpios: gpio@c000 {
compatible = "qcom,pm8150l-gpio";
reg = <0xc000>;

4
arch/arm64/boot/dts/qcom/pm8994.dtsi
View file

@ -6,7 +6,7 @@
/ {
thermal-zones {
pm8994 {
pm8994-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@ -43,7 +43,7 @@ rtc@6000 {
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pon@800 {
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;

2
arch/arm64/boot/dts/qcom/pm8998.dtsi
View file

@ -9,7 +9,7 @@
/ {
thermal-zones {
pm8998 {
pm8998-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

8
arch/arm64/boot/dts/qcom/pmi8998.dtsi
View file

@ -30,11 +30,15 @@ labibb {
compatible = "qcom,pmi8998-lab-ibb";
ibb: ibb {
interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>;
interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
<0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sc-err", "ocp";
};
lab: lab {
interrupts = <0x3 0xde 0x0 IRQ_TYPE_EDGE_RISING>;
interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sc-err", "ocp";
};
};
};

2
arch/arm64/boot/dts/qcom/pms405.dtsi
View file

@ -8,7 +8,7 @@
/ {
thermal-zones {
pms405 {
pms405-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

563
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View file

@ -7,6 +7,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include "sm8250.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
@ -40,6 +42,17 @@ dc12v: dc12v-regulator {
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&lt9611_out>;
};
};
};
leds {
compatible = "gpio-leds";
@ -66,6 +79,98 @@ bt {
};
lt9611_1v2: lt9611-vdd12-regulator {
compatible = "regulator-fixed";
regulator-name = "LT9611_1V2";
vin-supply = <&vdc_3v3>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
lt9611_3v3: lt9611-3v3 {
compatible = "regulator-fixed";
regulator-name = "LT9611_3V3";
vin-supply = <&vdc_3v3>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
thermal-zones {
conn-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150b_adc_tm 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
pm8150l-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 1>;
trips {
active-config0 {
temperature = <50000>;
hysteresis = <4000>;
type = "passive";
};
};
};
skin-msm-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 0>;
trips {
active-config0 {
temperature = <50000>;
hysteresis = <4000>;
type = "passive";
};
};
};
wifi-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 1>;
trips {
active-config0 {
temperature = <52000>;
hysteresis = <4000>;
type = "passive";
};
};
};
xo-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 0>;
trips {
active-config0 {
temperature = <50000>;
hysteresis = <4000>;
type = "passive";
};
};
};
};
vbat: vbat-regulator {
compatible = "regulator-fixed";
regulator-name = "VBAT";
@ -87,7 +192,7 @@ vbat_som: vbat-som-regulator {
vdc_3v3: vdc-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "VDC_3V3";
vin-supply = <&dc12v>;
vin-supply = <&vreg_l11c_3p3>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
@ -120,6 +225,11 @@ vreg_s4a_1p8: vreg-s4a-1p8 {
};
};
&adsp {
status = "okay";
firmware-name = "qcom/sm8250/adsp.mbn";
};
&apps_rsc {
pm8009-rpmh-regulators {
compatible = "qcom,pm8009-rpmh-regulators";
@ -406,6 +516,42 @@ vreg_s8c_1p3: smps8 {
};
};
&cdsp {
status = "okay";
firmware-name = "qcom/sm8250/cdsp.mbn";
};
&dsi0 {
status = "okay";
vdda-supply = <&vreg_l9a_1p2>;
#if 0
qcom,dual-dsi-mode;
qcom,master-dsi;
#endif
ports {
port@1 {
endpoint {
remote-endpoint = <&lt9611_a>;
data-lanes = <0 1 2 3>;
};
};
};
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vreg_l5a_0p88>;
};
&gpu {
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sm8250/a650_zap.mbn";
};
};
/* LS-I2C0 */
&i2c4 {
status = "okay";
@ -413,6 +559,55 @@ &i2c4 {
&i2c5 {
status = "okay";
clock-frequency = <400000>;
lt9611_codec: hdmi-bridge@2b {
compatible = "lontium,lt9611uxc";
reg = <0x2b>;
#sound-dai-cells = <1>;
interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_HIGH>;
vdd-supply = <&lt9611_1v2>;
vcc-supply = <&lt9611_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&lt9611_irq_pin &lt9611_rst_pin>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lt9611_a: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
#if 0
port@1 {
reg = <1>;
lt9611_b: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
#endif
port@2 {
reg = <2>;
lt9611_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
/* LS-I2C1 */
@ -420,6 +615,88 @@ &i2c15 {
status = "okay";
};
&mdss {
status = "okay";
};
&mdss_mdp {
status = "okay";
};
&pm8150_adc {
xo-therm@4c {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
wifi-therm@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pm8150_adc_tm {
status = "okay";
xo-therm@0 {
reg = <0>;
io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
wifi-therm@1 {
reg = <1>;
io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
};
&pcie0_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5a_0p88>;
vdda-pll-supply = <&vreg_l9a_1p2>;
};
&pcie1 {
status = "okay";
perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
};
&pcie1_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5a_0p88>;
vdda-pll-supply = <&vreg_l9a_1p2>;
};
&pcie2 {
status = "okay";
perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
};
&pcie2_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5a_0p88>;
vdda-pll-supply = <&vreg_l9a_1p2>;
};
&pm8150_gpios {
gpio-reserved-ranges = <1 1>, <3 2>, <7 1>;
gpio-line-names =
@ -435,6 +712,25 @@ &pm8150_gpios {
"GPIO_10_P"; /* Green LED */
};
&pm8150b_adc {
conn-therm@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pm8150b_adc_tm {
status = "okay";
conn-therm@0 {
reg = <0>;
io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pm8150b_gpios {
gpio-line-names =
"NC",
@ -451,6 +747,38 @@ &pm8150b_gpios {
"NC";
};
&pm8150l_adc {
skin-msm-therm@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm8150l-therm@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pm8150l_adc_tm {
status = "okay";
skin-msm-therm@0 {
reg = <0>;
io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
pm8150l-therm@1 {
reg = <1>;
io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pm8150l_gpios {
gpio-line-names =
"NC",
@ -465,6 +793,15 @@ &pm8150l_gpios {
"PM_GPIO-B",
"NC",
"PM3003A_MODE";
lt9611_rst_pin: lt9611-rst-pin {
pins = "gpio5";
function = "normal";
output-high;
input-disable;
power-source = <0>;
};
};
&pm8150_rtc {
@ -483,6 +820,35 @@ &qupv3_id_2 {
status = "okay";
};
&q6afedai {
qi2s@16 {
reg = <16>;
qcom,sd-lines = <0 1 2 3>;
};
};
/* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */
&q6afedai {
qi2s@20 {
reg = <20>;
qcom,sd-lines = <0>;
};
};
&q6asmdai {
dai@0 {
reg = <0>;
};
dai@1 {
reg = <1>;
};
dai@2 {
reg = <2>;
};
};
&sdhc_2 {
status = "okay";
pinctrl-names = "default";
@ -491,12 +857,91 @@ &sdhc_2 {
vqmmc-supply = <&vreg_l6c_2p96>;
cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
bus-width = <4>;
/* there seem to be issues with HS400-1.8V mode, so disable it */
no-1-8-v;
no-sdio;
no-emmc;
};
&sound {
compatible = "qcom,qrb5165-rb5-sndcard";
pinctrl-0 = <&tert_mi2s_active>;
pinctrl-names = "default";
model = "Qualcomm-RB5-WSA8815-Speakers-DMIC0";
audio-routing =
"SpkrLeft IN", "WSA_SPK1 OUT",
"SpkrRight IN", "WSA_SPK2 OUT",
"VA DMIC0", "vdd-micb",
"VA DMIC1", "vdd-micb",
"MM_DL1", "MultiMedia1 Playback",
"MM_DL2", "MultiMedia2 Playback",
"MultiMedia3 Capture", "MM_UL3";
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
mm2-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
mm3-dai-link {
link-name = "MultiMedia3";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
hdmi-dai-link {
link-name = "HDMI Playback";
cpu {
sound-dai = <&q6afedai TERTIARY_MI2S_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&lt9611_codec 0>;
};
};
dma-dai-link {
link-name = "WSA Playback";
cpu {
sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>;
};
};
va-dai-link {
link-name = "VA Capture";
cpu {
sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&vamacro 0>;
};
};
};
/* CAN */
&spi0 {
status = "okay";
@ -512,6 +957,26 @@ can@0 {
};
};
&swr0 {
left_spkr: wsa8810-left{
compatible = "sdw10217211000";
reg = <0 3>;
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrLeft";
#sound-dai-cells = <0>;
};
right_spkr: wsa8810-right{
compatible = "sdw10217211000";
reg = <0 4>;
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrRight";
#sound-dai-cells = <0>;
};
};
&tlmm {
gpio-reserved-ranges = <40 4>;
gpio-line-names =
@ -696,6 +1161,87 @@ &tlmm {
"HST_WLAN_UART_TX",
"HST_WLAN_UART_RX";
lt9611_irq_pin: lt9611-irq {
pins = "gpio63";
function = "gpio";
bias-disable;
};
pcie0_default_state: pcie0-default {
clkreq {
pins = "gpio80";
function = "pci_e0";
bias-pull-up;
};
reset-n {
pins = "gpio79";
function = "gpio";
drive-strength = <2>;
output-low;
bias-pull-down;
};
wake-n {
pins = "gpio81";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie1_default_state: pcie1-default {
clkreq {
pins = "gpio83";
function = "pci_e1";
bias-pull-up;
};
reset-n {
pins = "gpio82";
function = "gpio";
drive-strength = <2>;
output-low;
bias-pull-down;
};
wake-n {
pins = "gpio84";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie2_default_state: pcie2-default {
clkreq {
pins = "gpio86";
function = "pci_e2";
bias-pull-up;
};
reset-n {
pins = "gpio85";
function = "gpio";
drive-strength = <2>;
output-low;
bias-pull-down;
};
wake-n {
pins = "gpio87";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
sdc2_default_state: sdc2-default {
clk {
pins = "sdc2_clk";
@ -706,13 +1252,13 @@ clk {
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <16>;
drive-strength = <10>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <16>;
drive-strength = <10>;
};
};
@ -792,3 +1338,10 @@ &usb_2_qmpphy {
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p92>;
};
&vamacro {
pinctrl-0 = <&dmic01_active>;
pinctrl-names = "default";
vdd-micb-supply = <&vreg_s4a_1p8>;
qcom,dmic-sample-rate = <600000>;
};

91
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View file

@ -298,40 +298,6 @@ pp1125_s1a: smps1 {
regulator-max-microvolt = <1128000>;
};
/*
* pp2040_s5a (smps5) and pp1056_s4a (smps4) are just
* inputs to other rails on AOP-managed PMICs on trogdor.
* The system is already configured to manage these rails
* automatically (enable when needed, adjust voltage for
* headroom) so we won't specify anything here.
*
* NOTE: though the rails have a voltage implied by their
* name, the automatic headroom calculation might not result
* in them being that voltage. ...and that's OK.
* Specifically the only point of these rails is to provide
* an input source for other rails and if we can satisify the
* needs of those other rails with a lower source voltage then
* we save power.
*/
pp1200_l1a: ldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
pp1000_l2a: ldo2 {
regulator-min-microvolt = <944000>;
regulator-max-microvolt = <1056000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
pp1000_l3a: ldo3 {
regulator-min-microvolt = <968000>;
regulator-max-microvolt = <1064000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_qlink_lv:
vdd_qlink_lv_ck:
vdd_qusb_hs0_core:
@ -350,24 +316,6 @@ pp900_l4a: ldo4 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
pp2700_l5a: ldo5 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
ebi0_cal:
ebi1_cal:
vddio_ck_ebi0:
vddio_ck_ebi1:
vddio_ebi0:
vddq:
pp600_l6a: ldo6 {
regulator-min-microvolt = <568000>;
regulator-max-microvolt = <648000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_cx_wlan:
pp800_l9a: ldo9 {
regulator-min-microvolt = <488000>;
@ -404,6 +352,11 @@ pp1800_l12a_r: ldo12 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/*
* On trogdor this needs to match l10a since we use it to
* give power to things like SPI flash which communicate back
* on lines powered by l10a. Thus we force to 1.8V.
*/
pp1800_l13a: ldo13 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -424,12 +377,6 @@ pp1800_l15a: ldo15 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
pp2700_l16a: ldo16 {
regulator-min-microvolt = <2496000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_3p1:
vdd_pdphy:
pp3100_l17a: ldo17 {
@ -463,8 +410,8 @@ pp1300_s8c: smps8 {
};
pp1800_l1c: ldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1616000>;
regulator-max-microvolt = <1984000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@ -491,25 +438,10 @@ pp1200_l3c: ldo3 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
ld_pp1800_esim_l4c:
vddpx_5:
pp1800_l4c: ldo4 {
regulator-min-microvolt = <1648000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_6:
pp1800_l5c: ldo5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_2:
ppvar_l6c: ldo6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3304000>;
regulator-max-microvolt = <2952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@ -936,6 +868,13 @@ wifi-firmware {
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
&dp_hot_plug_det {
pinconf {
pins = "gpio117";
bias-disable;
};
};
&qspi_cs0 {
pinconf {
pins = "gpio68";

49
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file

@ -682,6 +682,11 @@ qusb2p_hstx_trim: hstx-trim-primary@25b {
reg = <0x25b 0x1>;
bits = <1 3>;
};
gpu_speed_bin: gpu_speed_bin@1d2 {
reg = <0x1d2 0x2>;
bits = <5 8>;
};
};
sdhc_1: sdhci@7c4000 {
@ -1468,12 +1473,6 @@ pinmux {
pins = "gpio117";
function = "dp_hot";
};
pinconf {
pins = "gpio117";
bias-disable;
input-enable;
};
};
qspi_clk: qspi-clk {
@ -2060,52 +2059,69 @@ gpu: gpu@5000000 {
#cooling-cells = <2>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-825000000 {
opp-hz = /bits/ 64 <825000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <8532000>;
opp-supported-hw = <0x04>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <8532000>;
opp-supported-hw = <0x07>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <7216000>;
opp-supported-hw = <0x07>;
};
opp-565000000 {
opp-hz = /bits/ 64 <565000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <5412000>;
opp-supported-hw = <0x07>;
};
opp-430000000 {
opp-hz = /bits/ 64 <430000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <5412000>;
opp-supported-hw = <0x07>;
};
opp-355000000 {
opp-hz = /bits/ 64 <355000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <3072000>;
opp-supported-hw = <0x07>;
};
opp-267000000 {
opp-hz = /bits/ 64 <267000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <3072000>;
opp-supported-hw = <0x07>;
};
opp-180000000 {
opp-hz = /bits/ 64 <180000000>;
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
opp-peak-kBps = <1804000>;
opp-supported-hw = <0x07>;
};
};
};
@ -3355,6 +3371,7 @@ watchdog@17c10000 {
compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
timer@17c20000{
@ -3596,7 +3613,7 @@ lpass_hm: clock-controller@63000000 {
};
thermal-zones {
cpu0-thermal {
cpu0_thermal: cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -3645,7 +3662,7 @@ map1 {
};
};
cpu1-thermal {
cpu1_thermal: cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -3694,7 +3711,7 @@ map1 {
};
};
cpu2-thermal {
cpu2_thermal: cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -3743,7 +3760,7 @@ map1 {
};
};
cpu3-thermal {
cpu3_thermal: cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -3792,7 +3809,7 @@ map1 {
};
};
cpu4-thermal {
cpu4_thermal: cpu4-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -3841,7 +3858,7 @@ map1 {
};
};
cpu5-thermal {
cpu5_thermal: cpu5-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -3890,7 +3907,7 @@ map1 {
};
};
cpu6-thermal {
cpu6_thermal: cpu6-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -3931,7 +3948,7 @@ map1 {
};
};
cpu7-thermal {
cpu7_thermal: cpu7-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -3972,7 +3989,7 @@ map1 {
};
};
cpu8-thermal {
cpu8_thermal: cpu8-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
@ -4013,7 +4030,7 @@ map1 {
};
};
cpu9-thermal {
cpu9_thermal: cpu9-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;

12
arch/arm64/boot/dts/qcom/sdm630.dtsi
View file

@ -808,17 +808,19 @@ spmi_bus: spmi@800f000 {
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0c0c4000 0x1000>,
<0x0c0c5000 0x1000>;
reg-names = "hc", "cqhci";
<0x0c0c5000 0x1000>,
<0x0c0c8000 0x8000>;
reg-names = "hc", "cqhci", "ice";
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&xo_board>;
clock-names = "core", "iface", "xo";
<&gcc GCC_SDCC1_AHB_CLK>,
<&xo_board>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "core", "iface", "xo", "ice";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;

4
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View file

@ -1112,11 +1112,11 @@ camera@10 {
reg = <0x10>;
// CAM0_RST_N
reset-gpios = <&tlmm 9 0>;
reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_default>;
gpios = <&tlmm 13 0>,
<&tlmm 9 0>;
<&tlmm 9 GPIO_ACTIVE_LOW>;
clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
clock-names = "xvclk";

623
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi Normal file
View file

@ -0,0 +1,623 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SDM845 OnePlus 6(T) (enchilada / fajita) common device tree source
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sdm845.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
/delete-node/ &rmtfs_mem;
/ {
aliases {
hsuart0 = &uart6;
};
gpio-keys {
compatible = "gpio-keys";
label = "Volume keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&volume_down_gpio &volume_up_gpio>;
vol-down {
label = "Volume down";
linux,code = <KEY_VOLUMEDOWN>;
gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
};
vol-up {
label = "Volume up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
};
};
reserved-memory {
/*
* The rmtfs memory region in downstream is 'dynamically allocated'
* but given the same address every time. Hard code it as this address is
* where the modem firmware expects it to be.
*/
rmtfs_mem: memory@f5b01000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0xf5b01000 0 0x200000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
/*
* It seems like reserving the old rmtfs_mem region is also needed to prevent
* random crashes which are most likely modem related, more testing needed.
*/
removed_region: memory@88f00000 {
no-map;
reg = <0 0x88f00000 0 0x200000>;
};
ramoops: ramoops@ac300000 {
compatible = "ramoops";
reg = <0 0xac300000 0 0x400000>;
record-size = <0x40000>;
console-size = <0x40000>;
ftrace-size = <0x40000>;
pmsg-size = <0x200000>;
devinfo-size = <0x1000>;
ecc-size = <16>;
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
/*
* Apparently RPMh does not provide support for PM8998 S4 because it
* is always-on; model it as a fixed regulator.
*/
vreg_s4a_1p8: pm8998-smps4 {
compatible = "regulator-fixed";
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vph_pwr>;
};
/*
* The touchscreen regulator seems to be controlled somehow by a gpio.
* Model it as a fixed regulator and keep it on. Without schematics we
* don't know how this is actually wired up...
*/
ts_1p8_supply: ts-1p8-regulator {
compatible = "regulator-fixed";
regulator-name = "ts_1p8_supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 88 0>;
enable-active-high;
regulator-boot-on;
};
};
&adsp_pas {
status = "okay";
firmware-name = "qcom/sdm845/oneplus6/adsp.mbn";
};
&apps_rsc {
pm8998-rpmh-regulators {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-s11-supply = <&vph_pwr>;
vdd-s12-supply = <&vph_pwr>;
vdd-s13-supply = <&vph_pwr>;
vdd-l1-l27-supply = <&vreg_s7a_1p025>;
vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
vdd-l3-l11-supply = <&vreg_s7a_1p025>;
vdd-l4-l5-supply = <&vreg_s7a_1p025>;
vdd-l6-supply = <&vph_pwr>;
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
vdd-l9-supply = <&vreg_bob>;
vdd-l10-l23-l25-supply = <&vreg_bob>;
vdd-l13-l19-l21-supply = <&vreg_bob>;
vdd-l16-l28-supply = <&vreg_bob>;
vdd-l18-l22-supply = <&vreg_bob>;
vdd-l20-l24-supply = <&vreg_bob>;
vdd-l26-supply = <&vreg_s3a_1p35>;
vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
vreg_s3a_1p35: smps3 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_s5a_2p04: smps5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2040000>;
};
vreg_s7a_1p025: smps7 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1028000>;
};
vdda_mipi_dsi0_pll:
vdda_qlink_lv:
vdda_ufs1_core:
vdda_usb1_ss_core:
vreg_l1a_0p875: ldo1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2a_1p2: ldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l5a_0p8: ldo5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_1p8:
vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14a_1p88: ldo14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l17a_1p3: ldo17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l20a_2p95: ldo20 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_3p1:
vreg_l24a_3p075: ldo24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l25a_3p3: ldo25 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_mipi_dsi0_1p2:
vdda_ufs1_1p2:
vreg_l26a_1p2: ldo26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l28a_3p0: ldo28 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pmi8998-rpmh-regulators {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
vdd-bob-supply = <&vph_pwr>;
vreg_bob: bob {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3600000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
regulator-allow-bypass;
};
};
pm8005-rpmh-regulators {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vreg_s3c_0p6: smps3 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
};
};
};
&cdsp_pas {
status = "okay";
firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn";
};
&dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
#address-cells = <1>;
#size-cells = <0>;
/*
* Both devices use different panels but all other properties
* are common. Compatible line is declared in device dts.
*/
display_panel: panel@0 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
vddio-supply = <&vreg_l14a_1p88>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
};
&gpu {
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn";
};
};
&i2c12 {
status = "okay";
clock-frequency = <400000>;
synaptics-rmi4-i2c@20 {
compatible = "syna,rmi4-i2c";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&ts_default_pins>;
vdd-supply = <&vreg_l28a_3p0>;
vio-supply = <&ts_1p8_supply>;
syna,reset-delay-ms = <200>;
syna,startup-delay-ms = <200>;
rmi4-f01@1 {
reg = <0x01>;
syna,nosleep-mode = <1>;
};
rmi4_f12: rmi4-f12@12 {
reg = <0x12>;
touchscreen-x-mm = <68>;
touchscreen-y-mm = <144>;
syna,sensor-type = <1>;
syna,rezero-wait-ms = <200>;
};
};
};
&mdss {
status = "okay";
};
&mdss_mdp {
status = "okay";
};
/* Modem/wifi*/
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn";
};
&pm8998_gpio {
volume_down_gpio: pm8998_gpio5 {
pinconf {
pins = "gpio5";
function = "normal";
input-enable;
bias-pull-up;
qcom,drive-strength = <0>;
};
};
volume_up_gpio: pm8998_gpio6 {
pinconf {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
qcom,drive-strength = <0>;
};
};
};
&qupv3_id_1 {
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
&qup_i2c12_default {
mux {
pins = "gpio49", "gpio50";
function = "qup12";
drive-strength = <2>;
bias-disable;
};
};
&qup_i2c10_default {
pinconf {
pins = "gpio55", "gpio56";
drive-strength = <2>;
bias-disable;
};
};
&qup_uart9_default {
pinconf-tx {
pins = "gpio4";
drive-strength = <2>;
bias-disable;
};
pinconf-rx {
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
};
/*
* Prevent garbage data on bluetooth UART lines
*/
&qup_uart6_default {
pinmux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "qup6";
};
cts {
pins = "gpio45";
bias-pull-down;
};
rts-tx {
pins = "gpio46", "gpio47";
drive-strength = <2>;
bias-disable;
};
rx {
pins = "gpio48";
bias-pull-up;
};
};
&uart6 {
status = "okay";
bluetooth {
compatible = "qcom,wcn3990-bt";
/*
* This path is relative to the qca/
* subdir under lib/firmware.
*/
firmware-name = "oneplus6/crnv21.bin";
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
vddrf-supply = <&vreg_l17a_1p3>;
vddch0-supply = <&vreg_l25a_3p3>;
max-speed = <3200000>;
};
};
&ufs_mem_hc {
status = "okay";
reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l20a_2p95>;
vcc-max-microamp = <600000>;
};
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vdda_ufs1_core>;
vdda-pll-supply = <&vdda_ufs1_1p2>;
};
&usb_1 {
status = "okay";
/*
* disable USB3 clock requirement as the device only supports
* USB2.
*/
qcom,select-utmi-as-pipe-clk;
};
&usb_1_dwc3 {
/*
* We don't have the capability to switch modes yet.
*/
dr_mode = "peripheral";
/* fastest mode for USB 2 */
maximum-speed = "high-speed";
/* Remove USB3 phy as it's unused on this device. */
phys = <&usb_1_hsphy>;
phy-names = "usb2-phy";
};
&usb_1_hsphy {
status = "okay";
vdd-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
qcom,imp-res-offset-value = <8>;
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
tri_state_key_default: tri_state_key_default {
mux {
pins = "gpio40", "gpio42", "gpio26";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
ts_default_pins: ts-int {
mux {
pins = "gpio99", "gpio125";
function = "gpio";
drive-strength = <16>;
bias-pull-up;
};
};
panel_reset_pins: panel-reset {
mux {
pins = "gpio6", "gpio25", "gpio26";
function = "gpio";
drive-strength = <8>;
bias-disable = <0>;
};
};
panel_te_pin: panel-te {
mux {
pins = "gpio10";
function = "mdp_vsync";
drive-strength = <2>;
bias-disable;
input-enable;
};
};
panel_esd_pin: panel-esd {
mux {
pins = "gpio30";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
};

19
arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts Normal file
View file

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SDM845 OnePlus 6 (enchilada) device tree.
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include "sdm845-oneplus-common.dtsi"
/ {
model = "OnePlus 6";
compatible = "oneplus,enchilada", "qcom,sdm845";
};
&display_panel {
status = "okay";
compatible = "samsung,sofef00";
};

23
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SDM845 OnePlus 6T (fajita) device tree.
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include "sdm845-oneplus-common.dtsi"
/ {
model = "OnePlus 6T";
compatible = "oneplus,fajita", "qcom,sdm845";
};
&display_panel {
status = "okay";
compatible = "samsung,s6e3fc2x01";
};
&rmi4_f12 {
touchscreen-y-mm = <148>;
};

1
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file

@ -4573,6 +4573,7 @@ watchdog@17980000 {
compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
reg = <0 0x17980000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
apss_shared: mailbox@17990000 {

2
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View file

@ -13,7 +13,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include "sdm845.dtsi"
#include "sdm850.dtsi"
#include "pm8998.dtsi"
/ {

21
arch/arm64/boot/dts/qcom/sdm850.dtsi Normal file
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@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SDM850 SoC device tree source
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include "sdm845.dtsi"
&cpu4_opp_table {
cpu4_opp33: opp-2841600000 {
opp-hz = /bits/ 64 <2841600000>;
opp-peak-kBps = <7216000 25497600>;
};
cpu4_opp34: opp-2956800000 {
opp-hz = /bits/ 64 <2956800000>;
opp-peak-kBps = <7216000 25497600>;
turbo-mode;
};
};

158
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file

@ -47,8 +47,12 @@ CPU0: cpu@0 {
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
@ -64,8 +68,12 @@ CPU1: cpu@100 {
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
@ -79,8 +87,12 @@ CPU2: cpu@200 {
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
@ -93,8 +105,12 @@ CPU3: cpu@300 {
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <488>;
dynamic-power-coefficient = <232>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
@ -107,8 +123,12 @@ CPU4: cpu@400 {
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
@ -121,8 +141,12 @@ CPU5: cpu@500 {
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
@ -135,8 +159,12 @@ CPU6: cpu@600 {
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <369>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
@ -149,14 +177,90 @@ CPU7: cpu@700 {
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <421>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <355>;
exit-latency-us = <909>;
min-residency-us = <3934>;
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <241>;
exit-latency-us = <1461>;
min-residency-us = <4488>;
local-timer-stop;
};
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
idle-state-name = "cluster-power-collapse";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
min-residency-us = <9987>;
local-timer-stop;
};
};
};
firmware {
@ -186,6 +290,59 @@ pmu {
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD1: cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD2: cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD3: cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD4: cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD5: cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD6: cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD7: cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CLUSTER_PD: cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
};
reserved-memory {
@ -1818,6 +1975,7 @@ watchdog@17c10000 {
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
timer@17c20000 {

269
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
View file

@ -24,6 +24,106 @@ chosen {
stdout-path = "serial0:115200n8";
};
thermal-zones {
camera-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
conn-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150b_adc_tm 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw-pa1-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 2>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw-pa2-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 2>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
skin-msm-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 1>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
skin-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 1>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
xo-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150_adc_tm 0>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@ -186,6 +286,13 @@ vreg_l17a_3p0: ldo17 {
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a_0p9: ldo18 {
regulator-name = "vreg_l18a_0p9";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pm8150l-rpmh-regulators {
@ -358,6 +465,13 @@ &cdsp {
firmware-name = "qcom/sm8250/cdsp.mbn";
};
&gpu {
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sm8250/a650_zap.mbn";
};
};
&i2c1 {
status = "okay";
clock-frequency = <1000000>;
@ -378,6 +492,115 @@ &i2c15 {
/* rtc6226 @ 64 */
};
&pm8150_adc {
xo-therm@4c {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
skin-therm@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pa-therm1@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pm8150_adc_tm {
status = "okay";
xo-therm@0 {
reg = <0>;
io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
skin-therm@1 {
reg = <1>;
io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
pa-therm1@2 {
reg = <2>;
io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pm8150b_adc {
conn-therm@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pm8150b_adc_tm {
status = "okay";
conn-therm@0 {
reg = <0>;
io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pm8150l_adc_tm {
status = "okay";
camera-flash-therm@0 {
reg = <0>;
io-channels = <&pm8150l_adc ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
skin-msm-therm@1 {
reg = <1>;
io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
pa-therm2@2 {
reg = <2>;
io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&pm8150l_adc {
camera-flash-therm@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
skin-msm-therm@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pa-therm2@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pm8150_rtc {
status = "okay";
};
@ -426,3 +649,49 @@ &ufs_mem_phy {
vdda-pll-supply = <&vreg_l9a_1p2>;
vdda-pll-max-microamp = <19000>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "host";
};
&usb_1_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l5a_0p875>;
vdda18-supply = <&vreg_l12a_1p8>;
vdda33-supply = <&vreg_l2a_3p1>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p9>;
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
};
&usb_2_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l5a_0p875>;
vdda18-supply = <&vreg_l12a_1p8>;
vdda33-supply = <&vreg_l2a_3p1>;
};
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p9>;
};

940
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file

File diff suppressed because it is too large Load diff

250
arch/arm64/boot/dts/qcom/sm8350-mtp.dts Normal file
View file

@ -0,0 +1,250 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8350.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sm8350 MTP";
compatible = "qcom,sm8350-mtp", "qcom,sm8350";
aliases {
serial0 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
pm8350-rpmh-regulators {
compatible = "qcom,pm8350-rpmh-regulators";
qcom,pmic-id = "b";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-s11-supply = <&vph_pwr>;
vdd-s12-supply = <&vph_pwr>;
vdd-l1-l4-supply = <&vreg_s11b_0p95>;
vdd-l2-l7-supply = <&vreg_bob>;
vdd-l3-l5-supply = <&vreg_bob>;
vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>;
vdd-l8-supply = <&vreg_s2c_0p8>;
vreg_s10b_1p8: smps10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_s11b_0p95: smps11 {
regulator-min-microvolt = <752000>;
regulator-max-microvolt = <1000000>;
};
vreg_s12b_1p25: smps12 {
regulator-min-microvolt = <1224000>;
regulator-max-microvolt = <1360000>;
};
vreg_l1b_0p88: ldo1 {
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_3p07: ldo2 {
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b_0p9: ldo3 {
regulator-min-microvolt = <904000>;
regulator-max-microvolt = <904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5b_0p88: ldo5 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <888000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b_1p2: ldo6 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1208000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b_2p96: ldo7 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_1p2: ldo9 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pm8350c-rpmh-regulators {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l12-supply = <&vreg_s1c_1p86>;
vdd-l2-l8-supply = <&vreg_s1c_1p86>;
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
vdd-l6-l9-l11-supply = <&vreg_bob>;
vdd-l10-supply = <&vreg_s12b_1p25>;
vdd-bob-supply = <&vph_pwr>;
vreg_s1c_1p86: smps1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1952000>;
};
vreg_s2c_0p8: smps2 {
regulator-min-microvolt = <640000>;
regulator-max-microvolt = <1000000>;
};
vreg_s10c_1p05: smps10 {
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1128000>;
};
vreg_bob: bob {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
};
vreg_l1c_1p8: ldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_1p8: ldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_3p0: ldo3 {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_uim1: ldo4 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5c_uim2: ldo5 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c_1p8: ldo6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_3p0: ldo7 {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c_1p8: ldo8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c_2p96: ldo9 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_1p2: ldo10 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11c_2p96: ldo11 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12c_1p8: ldo12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c_3p0: ldo13 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&qupv3_id_1 {
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <52 8>;
};
&uart2 {
status = "okay";
};

499
arch/arm64/boot/dts/qcom/sm8350.dtsi Normal file
View file

@ -0,0 +1,499 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Linaro Limaited
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo685";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo685";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo685";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo685";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo685";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo685";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo685";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo685";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm8350", "qcom,scm";
#reset-cells = <1>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: memory@80000000 {
reg = <0x0 0x80000000 0x0 0x600000>;
no-map;
};
xbl_aop_mem: memory@80700000 {
no-map;
reg = <0x0 0x80700000 0x0 0x160000>;
};
cmd_db: memory@80860000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x80860000 0x0 0x20000>;
no-map;
};
reserved_xbl_uefi_log: memory@80880000 {
reg = <0x0 0x80880000 0x0 0x14000>;
no-map;
};
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
};
cpucp_fw_mem: memory@80b00000 {
reg = <0x0 0x80b00000 0x0 0x100000>;
no-map;
};
cdsp_secure_heap: memory@80c00000 {
reg = <0x0 0x80c00000 0x0 0x4600000>;
no-map;
};
pil_camera_mem: mmeory@85200000 {
reg = <0x0 0x85200000 0x0 0x500000>;
no-map;
};
pil_video_mem: memory@85700000 {
reg = <0x0 0x85700000 0x0 0x500000>;
no-map;
};
pil_cvp_mem: memory@85c00000 {
reg = <0x0 0x85c00000 0x0 0x500000>;
no-map;
};
pil_adsp_mem: memory@86100000 {
reg = <0x0 0x86100000 0x0 0x2100000>;
no-map;
};
pil_slpi_mem: memory@88200000 {
reg = <0x0 0x88200000 0x0 0x1500000>;
no-map;
};
pil_cdsp_mem: memory@89700000 {
reg = <0x0 0x89700000 0x0 0x1e00000>;
no-map;
};
pil_ipa_fw_mem: memory@8b500000 {
reg = <0x0 0x8b500000 0x0 0x10000>;
no-map;
};
pil_ipa_gsi_mem: memory@8b510000 {
reg = <0x0 0x8b510000 0x0 0xa000>;
no-map;
};
pil_gpu_mem: memory@8b51a000 {
reg = <0x0 0x8b51a000 0x0 0x2000>;
no-map;
};
pil_spss_mem: memory@8b600000 {
reg = <0x0 0x8b600000 0x0 0x100000>;
no-map;
};
pil_modem_mem: memory@8b800000 {
reg = <0x0 0x8b800000 0x0 0x10000000>;
no-map;
};
hyp_reserved_mem: memory@d0000000 {
reg = <0x0 0xd0000000 0x0 0x800000>;
no-map;
};
pil_trustedvm_mem: memory@d0800000 {
reg = <0x0 0xd0800000 0x0 0x76f7000>;
no-map;
};
qrtr_shbuf: memory@d7ef7000 {
reg = <0x0 0xd7ef7000 0x0 0x9000>;
no-map;
};
chan0_shbuf: memory@d7f00000 {
reg = <0x0 0xd7f00000 0x0 0x80000>;
no-map;
};
chan1_shbuf: memory@d7f80000 {
reg = <0x0 0xd7f80000 0x0 0x80000>;
no-map;
};
removed_mem: memory@d8800000 {
reg = <0x0 0xd8800000 0x0 0x6800000>;
no-map;
};
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sm8350";
reg = <0x0 0x00100000 0x0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
};
ipcc: mailbox@408000 {
compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
reg = <0 0x00408000 0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
qupv3_id_1: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc 121>,
<&gcc 122>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
uart2: serial@98c000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x0098c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc 83>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default_state>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
#hwlock-cells = <1>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
<59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
<69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
<156 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
aoss_qmp: qmp@c300000 {
compatible = "qcom,sm8350-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sm8350-tlmm";
reg = <0 0x0f100000 0 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 203>;
qup_uart3_default_state: qup-uart3-default-state {
rx {
pins = "gpio18";
function = "qup3";
};
tx {
pins = "gpio19";
function = "qup3";
};
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
timer@17c20000 {
compatible = "arm,armv7-timer-mem";
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg = <0x0 0x17c20000 0x0 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c21000 0x0 0x1000>,
<0x0 0x17c22000 0x0 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c23000 0x0 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c25000 0x0 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c27000 0x0 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c29000 0x0 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2b000 0x0 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2d000 0x0 0x1000>;
status = "disabled";
};
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x0 0x18200000 0x0 0x10000>,
<0x0 0x18210000 0x0 0x10000>,
<0x0 0x18220000 0x0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
rpmhcc: clock-controller {
compatible = "qcom,sm8350-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
};