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x86/intel_rdt: More precise L2 hit/miss measurements
Intel Goldmont processors supports non-architectural precise events that can be used to give us more insight into the success of L2 cache pseudo-locking on these platforms. Introduce a new measurement trigger that will enable two precise events, MEM_LOAD_UOPS_RETIRED.L2_HIT and MEM_LOAD_UOPS_RETIRED.L2_MISS, while accessing pseudo-locked data. A new tracepoint, pseudo_lock_l2, is created to make these results visible to the user. Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: fenghua.yu@intel.com Cc: tony.luck@intel.com Cc: vikas.shivappa@linux.intel.com Cc: gavin.hindman@intel.com Cc: jithu.joseph@intel.com Cc: dave.hansen@intel.com Cc: hpa@zytor.com Link: https://lkml.kernel.org/r/06b1456da65b543479dac8d9493e41f92f175d6c.1529706536.git.reinette.chatre@intel.com
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746e08590b
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2 changed files with 146 additions and 9 deletions
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@ -23,6 +23,7 @@
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#include <asm/cacheflush.h>
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#include <asm/intel-family.h>
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#include <asm/intel_rdt_sched.h>
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#include <asm/perf_event.h>
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#include "intel_rdt.h"
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@ -63,6 +64,9 @@ static struct class *pseudo_lock_class;
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* hardware prefetch disable bits are included here as they are documented
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* in the SDM.
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*
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* When adding a platform here also add support for its cache events to
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* measure_cycles_perf_fn()
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*
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* Return:
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* If platform is supported, the bits to disable hardware prefetchers, 0
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* if platform is not supported.
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@ -101,6 +105,16 @@ static u64 get_prefetch_disable_bits(void)
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return 0;
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}
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/*
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* Helper to write 64bit value to MSR without tracing. Used when
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* use of the cache should be restricted and use of registers used
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* for local variables avoided.
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*/
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static inline void pseudo_wrmsrl_notrace(unsigned int msr, u64 val)
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{
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__wrmsr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
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}
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/**
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* pseudo_lock_minor_get - Obtain available minor number
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* @minor: Pointer to where new minor number will be stored
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@ -834,6 +848,107 @@ static int measure_cycles_lat_fn(void *_plr)
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return 0;
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}
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static int measure_cycles_perf_fn(void *_plr)
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{
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struct pseudo_lock_region *plr = _plr;
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unsigned long long l2_hits, l2_miss;
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u64 l2_hit_bits, l2_miss_bits;
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unsigned long i;
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#ifdef CONFIG_KASAN
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/*
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* The registers used for local register variables are also used
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* when KASAN is active. When KASAN is active we use regular variables
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* at the cost of including cache access latency to these variables
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* in the measurements.
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*/
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unsigned int line_size;
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unsigned int size;
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void *mem_r;
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#else
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register unsigned int line_size asm("esi");
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register unsigned int size asm("edi");
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#ifdef CONFIG_X86_64
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register void *mem_r asm("rbx");
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#else
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register void *mem_r asm("ebx");
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#endif /* CONFIG_X86_64 */
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#endif /* CONFIG_KASAN */
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/*
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* Non-architectural event for the Goldmont Microarchitecture
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* from Intel x86 Architecture Software Developer Manual (SDM):
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* MEM_LOAD_UOPS_RETIRED D1H (event number)
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* Umask values:
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* L1_HIT 01H
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* L2_HIT 02H
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* L1_MISS 08H
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* L2_MISS 10H
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*/
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/*
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* Start by setting flags for IA32_PERFEVTSELx:
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* OS (Operating system mode) 0x2
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* INT (APIC interrupt enable) 0x10
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* EN (Enable counter) 0x40
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*
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* Then add the Umask value and event number to select performance
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* event.
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*/
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switch (boot_cpu_data.x86_model) {
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_GEMINI_LAKE:
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l2_hit_bits = (0x52ULL << 16) | (0x2 << 8) | 0xd1;
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l2_miss_bits = (0x52ULL << 16) | (0x10 << 8) | 0xd1;
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break;
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default:
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goto out;
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}
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local_irq_disable();
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/*
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* Call wrmsr direcly to avoid the local register variables from
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* being overwritten due to reordering of their assignment with
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* the wrmsr calls.
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*/
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__wrmsr(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits, 0x0);
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/* Disable events and reset counters */
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0, 0x0);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 1, 0x0);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_PERFCTR0, 0x0);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_PERFCTR0 + 1, 0x0);
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/* Set and enable the L2 counters */
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0, l2_hit_bits);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 1, l2_miss_bits);
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mem_r = plr->kmem;
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size = plr->size;
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line_size = plr->line_size;
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for (i = 0; i < size; i += line_size) {
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asm volatile("mov (%0,%1,1), %%eax\n\t"
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:
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: "r" (mem_r), "r" (i)
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: "%eax", "memory");
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}
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/*
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* Call wrmsr directly (no tracing) to not influence
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* the cache access counters as they are disabled.
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*/
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0,
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l2_hit_bits & ~(0x40ULL << 16));
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 1,
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l2_miss_bits & ~(0x40ULL << 16));
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l2_hits = native_read_pmc(0);
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l2_miss = native_read_pmc(1);
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wrmsr(MSR_MISC_FEATURE_CONTROL, 0x0, 0x0);
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local_irq_enable();
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trace_pseudo_lock_l2(l2_hits, l2_miss);
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out:
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plr->thread_done = 1;
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wake_up_interruptible(&plr->lock_thread_wq);
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return 0;
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}
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/**
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* pseudo_lock_measure_cycles - Trigger latency measure to pseudo-locked region
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*
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@ -844,12 +959,12 @@ static int measure_cycles_lat_fn(void *_plr)
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*
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* Return: 0 on success, <0 on failure
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*/
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static int pseudo_lock_measure_cycles(struct rdtgroup *rdtgrp)
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static int pseudo_lock_measure_cycles(struct rdtgroup *rdtgrp, int sel)
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{
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struct pseudo_lock_region *plr = rdtgrp->plr;
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struct task_struct *thread;
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unsigned int cpu;
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int ret;
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int ret = -1;
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cpus_read_lock();
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mutex_lock(&rdtgroup_mutex);
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@ -866,9 +981,19 @@ static int pseudo_lock_measure_cycles(struct rdtgroup *rdtgrp)
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goto out;
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}
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thread = kthread_create_on_node(measure_cycles_lat_fn, plr,
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cpu_to_node(cpu),
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"pseudo_lock_measure/%u", cpu);
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if (sel == 1)
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thread = kthread_create_on_node(measure_cycles_lat_fn, plr,
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cpu_to_node(cpu),
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"pseudo_lock_measure/%u",
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cpu);
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else if (sel == 2)
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thread = kthread_create_on_node(measure_cycles_perf_fn, plr,
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cpu_to_node(cpu),
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"pseudo_lock_measure/%u",
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cpu);
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else
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goto out;
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if (IS_ERR(thread)) {
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ret = PTR_ERR(thread);
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goto out;
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@ -897,19 +1022,21 @@ static ssize_t pseudo_lock_measure_trigger(struct file *file,
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size_t buf_size;
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char buf[32];
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int ret;
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bool bv;
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int sel;
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buf_size = min(count, (sizeof(buf) - 1));
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if (copy_from_user(buf, user_buf, buf_size))
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return -EFAULT;
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buf[buf_size] = '\0';
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ret = strtobool(buf, &bv);
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if (ret == 0 && bv) {
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ret = kstrtoint(buf, 10, &sel);
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if (ret == 0) {
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if (sel != 1 && sel != 2)
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return -EINVAL;
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ret = debugfs_file_get(file->f_path.dentry);
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if (ret)
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return ret;
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ret = pseudo_lock_measure_cycles(rdtgrp);
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ret = pseudo_lock_measure_cycles(rdtgrp, sel);
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if (ret == 0)
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ret = count;
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debugfs_file_put(file->f_path.dentry);
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@ -15,6 +15,16 @@ TRACE_EVENT(pseudo_lock_mem_latency,
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TP_printk("latency=%u", __entry->latency)
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);
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TRACE_EVENT(pseudo_lock_l2,
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TP_PROTO(u64 l2_hits, u64 l2_miss),
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TP_ARGS(l2_hits, l2_miss),
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TP_STRUCT__entry(__field(u64, l2_hits)
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__field(u64, l2_miss)),
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TP_fast_assign(__entry->l2_hits = l2_hits;
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__entry->l2_miss = l2_miss;),
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TP_printk("hits=%llu miss=%llu",
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__entry->l2_hits, __entry->l2_miss));
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#endif /* _TRACE_PSEUDO_LOCK_H */
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#undef TRACE_INCLUDE_PATH
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