mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-08-27 03:10:12 +00:00
Code Issues Releases Wiki Activity

Merge branch 'net-pcs-xpcs-cleanups-for-clause-73-support'

Browse source 
Russell King says:

====================
net: pcs: xpcs: cleanups for clause 73 support

This series cleans up xpcs code, moving much of the clause 73 code
out of the driver into places where others can make use of it.

Specifically, we add a helper to convert a clause 73 advertisement
to ethtool link modes to mdio.h, and a helper to resolve the clause
73 negotiation state to phylink, which includes the pause modes.

In doing this cleanup, several issues were identified with the
original xpcs implementation:

1) it masks the link partner advertisement with its own advertisement
   so userspace can't see what the full link partner advertisement
   was.
2) it was always setting pause modes irrespective of the advertisements
   on either end of the link.
3) it was reading the STAT1 registers multiple times. Reading STAT1
   has the side effect of unlatching the link-down status, so
   multiple reads should be avoided.

This patch series addresses the first two first by addressing the
issues, and then by moving over to the new helpers. The third issue
is solved by restructuring the xpcs code.
====================

Link: https://lore.kernel.org/r/ZGyR/jDyYTYzRklg@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2023-05-24 09:13:30 -07:00
commit 8a5ad2ea6b
6 changed files with 170 additions and 111 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

159
drivers/net/pcs/pcs-xpcs.c
View file

@ -271,15 +271,12 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs,
})
static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
struct phylink_link_state *state)
struct phylink_link_state *state,
u16 pcs_stat1)
{
int ret;
ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
if (ret < 0)
return ret;
if (ret & MDIO_STAT1_FAULT) {
if (pcs_stat1 & MDIO_STAT1_FAULT) {
xpcs_warn(xpcs, state, "Link fault condition detected!\n");
return -EFAULT;
}
@ -321,37 +318,6 @@ static int xpcs_read_fault_c73(struct dw_xpcs *xpcs,
return 0;
}
static int xpcs_read_link_c73(struct dw_xpcs *xpcs)
{
bool link = true;
int ret;
ret = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
if (ret < 0)
return ret;
if (!(ret & MDIO_STAT1_LSTATUS))
link = false;
return link;
}
static int xpcs_get_max_usxgmii_speed(const unsigned long *supported)
{
int max = SPEED_UNKNOWN;
if (phylink_test(supported, 1000baseKX_Full))
max = SPEED_1000;
if (phylink_test(supported, 2500baseX_Full))
max = SPEED_2500;
if (phylink_test(supported, 10000baseKX4_Full))
max = SPEED_10000;
if (phylink_test(supported, 10000baseKR_Full))
max = SPEED_10000;
return max;
}
static void xpcs_config_usxgmii(struct dw_xpcs *xpcs, int speed)
{
int ret, speed_sel;
@ -478,16 +444,12 @@ static int xpcs_config_aneg_c73(struct dw_xpcs *xpcs,
static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
struct phylink_link_state *state,
const struct xpcs_compat *compat)
const struct xpcs_compat *compat, u16 an_stat1)
{
int ret;
ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
if (ret < 0)
return ret;
if (ret & MDIO_AN_STAT1_COMPLETE) {
ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
if (an_stat1 & MDIO_AN_STAT1_COMPLETE) {
ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA);
if (ret < 0)
return ret;
@ -504,64 +466,32 @@ static int xpcs_aneg_done_c73(struct dw_xpcs *xpcs,
}
static int xpcs_read_lpa_c73(struct dw_xpcs *xpcs,
struct phylink_link_state *state)
struct phylink_link_state *state, u16 an_stat1)
{
int ret;
u16 lpa[3];
int i, ret;
ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
if (ret < 0)
return ret;
if (!(ret & MDIO_AN_STAT1_LPABLE)) {
if (!(an_stat1 & MDIO_AN_STAT1_LPABLE)) {
phylink_clear(state->lp_advertising, Autoneg);
return 0;
}
phylink_set(state->lp_advertising, Autoneg);
/* Clause 73 outcome */
ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL3);
if (ret < 0)
return ret;
/* Read Clause 73 link partner advertisement */
for (i = ARRAY_SIZE(lpa); --i >= 0; ) {
ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i);
if (ret < 0)
return ret;
if (ret & DW_C73_2500KX)
phylink_set(state->lp_advertising, 2500baseX_Full);
lpa[i] = ret;
}
ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL2);
if (ret < 0)
return ret;
mii_c73_mod_linkmode(state->lp_advertising, lpa);
if (ret & DW_C73_1000KX)
phylink_set(state->lp_advertising, 1000baseKX_Full);
if (ret & DW_C73_10000KX4)
phylink_set(state->lp_advertising, 10000baseKX4_Full);
if (ret & DW_C73_10000KR)
phylink_set(state->lp_advertising, 10000baseKR_Full);
ret = xpcs_read(xpcs, MDIO_MMD_AN, DW_SR_AN_LP_ABL1);
if (ret < 0)
return ret;
if (ret & DW_C73_PAUSE)
phylink_set(state->lp_advertising, Pause);
if (ret & DW_C73_ASYM_PAUSE)
phylink_set(state->lp_advertising, Asym_Pause);
linkmode_and(state->lp_advertising, state->lp_advertising,
state->advertising);
return 0;
}
static void xpcs_resolve_lpa_c73(struct dw_xpcs *xpcs,
struct phylink_link_state *state)
{
int max_speed = xpcs_get_max_usxgmii_speed(state->lp_advertising);
state->pause = MLO_PAUSE_TX | MLO_PAUSE_RX;
state->speed = max_speed;
state->duplex = DUPLEX_FULL;
}
static int xpcs_get_max_xlgmii_speed(struct dw_xpcs *xpcs,
struct phylink_link_state *state)
{
@ -924,13 +854,25 @@ static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
const struct xpcs_compat *compat)
{
bool an_enabled;
int pcs_stat1;
int an_stat1;
int ret;
/* The link status bit is latching-low, so it is important to
* avoid unnecessary re-reads of this register to avoid missing
* a link-down event.
*/
pcs_stat1 = xpcs_read(xpcs, MDIO_MMD_PCS, MDIO_STAT1);
if (pcs_stat1 < 0) {
state->link = false;
return pcs_stat1;
}
/* Link needs to be read first ... */
state->link = xpcs_read_link_c73(xpcs) > 0 ? 1 : 0;
state->link = !!(pcs_stat1 & MDIO_STAT1_LSTATUS);
/* ... and then we check the faults. */
ret = xpcs_read_fault_c73(xpcs, state);
ret = xpcs_read_fault_c73(xpcs, state, pcs_stat1);
if (ret) {
ret = xpcs_soft_reset(xpcs, compat);
if (ret)
@ -941,15 +883,38 @@ static int xpcs_get_state_c73(struct dw_xpcs *xpcs,
return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND, NULL);
}
/* There is no point doing anything else if the link is down. */
if (!state->link)
return 0;
an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
state->advertising);
if (an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
state->an_complete = true;
xpcs_read_lpa_c73(xpcs, state);
xpcs_resolve_lpa_c73(xpcs, state);
} else if (an_enabled) {
state->link = 0;
} else if (state->link) {
if (an_enabled) {
/* The link status bit is latching-low, so it is important to
* avoid unnecessary re-reads of this register to avoid missing
* a link-down event.
*/
an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1);
if (an_stat1 < 0) {
state->link = false;
return an_stat1;
}
state->an_complete = xpcs_aneg_done_c73(xpcs, state, compat,
an_stat1);
if (!state->an_complete) {
state->link = false;
return 0;
}
ret = xpcs_read_lpa_c73(xpcs, state, an_stat1);
if (ret < 0) {
state->link = false;
return ret;
}
phylink_resolve_c73(state);
} else {
xpcs_resolve_pma(xpcs, state);
}

3
drivers/net/pcs/pcs-xpcs.h
View file

@ -32,9 +32,6 @@
#define DW_SR_AN_ADV1 0x10
#define DW_SR_AN_ADV2 0x11
#define DW_SR_AN_ADV3 0x12
#define DW_SR_AN_LP_ABL1 0x13
#define DW_SR_AN_LP_ABL2 0x14
#define DW_SR_AN_LP_ABL3 0x15
/* Clause 73 Defines */
/* AN_LP_ABL1 */

54
drivers/net/phy/phylink.c
View file

@ -977,11 +977,10 @@ static void phylink_apply_manual_flow(struct phylink *pl,
state->pause = pl->link_config.pause;
}
static void phylink_resolve_flow(struct phylink_link_state *state)
static void phylink_resolve_an_pause(struct phylink_link_state *state)
{
bool tx_pause, rx_pause;
state->pause = MLO_PAUSE_NONE;
if (state->duplex == DUPLEX_FULL) {
linkmode_resolve_pause(state->advertising,
state->lp_advertising,
@ -1193,7 +1192,8 @@ static void phylink_get_fixed_state(struct phylink *pl,
else if (pl->link_gpio)
state->link = !!gpiod_get_value_cansleep(pl->link_gpio);
phylink_resolve_flow(state);
state->pause = MLO_PAUSE_NONE;
phylink_resolve_an_pause(state);
}
static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)
@ -3212,10 +3212,48 @@ static const struct sfp_upstream_ops sfp_phylink_ops = {
/* Helpers for MAC drivers */
static struct {
int bit;
int speed;
} phylink_c73_priority_resolution[] = {
{ ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, SPEED_100000 },
{ ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, SPEED_100000 },
/* 100GBASE-KP4 and 100GBASE-CR10 not supported */
{ ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, SPEED_40000 },
{ ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, SPEED_40000 },
{ ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, SPEED_10000 },
{ ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, SPEED_10000 },
/* 5GBASE-KR not supported */
{ ETHTOOL_LINK_MODE_2500baseX_Full_BIT, SPEED_2500 },
{ ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, SPEED_1000 },
};
void phylink_resolve_c73(struct phylink_link_state *state)
{
int i;
for (i = 0; i < ARRAY_SIZE(phylink_c73_priority_resolution); i++) {
int bit = phylink_c73_priority_resolution[i].bit;
if (linkmode_test_bit(bit, state->advertising) &&
linkmode_test_bit(bit, state->lp_advertising))
break;
}
if (i < ARRAY_SIZE(phylink_c73_priority_resolution)) {
state->speed = phylink_c73_priority_resolution[i].speed;
state->duplex = DUPLEX_FULL;
} else {
/* negotiation failure */
state->link = false;
}
phylink_resolve_an_pause(state);
}
EXPORT_SYMBOL_GPL(phylink_resolve_c73);
static void phylink_decode_c37_word(struct phylink_link_state *state,
uint16_t config_reg, int speed)
{
bool tx_pause, rx_pause;
int fd_bit;
if (speed == SPEED_2500)
@ -3234,13 +3272,7 @@ static void phylink_decode_c37_word(struct phylink_link_state *state,
state->link = false;
}
linkmode_resolve_pause(state->advertising, state->lp_advertising,
&tx_pause, &rx_pause);
if (tx_pause)
state->pause |= MLO_PAUSE_TX;
if (rx_pause)
state->pause |= MLO_PAUSE_RX;
phylink_resolve_an_pause(state);
}
static void phylink_decode_sgmii_word(struct phylink_link_state *state,

39
include/linux/mdio.h
View file

@ -486,6 +486,45 @@ static inline u32 linkmode_adv_to_mii_10base_t1_t(unsigned long *adv)
return result;
}
/**
* mii_c73_mod_linkmode - convert a Clause 73 advertisement to linkmodes
* @adv: linkmode advertisement setting
* @lpa: array of three u16s containing the advertisement
*
* Convert an IEEE 802.3 Clause 73 advertisement to ethtool link modes.
*/
static inline void mii_c73_mod_linkmode(unsigned long *adv, u16 *lpa)
{
linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,
adv, lpa[0] & MDIO_AN_C73_0_PAUSE);
linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
adv, lpa[0] & MDIO_AN_C73_0_ASM_DIR);
linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_1000BASE_KX);
linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_10GBASE_KX4);
linkmode_mod_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_40GBASE_KR4);
linkmode_mod_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_40GBASE_CR4);
/* 100GBASE_CR10 and 100GBASE_KP4 not implemented */
linkmode_mod_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_100GBASE_KR4);
linkmode_mod_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_100GBASE_CR4);
/* 25GBASE_R_S not implemented */
/* The 25GBASE_R bit can be used for 25Gbase KR or CR modes */
linkmode_mod_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_25GBASE_R);
linkmode_mod_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_25GBASE_R);
linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
adv, lpa[1] & MDIO_AN_C73_1_10GBASE_KR);
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
adv, lpa[2] & MDIO_AN_C73_2_2500BASE_KX);
/* 5GBASE_KR not implemented */
}
int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum,

2
include/linux/phylink.h
View file

@ -656,6 +656,8 @@ int phylink_mii_c22_pcs_config(struct mdio_device *pcs, unsigned int mode,
const unsigned long *advertising);
void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
void phylink_resolve_c73(struct phylink_link_state *state);
void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
struct phylink_link_state *state);

24
include/uapi/linux/mdio.h
View file

@ -231,6 +231,30 @@
#define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */
#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
/* AN Clause 73 linkword */
#define MDIO_AN_C73_0_S_MASK GENMASK(4, 0)
#define MDIO_AN_C73_0_E_MASK GENMASK(9, 5)
#define MDIO_AN_C73_0_PAUSE BIT(10)
#define MDIO_AN_C73_0_ASM_DIR BIT(11)
#define MDIO_AN_C73_0_C2 BIT(12)
#define MDIO_AN_C73_0_RF BIT(13)
#define MDIO_AN_C73_0_ACK BIT(14)
#define MDIO_AN_C73_0_NP BIT(15)
#define MDIO_AN_C73_1_T_MASK GENMASK(4, 0)
#define MDIO_AN_C73_1_1000BASE_KX BIT(5)
#define MDIO_AN_C73_1_10GBASE_KX4 BIT(6)
#define MDIO_AN_C73_1_10GBASE_KR BIT(7)
#define MDIO_AN_C73_1_40GBASE_KR4 BIT(8)
#define MDIO_AN_C73_1_40GBASE_CR4 BIT(9)
#define MDIO_AN_C73_1_100GBASE_CR10 BIT(10)
#define MDIO_AN_C73_1_100GBASE_KP4 BIT(11)
#define MDIO_AN_C73_1_100GBASE_KR4 BIT(12)
#define MDIO_AN_C73_1_100GBASE_CR4 BIT(13)
#define MDIO_AN_C73_1_25GBASE_R_S BIT(14)
#define MDIO_AN_C73_1_25GBASE_R BIT(15)
#define MDIO_AN_C73_2_2500BASE_KX BIT(0)
#define MDIO_AN_C73_2_5GBASE_KR BIT(1)
/* PHY XGXS lane state register. */
#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002