ARM: dt: sun5i: Add A10s SPI controller nodes

The A10s has 3 SPI controllers compatible with the one found in the A10. Add
them in the DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Maxime Ripard 2014-02-22 22:35:56 +01:00
parent 65918e2606
commit 8a689569b1

View file

@ -300,6 +300,28 @@ soc@01c00000 {
#size-cells = <1>;
ranges;
spi0: spi@01c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
interrupts = <10>;
clocks = <&ahb_gates 20>, <&spi0_clk>;
clock-names = "ahb", "mod";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@01c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
clocks = <&ahb_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
emac: ethernet@01c0b000 {
compatible = "allwinner,sun4i-emac";
reg = <0x01c0b000 0x1000>;
@ -316,6 +338,17 @@ mdio@01c0b080 {
#size-cells = <0>;
};
spi2: spi@01c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <12>;
clocks = <&ahb_gates 22>, <&spi2_clk>;
clock-names = "ahb", "mod";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;