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drm/amdgpu: Rename to ras_*_enabled
Rename, ras_hw_supported --> ras_hw_enabled, and ras_features --> ras_enabled, to show that ras_enabled is a subset of ras_hw_enabled, which itself is a subset of the ASIC capability. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
e509965e58
commit
8ab0d6f030
11 changed files with 41 additions and 41 deletions
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@ -1073,8 +1073,8 @@ struct amdgpu_device {
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atomic_t throttling_logging_enabled;
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struct ratelimit_state throttling_logging_rs;
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uint32_t ras_hw_supported;
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uint32_t ras_features;
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uint32_t ras_hw_enabled;
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uint32_t ras_enabled;
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bool in_pci_err_recovery;
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struct pci_saved_state *pci_state;
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@ -5108,7 +5108,7 @@ int amdgpu_device_baco_enter(struct drm_device *dev)
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if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
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return -ENOTSUPP;
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if (ras && adev->ras_features &&
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if (ras && adev->ras_enabled &&
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adev->nbio.funcs->enable_doorbell_interrupt)
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adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
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@ -5128,7 +5128,7 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
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if (ret)
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return ret;
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if (ras && adev->ras_features &&
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if (ras && adev->ras_enabled &&
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adev->nbio.funcs->enable_doorbell_interrupt)
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adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
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@ -986,7 +986,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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if (!ras)
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return -EINVAL;
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ras_mask = (uint64_t)adev->ras_features << 32 | ras->features;
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ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
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return copy_to_user(out, &ras_mask,
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min_t(u64, size, sizeof(ras_mask))) ?
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@ -2146,7 +2146,7 @@ static int psp_load_smu_fw(struct psp_context *psp)
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return 0;
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if ((amdgpu_in_reset(adev) &&
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ras && adev->ras_features &&
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ras && adev->ras_enabled &&
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(adev->asic_type == CHIP_ARCTURUS ||
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adev->asic_type == CHIP_VEGA20)) ||
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(adev->in_runpm &&
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@ -532,7 +532,7 @@ static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj;
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if (!adev->ras_features || !con)
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if (!adev->ras_enabled || !con)
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return NULL;
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if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
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@ -559,7 +559,7 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
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struct ras_manager *obj;
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int i;
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if (!adev->ras_features || !con)
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if (!adev->ras_enabled || !con)
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return NULL;
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if (head) {
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@ -613,7 +613,7 @@ static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
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static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
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struct ras_common_if *head)
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{
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return adev->ras_hw_supported & BIT(head->block);
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return adev->ras_hw_enabled & BIT(head->block);
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}
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static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
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@ -767,7 +767,7 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
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ret = amdgpu_ras_feature_enable(adev, head, 0);
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/* clean gfx block ras features flag */
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if (adev->ras_features && head->block == AMDGPU_RAS_BLOCK__GFX)
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if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
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con->features &= ~BIT(head->block);
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}
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} else
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@ -1072,7 +1072,7 @@ unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
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struct ras_manager *obj;
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struct ras_err_data data = {0, 0};
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if (!adev->ras_features || !con)
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if (!adev->ras_enabled || !con)
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return 0;
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list_for_each_entry(obj, &con->head, node) {
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@ -1595,7 +1595,7 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj;
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if (!adev->ras_features || !con)
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if (!adev->ras_enabled || !con)
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return;
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list_for_each_entry(obj, &con->head, node) {
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@ -1645,7 +1645,7 @@ static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj;
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if (!adev->ras_features || !con)
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if (!adev->ras_enabled || !con)
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return;
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list_for_each_entry(obj, &con->head, node) {
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@ -1959,7 +1959,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
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bool exc_err_limit = false;
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int ret;
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if (adev->ras_features && con)
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if (adev->ras_enabled && con)
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data = &con->eh_data;
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else
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return 0;
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@ -2076,7 +2076,7 @@ static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
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if (strnstr(ctx->vbios_version, "D16406",
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sizeof(ctx->vbios_version)))
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adev->ras_hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX);
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adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
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}
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/*
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@ -2090,7 +2090,7 @@ static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
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*/
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static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
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{
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adev->ras_hw_supported = adev->ras_features = 0;
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adev->ras_hw_enabled = adev->ras_enabled = 0;
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if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
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!amdgpu_ras_asic_supported(adev))
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@ -2099,7 +2099,7 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
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if (!adev->gmc.xgmi.connected_to_cpu) {
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if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
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dev_info(adev->dev, "MEM ECC is active.\n");
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adev->ras_hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
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adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
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1 << AMDGPU_RAS_BLOCK__DF);
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} else {
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dev_info(adev->dev, "MEM ECC is not presented.\n");
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@ -2107,7 +2107,7 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
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if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
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dev_info(adev->dev, "SRAM ECC is active.\n");
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adev->ras_hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
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adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
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1 << AMDGPU_RAS_BLOCK__DF);
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} else {
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dev_info(adev->dev, "SRAM ECC is not presented.\n");
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@ -2115,7 +2115,7 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
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} else {
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/* driver only manages a few IP blocks RAS feature
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* when GPU is connected cpu through XGMI */
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adev->ras_hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX |
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adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
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1 << AMDGPU_RAS_BLOCK__SDMA |
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1 << AMDGPU_RAS_BLOCK__MMHUB);
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}
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@ -2123,10 +2123,10 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
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amdgpu_ras_get_quirks(adev);
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/* hw_supported needs to be aligned with RAS block mask. */
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adev->ras_hw_supported &= AMDGPU_RAS_BLOCK_MASK;
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adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
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adev->ras_features = amdgpu_ras_enable == 0 ? 0 :
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adev->ras_hw_supported & amdgpu_ras_mask;
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adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
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adev->ras_hw_enabled & amdgpu_ras_mask;
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}
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int amdgpu_ras_init(struct amdgpu_device *adev)
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@ -2149,11 +2149,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
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amdgpu_ras_check_supported(adev);
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if (!adev->ras_hw_supported || adev->asic_type == CHIP_VEGA10) {
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if (!adev->ras_hw_enabled || adev->asic_type == CHIP_VEGA10) {
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/* set gfx block ras context feature for VEGA20 Gaming
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* send ras disable cmd to ras ta during ras late init.
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*/
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if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
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if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
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con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
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return 0;
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@ -2204,7 +2204,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
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dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
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"hardware ability[%x] ras_mask[%x]\n",
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adev->ras_hw_supported, adev->ras_features);
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adev->ras_hw_enabled, adev->ras_enabled);
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return 0;
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release_con:
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@ -2319,7 +2319,7 @@ void amdgpu_ras_resume(struct amdgpu_device *adev)
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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struct ras_manager *obj, *tmp;
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if (!adev->ras_features || !con) {
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if (!adev->ras_enabled || !con) {
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/* clean ras context for VEGA20 Gaming after send ras disable cmd */
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amdgpu_release_ras_context(adev);
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@ -2365,7 +2365,7 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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if (!adev->ras_features || !con)
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if (!adev->ras_enabled || !con)
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return;
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amdgpu_ras_disable_all_features(adev, 0);
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@ -2379,7 +2379,7 @@ int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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if (!adev->ras_features || !con)
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if (!adev->ras_enabled || !con)
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return 0;
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/* Need disable ras on all IPs here before ip [hw/sw]fini */
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@ -2392,7 +2392,7 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
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{
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struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
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if (!adev->ras_features || !con)
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if (!adev->ras_enabled || !con)
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return 0;
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amdgpu_ras_fs_fini(adev);
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@ -2412,7 +2412,7 @@ int amdgpu_ras_fini(struct amdgpu_device *adev)
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void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
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{
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amdgpu_ras_check_supported(adev);
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if (!adev->ras_hw_supported)
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if (!adev->ras_hw_enabled)
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return;
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if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
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@ -2441,7 +2441,7 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev)
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if (!con)
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return;
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if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
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if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
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con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
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amdgpu_ras_set_context(adev, NULL);
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kfree(con);
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@ -475,7 +475,7 @@ static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
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if (block >= AMDGPU_RAS_BLOCK_COUNT)
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return 0;
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return ras && (adev->ras_features & (1 << block));
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return ras && (adev->ras_enabled & (1 << block));
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}
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int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
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@ -1262,7 +1262,7 @@ static int gmc_v9_0_late_init(void *handle)
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* writes, while disables HBM ECC for vega10.
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*/
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if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
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if (!(adev->ras_features & (1 << AMDGPU_RAS_BLOCK__UMC))) {
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if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
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if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
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adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
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}
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int ret = 0;
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/* avoid NBIF got stuck when do RAS recovery in BACO reset */
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if (ras && adev->ras_features)
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if (ras && adev->ras_enabled)
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adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
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ret = amdgpu_dpm_baco_reset(adev);
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return ret;
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/* re-enable doorbell interrupt after BACO exit */
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if (ras && adev->ras_features)
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if (ras && adev->ras_enabled)
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adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
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return 0;
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@ -710,7 +710,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
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* 1. PMFW version > 0x284300: all cases use baco
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* 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
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*/
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if (ras && adev->ras_features &&
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if (ras && adev->ras_enabled &&
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adev->pm.fw_version <= 0x283400)
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baco_reset = false;
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break;
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@ -1430,13 +1430,13 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
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adev = (struct amdgpu_device *)(dev->gpu->kgd);
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/* kfd only concerns sram ecc on GFX and HBM ecc on UMC */
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dev->node_props.capability |=
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((adev->ras_features & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
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((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
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HSA_CAP_SRAM_EDCSUPPORTED : 0;
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dev->node_props.capability |= ((adev->ras_features & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
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dev->node_props.capability |= ((adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
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HSA_CAP_MEM_EDCSUPPORTED : 0;
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if (adev->asic_type != CHIP_VEGA10)
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dev->node_props.capability |= (adev->ras_features != 0) ?
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dev->node_props.capability |= (adev->ras_enabled != 0) ?
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HSA_CAP_RASEVENTNOTIFY : 0;
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/* SVM API and HMM page migration work together, device memory type
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@ -85,7 +85,7 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
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return 0;
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if (state == BACO_STATE_IN) {
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if (!ras || !adev->ras_features) {
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if (!ras || !adev->ras_enabled) {
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data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
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data |= 0x80000000;
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WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
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@ -1531,7 +1531,7 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
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NULL);
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break;
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default:
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if (!ras || !adev->ras_features ||
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if (!ras || !adev->ras_enabled ||
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adev->gmc.xgmi.pending_reset) {
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if (adev->asic_type == CHIP_ARCTURUS) {
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data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
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