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drm/amdgpu: add vcn enc ring type and functions
Add the ring function callbacks for the encode rings. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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101c6fee53
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3 changed files with 180 additions and 1 deletions
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@ -48,7 +48,8 @@ enum amdgpu_ring_type {
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AMDGPU_RING_TYPE_VCE,
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AMDGPU_RING_TYPE_VCE,
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AMDGPU_RING_TYPE_KIQ,
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AMDGPU_RING_TYPE_KIQ,
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AMDGPU_RING_TYPE_UVD_ENC,
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AMDGPU_RING_TYPE_UVD_ENC,
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AMDGPU_RING_TYPE_VCN_DEC
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AMDGPU_RING_TYPE_VCN_DEC,
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AMDGPU_RING_TYPE_VCN_ENC
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};
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};
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struct amdgpu_device;
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struct amdgpu_device;
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@ -37,6 +37,14 @@
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#define VCN_DEC_CMD_PACKET_START 0x0000000a
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#define VCN_DEC_CMD_PACKET_START 0x0000000a
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#define VCN_DEC_CMD_PACKET_END 0x0000000b
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#define VCN_DEC_CMD_PACKET_END 0x0000000b
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#define VCN_ENC_CMD_NO_OP 0x00000000
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#define VCN_ENC_CMD_END 0x00000001
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#define VCN_ENC_CMD_IB 0x00000002
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#define VCN_ENC_CMD_FENCE 0x00000003
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#define VCN_ENC_CMD_TRAP 0x00000004
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#define VCN_ENC_CMD_REG_WRITE 0x0000000b
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#define VCN_ENC_CMD_REG_WAIT 0x0000000c
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struct amdgpu_vcn {
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struct amdgpu_vcn {
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struct amdgpu_bo *vcpu_bo;
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struct amdgpu_bo *vcpu_bo;
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void *cpu_addr;
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void *cpu_addr;
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@ -38,6 +38,7 @@
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static int vcn_v1_0_start(struct amdgpu_device *adev);
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static int vcn_v1_0_start(struct amdgpu_device *adev);
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static int vcn_v1_0_stop(struct amdgpu_device *adev);
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static int vcn_v1_0_stop(struct amdgpu_device *adev);
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static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
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static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
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static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
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static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
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static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
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/**
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/**
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@ -54,6 +55,7 @@ static int vcn_v1_0_early_init(void *handle)
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adev->vcn.num_enc_rings = 2;
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adev->vcn.num_enc_rings = 2;
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vcn_v1_0_set_dec_ring_funcs(adev);
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vcn_v1_0_set_dec_ring_funcs(adev);
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vcn_v1_0_set_enc_ring_funcs(adev);
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vcn_v1_0_set_irq_funcs(adev);
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vcn_v1_0_set_irq_funcs(adev);
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return 0;
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return 0;
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@ -688,6 +690,141 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
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vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
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vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
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}
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}
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/**
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* vcn_v1_0_enc_ring_get_rptr - get enc read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware enc read pointer
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*/
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static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vcn.ring_enc[0])
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR));
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else
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2));
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}
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/**
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* vcn_v1_0_enc_ring_get_wptr - get enc write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware enc write pointer
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*/
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static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vcn.ring_enc[0])
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR));
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else
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return RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2));
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}
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/**
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* vcn_v1_0_enc_ring_set_wptr - set enc write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the enc write pointer to the hardware
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*/
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static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vcn.ring_enc[0])
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR),
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lower_32_bits(ring->wptr));
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else
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WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2),
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lower_32_bits(ring->wptr));
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}
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/**
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* vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
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*
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* @ring: amdgpu_ring pointer
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* @fence: fence to emit
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*
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* Write enc a fence and a trap command to the ring.
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*/
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static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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u64 seq, unsigned flags)
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{
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WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
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amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
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amdgpu_ring_write(ring, addr);
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amdgpu_ring_write(ring, upper_32_bits(addr));
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amdgpu_ring_write(ring, seq);
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amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
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}
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static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
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{
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amdgpu_ring_write(ring, VCN_ENC_CMD_END);
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}
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/**
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* vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
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*
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* @ring: amdgpu_ring pointer
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* @ib: indirect buffer to execute
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*
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* Write enc ring commands to execute the indirect buffer
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*/
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static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
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struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
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{
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amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
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amdgpu_ring_write(ring, vm_id);
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amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring, ib->length_dw);
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}
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static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned int vm_id, uint64_t pd_addr)
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
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unsigned eng = ring->vm_inv_eng;
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pd_addr = pd_addr | 0x1; /* valid bit */
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/* now only use physical base address of PDE and valid */
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BUG_ON(pd_addr & 0xFFFF00000000003EULL);
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amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
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amdgpu_ring_write(ring,
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(hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
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amdgpu_ring_write(ring, upper_32_bits(pd_addr));
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amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
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amdgpu_ring_write(ring,
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(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
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amdgpu_ring_write(ring, lower_32_bits(pd_addr));
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amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
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amdgpu_ring_write(ring,
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(hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
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amdgpu_ring_write(ring, 0xffffffff);
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amdgpu_ring_write(ring, lower_32_bits(pd_addr));
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/* flush TLB */
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amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
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amdgpu_ring_write(ring, (hub->vm_inv_eng0_req + eng) << 2);
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amdgpu_ring_write(ring, req);
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/* wait for flush */
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amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
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amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
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amdgpu_ring_write(ring, 1 << vm_id);
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amdgpu_ring_write(ring, 1 << vm_id);
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}
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static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
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static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_irq_src *source,
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unsigned type,
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unsigned type,
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@ -755,12 +892,45 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
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.end_use = amdgpu_vcn_ring_end_use,
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.end_use = amdgpu_vcn_ring_end_use,
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};
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};
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static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_ENC,
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.align_mask = 0x3f,
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.nop = VCN_ENC_CMD_NO_OP,
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.support_64bit_ptrs = false,
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.get_rptr = vcn_v1_0_enc_ring_get_rptr,
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.get_wptr = vcn_v1_0_enc_ring_get_wptr,
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.set_wptr = vcn_v1_0_enc_ring_set_wptr,
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.emit_frame_size =
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17 * AMDGPU_MAX_VMHUBS + /* vcn_v1_0_enc_ring_emit_vm_flush */
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5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
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1, /* vcn_v1_0_enc_ring_insert_end */
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.emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
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.emit_ib = vcn_v1_0_enc_ring_emit_ib,
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.emit_fence = vcn_v1_0_enc_ring_emit_fence,
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.emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
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.insert_nop = amdgpu_ring_insert_nop,
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.insert_end = vcn_v1_0_enc_ring_insert_end,
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_vcn_ring_begin_use,
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.end_use = amdgpu_vcn_ring_end_use,
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};
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static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
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static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
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{
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{
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adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
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adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
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DRM_INFO("VCN decode is enabled in VM mode\n");
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DRM_INFO("VCN decode is enabled in VM mode\n");
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}
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}
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static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
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{
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int i;
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for (i = 0; i < adev->vcn.num_enc_rings; ++i)
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adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
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DRM_INFO("VCN encode is enabled in VM mode\n");
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}
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static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
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static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
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.set = vcn_v1_0_set_interrupt_state,
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.set = vcn_v1_0_set_interrupt_state,
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.process = vcn_v1_0_process_interrupt,
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.process = vcn_v1_0_process_interrupt,
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