mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 10:57:46 +00:00
Changes for .dts files for omaps for v3.18 merge window:
- Updates for gta04 to add gta04a3 model - Add support for Tehnexion TAO3530 boards - Regulator names for beaglebone - Pinctrl related updates for omap5, dra7 and am437 - Model name fix for sbc-t54 - Enable mailbox for various omaps -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUEhVBAAoJEBvUPslcq6VzQYAQAKDnfBYh1UWb5hA7IQtmutih ITnsvB0lhrAK9SRNk3UCmTdLMnc18ZYfA/DBht/tQ8OM53GKA8TF1rmWjuIk9HWa 2cMHuCYa/n96Wkrue1j3M6iaUqT8tS78lX/dKHueF7RGVrc40v5m6vXOLR7Kh97w LIARYZb5xmoFU6kIHrUdNEJ1xyp02qCIkwHK4xIiCQp61OYNYYpXHiyjnIg43U65 duNVXAkTGArYSR0qJUi7Nu9gmakRJVG8vTm9sVyDvHuF9uDbrjRUb9pzLV0j4P0t Xf5ze4FPUTPQEc5AjaK3LgIEhnvT2OYIDlMFsJfwFfeVByWOlxDLiJ1LurK6oZrH lPRF81bP8VS/0th7/HUGGxPO3ddHbtPJHyJxgrOW6Gf4OC5X+HDajrovSTr/j0bq 5CK3bpIMYLoYDzWcXreAueMI5Un77UsOxIR80gvwMbFIeAQUzz0OdvfjxmFX1keE PaMDv6mk1LE2vm32KGVbwwU7ep800bCWNOb2iAuBb4bQh0k6EkxEOnhQgQiYgSsP k3intuxCHVCwMDs29bM4cYlLVwXer6cAVLd6rSlyI3SaoLnAaeP7lqP9yLKS9Dbj tewUG1y67ReYyliqrv3BuZhQZwdSJ6Mgp6JS0aWE0iJbm5fPCyHYobsIh/NKFKoR zBTcOFc1uK+Vi/Q+mXa6 =i9cD -----END PGP SIGNATURE----- Merge tag 'dt-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Merge "omap dts changes for v3.18 merge window" from Tony Lindgren: Changes for .dts files for omaps for v3.18 merge window: - Updates for gta04 to add gta04a3 model - Add support for Tehnexion TAO3530 boards - Regulator names for beaglebone - Pinctrl related updates for omap5, dra7 and am437 - Model name fix for sbc-t54 - Enable mailbox for various omaps * tag 'dt-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (291 commits) ARM: dts: OMAP2+: Add sub mailboxes device node information ARM: dts: dra7-evm: Mark uart1 rxd as wakeup capable ARM: dts: OMAP5 / DRA7: switch over to interrupts-extended property for UART ARM: dts: AM437x: switch to compatible pinctrl ARM: dts: DRA7: switch to compatible pinctrl ARM: dts: OMAP5: switch to compatible pinctrl ARM: dts: am335x-boneblack: Add names for remaining regulators ARM: dts: sbc-t54: fix model property ARM: dts: omap5.dtsi: add DSS RFBI node ARM: dts: omap3: Add HEAD acoustics omap3-ha.dts and omap3-ha-lcd.dts (TAO3530 based) ARM: dts: omap3: Add Technexion Thunder support (TAO3530 SOM based) ARM: dts: omap3: Add Technexion TAO3530 SOM omap3-tao3530.dtsi ARM: OMAP2+: tao3530: Add pdata-quirk for the mmc2 internal clock ARM: OMAP2+: board-generic: add support for AM57xx family ARM: dts: dra72-evm: Add tps65917 PMIC node ARM: dts: dra72-evm: Enable I2C1 node Linux 3.17-rc3 unicore32: Fix build error vexpress/spc: fix a build warning on array bounds spi: sh-msiof: Fix transmit-only DMA transfers ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
8adc36bcd3
363 changed files with 3913 additions and 1763 deletions
|
|
@ -85,6 +85,18 @@ SoCs:
|
|||
- DRA722
|
||||
compatible = "ti,dra722", "ti,dra72", "ti,dra7"
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||||
|
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- AM5728
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||||
compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- AM5726
|
||||
compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7"
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||||
|
||||
- AM5718
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||||
compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7"
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||||
|
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- AM5716
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compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7"
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|
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- AM4372
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compatible = "ti,am4372", "ti,am43"
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|
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|
|
|
|||
107
Documentation/devicetree/bindings/mfd/tc3589x.txt
Normal file
107
Documentation/devicetree/bindings/mfd/tc3589x.txt
Normal file
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|
@ -0,0 +1,107 @@
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* Toshiba TC3589x multi-purpose expander
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||||
|
||||
The Toshiba TC3589x series are I2C-based MFD devices which may expose the
|
||||
following built-in devices: gpio, keypad, rotator (vibrator), PWM (for
|
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e.g. LEDs or vibrators) The included models are:
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|
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- TC35890
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- TC35892
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- TC35893
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- TC35894
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- TC35895
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- TC35896
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|
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Required properties:
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- compatible : must be "toshiba,tc35890", "toshiba,tc35892", "toshiba,tc35893",
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"toshiba,tc35894", "toshiba,tc35895" or "toshiba,tc35896"
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- reg : I2C address of the device
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- interrupt-parent : specifies which IRQ controller we're connected to
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- interrupts : the interrupt on the parent the controller is connected to
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- interrupt-controller : marks the device node as an interrupt controller
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- #interrupt-cells : should be <1>, the first cell is the IRQ offset on this
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TC3589x interrupt controller.
|
||||
|
||||
Optional nodes:
|
||||
|
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- GPIO
|
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This GPIO module inside the TC3589x has 24 (TC35890, TC35892) or 20
|
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(other models) GPIO lines.
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||||
- compatible : must be "toshiba,tc3589x-gpio"
|
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- interrupts : interrupt on the parent, which must be the tc3589x MFD device
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- interrupt-controller : marks the device node as an interrupt controller
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- #interrupt-cells : should be <2>, the first cell is the IRQ offset on this
|
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TC3589x GPIO interrupt controller, the second cell is the interrupt flags
|
||||
in accordance with <dt-bindings/interrupt-controller/irq.h>. The following
|
||||
flags are valid:
|
||||
- IRQ_TYPE_LEVEL_LOW
|
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- IRQ_TYPE_LEVEL_HIGH
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- IRQ_TYPE_EDGE_RISING
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- IRQ_TYPE_EDGE_FALLING
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- IRQ_TYPE_EDGE_BOTH
|
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- gpio-controller : marks the device node as a GPIO controller
|
||||
- #gpio-cells : should be <2>, the first cell is the GPIO offset on this
|
||||
GPIO controller, the second cell is the flags.
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|
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- Keypad
|
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This keypad is the same on all variants, supporting up to 96 different
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keys. The linux-specific properties are modeled on those already existing
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in other input drivers.
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- compatible : must be "toshiba,tc3589x-keypad"
|
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- debounce-delay-ms : debounce interval in milliseconds
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- keypad,num-rows : number of rows in the matrix, see
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bindings/input/matrix-keymap.txt
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- keypad,num-columns : number of columns in the matrix, see
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bindings/input/matrix-keymap.txt
|
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- linux,keymap: the definition can be found in
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bindings/input/matrix-keymap.txt
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- linux,no-autorepeat: do no enable autorepeat feature.
|
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- linux,wakeup: use any event on keypad as wakeup event.
|
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|
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Example:
|
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|
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tc35893@44 {
|
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compatible = "toshiba,tc35893";
|
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reg = <0x44>;
|
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interrupt-parent = <&gpio6>;
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interrupts = <26 IRQ_TYPE_EDGE_RISING>;
|
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|
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interrupt-controller;
|
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#interrupt-cells = <1>;
|
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|
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tc3589x_gpio {
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compatible = "toshiba,tc3589x-gpio";
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interrupts = <0>;
|
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|
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interrupt-controller;
|
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#interrupt-cells = <2>;
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gpio-controller;
|
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#gpio-cells = <2>;
|
||||
};
|
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tc3589x_keypad {
|
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compatible = "toshiba,tc3589x-keypad";
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interrupts = <6>;
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debounce-delay-ms = <4>;
|
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keypad,num-columns = <8>;
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keypad,num-rows = <8>;
|
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linux,no-autorepeat;
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linux,wakeup;
|
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linux,keymap = <0x0301006b
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0x04010066
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0x06040072
|
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0x040200d7
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0x0303006a
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0x0205000e
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0x0607008b
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0x0500001c
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0x0403000b
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0x03040034
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0x05020067
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0x0305006c
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0x040500e7
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0x0005009e
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||||
0x06020073
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0x01030039
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0x07060069
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0x050500d9>;
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};
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};
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|
|
@ -22,7 +22,7 @@ Optional properties:
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|||
width of 8 is assumed.
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||||
|
||||
- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
|
||||
"sw" <deprecated> use "ham1" instead
|
||||
"sw" 1-bit Hamming ecc code via software
|
||||
"hw" <deprecated> use "ham1" instead
|
||||
"hw-romcode" <deprecated> use "ham1" instead
|
||||
"ham1" 1-bit Hamming ecc code
|
||||
|
|
|
|||
|
|
@ -62,7 +62,7 @@ Example:
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|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 32 0x4>;
|
||||
interrupts = <0 16 0x4>;
|
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|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gsbi5_uart_default>;
|
||||
|
|
|
|||
|
|
@ -56,10 +56,10 @@ The dma_buf buffer sharing API usage contains the following steps:
|
|||
size_t size, int flags,
|
||||
const char *exp_name)
|
||||
|
||||
If this succeeds, dma_buf_export allocates a dma_buf structure, and returns a
|
||||
pointer to the same. It also associates an anonymous file with this buffer,
|
||||
so it can be exported. On failure to allocate the dma_buf object, it returns
|
||||
NULL.
|
||||
If this succeeds, dma_buf_export_named allocates a dma_buf structure, and
|
||||
returns a pointer to the same. It also associates an anonymous file with this
|
||||
buffer, so it can be exported. On failure to allocate the dma_buf object,
|
||||
it returns NULL.
|
||||
|
||||
'exp_name' is the name of exporter - to facilitate information while
|
||||
debugging.
|
||||
|
|
@ -76,7 +76,7 @@ The dma_buf buffer sharing API usage contains the following steps:
|
|||
drivers and/or processes.
|
||||
|
||||
Interface:
|
||||
int dma_buf_fd(struct dma_buf *dmabuf)
|
||||
int dma_buf_fd(struct dma_buf *dmabuf, int flags)
|
||||
|
||||
This API installs an fd for the anonymous file associated with this buffer;
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||||
returns either 'fd', or error.
|
||||
|
|
@ -157,7 +157,9 @@ to request use of buffer for allocation.
|
|||
"dma_buf->ops->" indirection from the users of this interface.
|
||||
|
||||
In struct dma_buf_ops, unmap_dma_buf is defined as
|
||||
void (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *);
|
||||
void (*unmap_dma_buf)(struct dma_buf_attachment *,
|
||||
struct sg_table *,
|
||||
enum dma_data_direction);
|
||||
|
||||
unmap_dma_buf signifies the end-of-DMA for the attachment provided. Like
|
||||
map_dma_buf, this API also must be implemented by the exporter.
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ memory image to a dump file on the local disk, or across the network to
|
|||
a remote system.
|
||||
|
||||
Kdump and kexec are currently supported on the x86, x86_64, ppc64, ia64,
|
||||
and s390x architectures.
|
||||
s390x and arm architectures.
|
||||
|
||||
When the system kernel boots, it reserves a small section of memory for
|
||||
the dump-capture kernel. This ensures that ongoing Direct Memory Access
|
||||
|
|
@ -112,7 +112,7 @@ There are two possible methods of using Kdump.
|
|||
2) Or use the system kernel binary itself as dump-capture kernel and there is
|
||||
no need to build a separate dump-capture kernel. This is possible
|
||||
only with the architectures which support a relocatable kernel. As
|
||||
of today, i386, x86_64, ppc64 and ia64 architectures support relocatable
|
||||
of today, i386, x86_64, ppc64, ia64 and arm architectures support relocatable
|
||||
kernel.
|
||||
|
||||
Building a relocatable kernel is advantageous from the point of view that
|
||||
|
|
@ -241,6 +241,13 @@ Dump-capture kernel config options (Arch Dependent, ia64)
|
|||
kernel will be aligned to 64Mb, so if the start address is not then
|
||||
any space below the alignment point will be wasted.
|
||||
|
||||
Dump-capture kernel config options (Arch Dependent, arm)
|
||||
----------------------------------------------------------
|
||||
|
||||
- To use a relocatable kernel,
|
||||
Enable "AUTO_ZRELADDR" support under "Boot" options:
|
||||
|
||||
AUTO_ZRELADDR=y
|
||||
|
||||
Extended crashkernel syntax
|
||||
===========================
|
||||
|
|
@ -256,6 +263,10 @@ The syntax is:
|
|||
crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset]
|
||||
range=start-[end]
|
||||
|
||||
Please note, on arm, the offset is required.
|
||||
crashkernel=<range1>:<size1>[,<range2>:<size2>,...]@offset
|
||||
range=start-[end]
|
||||
|
||||
'start' is inclusive and 'end' is exclusive.
|
||||
|
||||
For example:
|
||||
|
|
@ -296,6 +307,12 @@ Boot into System Kernel
|
|||
on the memory consumption of the kdump system. In general this is not
|
||||
dependent on the memory size of the production system.
|
||||
|
||||
On arm, use "crashkernel=Y@X". Note that the start address of the kernel
|
||||
will be aligned to 128MiB (0x08000000), so if the start address is not then
|
||||
any space below the alignment point may be overwritten by the dump-capture kernel,
|
||||
which means it is possible that the vmcore is not that precise as expected.
|
||||
|
||||
|
||||
Load the Dump-capture Kernel
|
||||
============================
|
||||
|
||||
|
|
@ -315,7 +332,8 @@ For ia64:
|
|||
- Use vmlinux or vmlinuz.gz
|
||||
For s390x:
|
||||
- Use image or bzImage
|
||||
|
||||
For arm:
|
||||
- Use zImage
|
||||
|
||||
If you are using a uncompressed vmlinux image then use following command
|
||||
to load dump-capture kernel.
|
||||
|
|
@ -331,6 +349,15 @@ to load dump-capture kernel.
|
|||
--initrd=<initrd-for-dump-capture-kernel> \
|
||||
--append="root=<root-dev> <arch-specific-options>"
|
||||
|
||||
If you are using a compressed zImage, then use following command
|
||||
to load dump-capture kernel.
|
||||
|
||||
kexec --type zImage -p <dump-capture-kernel-bzImage> \
|
||||
--initrd=<initrd-for-dump-capture-kernel> \
|
||||
--dtb=<dtb-for-dump-capture-kernel> \
|
||||
--append="root=<root-dev> <arch-specific-options>"
|
||||
|
||||
|
||||
Please note, that --args-linux does not need to be specified for ia64.
|
||||
It is planned to make this a no-op on that architecture, but for now
|
||||
it should be omitted
|
||||
|
|
@ -347,6 +374,9 @@ For ppc64:
|
|||
For s390x:
|
||||
"1 maxcpus=1 cgroup_disable=memory"
|
||||
|
||||
For arm:
|
||||
"1 maxcpus=1 reset_devices"
|
||||
|
||||
Notes on loading the dump-capture kernel:
|
||||
|
||||
* By default, the ELF headers are stored in ELF64 format to support
|
||||
|
|
|
|||
|
|
@ -2,26 +2,26 @@ this_cpu operations
|
|||
-------------------
|
||||
|
||||
this_cpu operations are a way of optimizing access to per cpu
|
||||
variables associated with the *currently* executing processor through
|
||||
the use of segment registers (or a dedicated register where the cpu
|
||||
permanently stored the beginning of the per cpu area for a specific
|
||||
processor).
|
||||
variables associated with the *currently* executing processor. This is
|
||||
done through the use of segment registers (or a dedicated register where
|
||||
the cpu permanently stored the beginning of the per cpu area for a
|
||||
specific processor).
|
||||
|
||||
The this_cpu operations add a per cpu variable offset to the processor
|
||||
specific percpu base and encode that operation in the instruction
|
||||
this_cpu operations add a per cpu variable offset to the processor
|
||||
specific per cpu base and encode that operation in the instruction
|
||||
operating on the per cpu variable.
|
||||
|
||||
This means there are no atomicity issues between the calculation of
|
||||
This means that there are no atomicity issues between the calculation of
|
||||
the offset and the operation on the data. Therefore it is not
|
||||
necessary to disable preempt or interrupts to ensure that the
|
||||
necessary to disable preemption or interrupts to ensure that the
|
||||
processor is not changed between the calculation of the address and
|
||||
the operation on the data.
|
||||
|
||||
Read-modify-write operations are of particular interest. Frequently
|
||||
processors have special lower latency instructions that can operate
|
||||
without the typical synchronization overhead but still provide some
|
||||
sort of relaxed atomicity guarantee. The x86 for example can execute
|
||||
RMV (Read Modify Write) instructions like inc/dec/cmpxchg without the
|
||||
without the typical synchronization overhead, but still provide some
|
||||
sort of relaxed atomicity guarantees. The x86, for example, can execute
|
||||
RMW (Read Modify Write) instructions like inc/dec/cmpxchg without the
|
||||
lock prefix and the associated latency penalty.
|
||||
|
||||
Access to the variable without the lock prefix is not synchronized but
|
||||
|
|
@ -30,6 +30,38 @@ data specific to the currently executing processor. Only the current
|
|||
processor should be accessing that variable and therefore there are no
|
||||
concurrency issues with other processors in the system.
|
||||
|
||||
Please note that accesses by remote processors to a per cpu area are
|
||||
exceptional situations and may impact performance and/or correctness
|
||||
(remote write operations) of local RMW operations via this_cpu_*.
|
||||
|
||||
The main use of the this_cpu operations has been to optimize counter
|
||||
operations.
|
||||
|
||||
The following this_cpu() operations with implied preemption protection
|
||||
are defined. These operations can be used without worrying about
|
||||
preemption and interrupts.
|
||||
|
||||
this_cpu_add()
|
||||
this_cpu_read(pcp)
|
||||
this_cpu_write(pcp, val)
|
||||
this_cpu_add(pcp, val)
|
||||
this_cpu_and(pcp, val)
|
||||
this_cpu_or(pcp, val)
|
||||
this_cpu_add_return(pcp, val)
|
||||
this_cpu_xchg(pcp, nval)
|
||||
this_cpu_cmpxchg(pcp, oval, nval)
|
||||
this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
|
||||
this_cpu_sub(pcp, val)
|
||||
this_cpu_inc(pcp)
|
||||
this_cpu_dec(pcp)
|
||||
this_cpu_sub_return(pcp, val)
|
||||
this_cpu_inc_return(pcp)
|
||||
this_cpu_dec_return(pcp)
|
||||
|
||||
|
||||
Inner working of this_cpu operations
|
||||
------------------------------------
|
||||
|
||||
On x86 the fs: or the gs: segment registers contain the base of the
|
||||
per cpu area. It is then possible to simply use the segment override
|
||||
to relocate a per cpu relative address to the proper per cpu area for
|
||||
|
|
@ -48,22 +80,21 @@ results in a single instruction
|
|||
mov ax, gs:[x]
|
||||
|
||||
instead of a sequence of calculation of the address and then a fetch
|
||||
from that address which occurs with the percpu operations. Before
|
||||
from that address which occurs with the per cpu operations. Before
|
||||
this_cpu_ops such sequence also required preempt disable/enable to
|
||||
prevent the kernel from moving the thread to a different processor
|
||||
while the calculation is performed.
|
||||
|
||||
The main use of the this_cpu operations has been to optimize counter
|
||||
operations.
|
||||
Consider the following this_cpu operation:
|
||||
|
||||
this_cpu_inc(x)
|
||||
|
||||
results in the following single instruction (no lock prefix!)
|
||||
The above results in the following single instruction (no lock prefix!)
|
||||
|
||||
inc gs:[x]
|
||||
|
||||
instead of the following operations required if there is no segment
|
||||
register.
|
||||
register:
|
||||
|
||||
int *y;
|
||||
int cpu;
|
||||
|
|
@ -73,10 +104,10 @@ register.
|
|||
(*y)++;
|
||||
put_cpu();
|
||||
|
||||
Note that these operations can only be used on percpu data that is
|
||||
Note that these operations can only be used on per cpu data that is
|
||||
reserved for a specific processor. Without disabling preemption in the
|
||||
surrounding code this_cpu_inc() will only guarantee that one of the
|
||||
percpu counters is correctly incremented. However, there is no
|
||||
per cpu counters is correctly incremented. However, there is no
|
||||
guarantee that the OS will not move the process directly before or
|
||||
after the this_cpu instruction is executed. In general this means that
|
||||
the value of the individual counters for each processor are
|
||||
|
|
@ -86,9 +117,9 @@ that is of interest.
|
|||
Per cpu variables are used for performance reasons. Bouncing cache
|
||||
lines can be avoided if multiple processors concurrently go through
|
||||
the same code paths. Since each processor has its own per cpu
|
||||
variables no concurrent cacheline updates take place. The price that
|
||||
variables no concurrent cache line updates take place. The price that
|
||||
has to be paid for this optimization is the need to add up the per cpu
|
||||
counters when the value of the counter is needed.
|
||||
counters when the value of a counter is needed.
|
||||
|
||||
|
||||
Special operations:
|
||||
|
|
@ -100,33 +131,39 @@ Takes the offset of a per cpu variable (&x !) and returns the address
|
|||
of the per cpu variable that belongs to the currently executing
|
||||
processor. this_cpu_ptr avoids multiple steps that the common
|
||||
get_cpu/put_cpu sequence requires. No processor number is
|
||||
available. Instead the offset of the local per cpu area is simply
|
||||
added to the percpu offset.
|
||||
available. Instead, the offset of the local per cpu area is simply
|
||||
added to the per cpu offset.
|
||||
|
||||
Note that this operation is usually used in a code segment when
|
||||
preemption has been disabled. The pointer is then used to
|
||||
access local per cpu data in a critical section. When preemption
|
||||
is re-enabled this pointer is usually no longer useful since it may
|
||||
no longer point to per cpu data of the current processor.
|
||||
|
||||
|
||||
Per cpu variables and offsets
|
||||
-----------------------------
|
||||
|
||||
Per cpu variables have *offsets* to the beginning of the percpu
|
||||
Per cpu variables have *offsets* to the beginning of the per cpu
|
||||
area. They do not have addresses although they look like that in the
|
||||
code. Offsets cannot be directly dereferenced. The offset must be
|
||||
added to a base pointer of a percpu area of a processor in order to
|
||||
added to a base pointer of a per cpu area of a processor in order to
|
||||
form a valid address.
|
||||
|
||||
Therefore the use of x or &x outside of the context of per cpu
|
||||
operations is invalid and will generally be treated like a NULL
|
||||
pointer dereference.
|
||||
|
||||
In the context of per cpu operations
|
||||
DEFINE_PER_CPU(int, x);
|
||||
|
||||
x is a per cpu variable. Most this_cpu operations take a cpu
|
||||
variable.
|
||||
In the context of per cpu operations the above implies that x is a per
|
||||
cpu variable. Most this_cpu operations take a cpu variable.
|
||||
|
||||
&x is the *offset* a per cpu variable. this_cpu_ptr() takes
|
||||
the offset of a per cpu variable which makes this look a bit
|
||||
strange.
|
||||
int __percpu *p = &x;
|
||||
|
||||
&x and hence p is the *offset* of a per cpu variable. this_cpu_ptr()
|
||||
takes the offset of a per cpu variable which makes this look a bit
|
||||
strange.
|
||||
|
||||
|
||||
Operations on a field of a per cpu structure
|
||||
|
|
@ -152,7 +189,7 @@ If we have an offset to struct s:
|
|||
|
||||
struct s __percpu *ps = &p;
|
||||
|
||||
z = this_cpu_dec(ps->m);
|
||||
this_cpu_dec(ps->m);
|
||||
|
||||
z = this_cpu_inc_return(ps->n);
|
||||
|
||||
|
|
@ -172,29 +209,52 @@ if we do not make use of this_cpu ops later to manipulate fields:
|
|||
Variants of this_cpu ops
|
||||
-------------------------
|
||||
|
||||
this_cpu ops are interrupt safe. Some architecture do not support
|
||||
this_cpu ops are interrupt safe. Some architectures do not support
|
||||
these per cpu local operations. In that case the operation must be
|
||||
replaced by code that disables interrupts, then does the operations
|
||||
that are guaranteed to be atomic and then reenable interrupts. Doing
|
||||
that are guaranteed to be atomic and then re-enable interrupts. Doing
|
||||
so is expensive. If there are other reasons why the scheduler cannot
|
||||
change the processor we are executing on then there is no reason to
|
||||
disable interrupts. For that purpose the __this_cpu operations are
|
||||
provided. For example.
|
||||
disable interrupts. For that purpose the following __this_cpu operations
|
||||
are provided.
|
||||
|
||||
__this_cpu_inc(x);
|
||||
These operations have no guarantee against concurrent interrupts or
|
||||
preemption. If a per cpu variable is not used in an interrupt context
|
||||
and the scheduler cannot preempt, then they are safe. If any interrupts
|
||||
still occur while an operation is in progress and if the interrupt too
|
||||
modifies the variable, then RMW actions can not be guaranteed to be
|
||||
safe.
|
||||
|
||||
Will increment x and will not fallback to code that disables
|
||||
__this_cpu_add()
|
||||
__this_cpu_read(pcp)
|
||||
__this_cpu_write(pcp, val)
|
||||
__this_cpu_add(pcp, val)
|
||||
__this_cpu_and(pcp, val)
|
||||
__this_cpu_or(pcp, val)
|
||||
__this_cpu_add_return(pcp, val)
|
||||
__this_cpu_xchg(pcp, nval)
|
||||
__this_cpu_cmpxchg(pcp, oval, nval)
|
||||
__this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)
|
||||
__this_cpu_sub(pcp, val)
|
||||
__this_cpu_inc(pcp)
|
||||
__this_cpu_dec(pcp)
|
||||
__this_cpu_sub_return(pcp, val)
|
||||
__this_cpu_inc_return(pcp)
|
||||
__this_cpu_dec_return(pcp)
|
||||
|
||||
|
||||
Will increment x and will not fall-back to code that disables
|
||||
interrupts on platforms that cannot accomplish atomicity through
|
||||
address relocation and a Read-Modify-Write operation in the same
|
||||
instruction.
|
||||
|
||||
|
||||
|
||||
&this_cpu_ptr(pp)->n vs this_cpu_ptr(&pp->n)
|
||||
--------------------------------------------
|
||||
|
||||
The first operation takes the offset and forms an address and then
|
||||
adds the offset of the n field.
|
||||
adds the offset of the n field. This may result in two add
|
||||
instructions emitted by the compiler.
|
||||
|
||||
The second one first adds the two offsets and then does the
|
||||
relocation. IMHO the second form looks cleaner and has an easier time
|
||||
|
|
@ -202,4 +262,73 @@ with (). The second form also is consistent with the way
|
|||
this_cpu_read() and friends are used.
|
||||
|
||||
|
||||
Christoph Lameter, April 3rd, 2013
|
||||
Remote access to per cpu data
|
||||
------------------------------
|
||||
|
||||
Per cpu data structures are designed to be used by one cpu exclusively.
|
||||
If you use the variables as intended, this_cpu_ops() are guaranteed to
|
||||
be "atomic" as no other CPU has access to these data structures.
|
||||
|
||||
There are special cases where you might need to access per cpu data
|
||||
structures remotely. It is usually safe to do a remote read access
|
||||
and that is frequently done to summarize counters. Remote write access
|
||||
something which could be problematic because this_cpu ops do not
|
||||
have lock semantics. A remote write may interfere with a this_cpu
|
||||
RMW operation.
|
||||
|
||||
Remote write accesses to percpu data structures are highly discouraged
|
||||
unless absolutely necessary. Please consider using an IPI to wake up
|
||||
the remote CPU and perform the update to its per cpu area.
|
||||
|
||||
To access per-cpu data structure remotely, typically the per_cpu_ptr()
|
||||
function is used:
|
||||
|
||||
|
||||
DEFINE_PER_CPU(struct data, datap);
|
||||
|
||||
struct data *p = per_cpu_ptr(&datap, cpu);
|
||||
|
||||
This makes it explicit that we are getting ready to access a percpu
|
||||
area remotely.
|
||||
|
||||
You can also do the following to convert the datap offset to an address
|
||||
|
||||
struct data *p = this_cpu_ptr(&datap);
|
||||
|
||||
but, passing of pointers calculated via this_cpu_ptr to other cpus is
|
||||
unusual and should be avoided.
|
||||
|
||||
Remote access are typically only for reading the status of another cpus
|
||||
per cpu data. Write accesses can cause unique problems due to the
|
||||
relaxed synchronization requirements for this_cpu operations.
|
||||
|
||||
One example that illustrates some concerns with write operations is
|
||||
the following scenario that occurs because two per cpu variables
|
||||
share a cache-line but the relaxed synchronization is applied to
|
||||
only one process updating the cache-line.
|
||||
|
||||
Consider the following example
|
||||
|
||||
|
||||
struct test {
|
||||
atomic_t a;
|
||||
int b;
|
||||
};
|
||||
|
||||
DEFINE_PER_CPU(struct test, onecacheline);
|
||||
|
||||
There is some concern about what would happen if the field 'a' is updated
|
||||
remotely from one processor and the local processor would use this_cpu ops
|
||||
to update field b. Care should be taken that such simultaneous accesses to
|
||||
data within the same cache line are avoided. Also costly synchronization
|
||||
may be necessary. IPIs are generally recommended in such scenarios instead
|
||||
of a remote write to the per cpu area of another processor.
|
||||
|
||||
Even in cases where the remote writes are rare, please bear in
|
||||
mind that a remote write will evict the cache line from the processor
|
||||
that most likely will access it. If the processor wakes up and finds a
|
||||
missing local cache line of a per cpu area, its performance and hence
|
||||
the wake up times will be affected.
|
||||
|
||||
Christoph Lameter, August 4th, 2014
|
||||
Pranith Kumar, Aug 2nd, 2014
|
||||
|
|
|
|||
13
MAINTAINERS
13
MAINTAINERS
|
|
@ -1279,8 +1279,13 @@ M: Heiko Stuebner <heiko@sntech.de>
|
|||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-rockchip@lists.infradead.org
|
||||
S: Maintained
|
||||
F: arch/arm/boot/dts/rk3*
|
||||
F: arch/arm/mach-rockchip/
|
||||
F: drivers/clk/rockchip/
|
||||
F: drivers/i2c/busses/i2c-rk3x.c
|
||||
F: drivers/*/*rockchip*
|
||||
F: drivers/*/*/*rockchip*
|
||||
F: sound/soc/rockchip/
|
||||
|
||||
ARM/SAMSUNG ARM ARCHITECTURES
|
||||
M: Ben Dooks <ben-linux@fluff.org>
|
||||
|
|
@ -9560,6 +9565,14 @@ S: Maintained
|
|||
F: Documentation/usb/ohci.txt
|
||||
F: drivers/usb/host/ohci*
|
||||
|
||||
USB OVER IP DRIVER
|
||||
M: Valentina Manea <valentina.manea.m@gmail.com>
|
||||
M: Shuah Khan <shuah.kh@samsung.com>
|
||||
L: linux-usb@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/usb/usbip/
|
||||
F: tools/usb/usbip/
|
||||
|
||||
USB PEGASUS DRIVER
|
||||
M: Petko Manolov <petkan@nucleusys.com>
|
||||
L: linux-usb@vger.kernel.org
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 17
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Shuffling Zombie Juror
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -500,10 +500,14 @@ extern inline void writeq(u64 b, volatile void __iomem *addr)
|
|||
#define outb_p outb
|
||||
#define outw_p outw
|
||||
#define outl_p outl
|
||||
#define readb_relaxed(addr) __raw_readb(addr)
|
||||
#define readw_relaxed(addr) __raw_readw(addr)
|
||||
#define readl_relaxed(addr) __raw_readl(addr)
|
||||
#define readq_relaxed(addr) __raw_readq(addr)
|
||||
#define readb_relaxed(addr) __raw_readb(addr)
|
||||
#define readw_relaxed(addr) __raw_readw(addr)
|
||||
#define readl_relaxed(addr) __raw_readl(addr)
|
||||
#define readq_relaxed(addr) __raw_readq(addr)
|
||||
#define writeb_relaxed(b, addr) __raw_writeb(b, addr)
|
||||
#define writew_relaxed(b, addr) __raw_writew(b, addr)
|
||||
#define writel_relaxed(b, addr) __raw_writel(b, addr)
|
||||
#define writeq_relaxed(b, addr) __raw_writeq(b, addr)
|
||||
|
||||
#define mmiowb()
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
#include <uapi/asm/unistd.h>
|
||||
|
||||
#define NR_SYSCALLS 508
|
||||
#define NR_SYSCALLS 511
|
||||
|
||||
#define __ARCH_WANT_OLD_READDIR
|
||||
#define __ARCH_WANT_STAT64
|
||||
|
|
|
|||
|
|
@ -469,5 +469,8 @@
|
|||
#define __NR_process_vm_writev 505
|
||||
#define __NR_kcmp 506
|
||||
#define __NR_finit_module 507
|
||||
#define __NR_sched_setattr 508
|
||||
#define __NR_sched_getattr 509
|
||||
#define __NR_renameat2 510
|
||||
|
||||
#endif /* _UAPI_ALPHA_UNISTD_H */
|
||||
|
|
|
|||
|
|
@ -526,6 +526,9 @@ sys_call_table:
|
|||
.quad sys_process_vm_writev /* 505 */
|
||||
.quad sys_kcmp
|
||||
.quad sys_finit_module
|
||||
.quad sys_sched_setattr
|
||||
.quad sys_sched_getattr
|
||||
.quad sys_renameat2 /* 510 */
|
||||
|
||||
.size sys_call_table, . - sys_call_table
|
||||
.type sys_call_table, @object
|
||||
|
|
|
|||
|
|
@ -581,6 +581,7 @@ void flush_icache_range(unsigned long kstart, unsigned long kend)
|
|||
tot_sz -= sz;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(flush_icache_range);
|
||||
|
||||
/*
|
||||
* General purpose helper to make I and D cache lines consistent.
|
||||
|
|
|
|||
|
|
@ -1983,8 +1983,6 @@ config XIP_PHYS_ADDR
|
|||
config KEXEC
|
||||
bool "Kexec system call (EXPERIMENTAL)"
|
||||
depends on (!SMP || PM_SLEEP_SMP)
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -286,7 +286,11 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
|
|||
omap3-devkit8000.dtb \
|
||||
omap3-evm.dtb \
|
||||
omap3-evm-37xx.dtb \
|
||||
omap3-gta04.dtb \
|
||||
omap3-gta04a3.dtb \
|
||||
omap3-gta04a4.dtb \
|
||||
omap3-gta04a5.dtb \
|
||||
omap3-ha.dtb \
|
||||
omap3-ha-lcd.dtb \
|
||||
omap3-igep0020.dtb \
|
||||
omap3-igep0030.dtb \
|
||||
omap3-ldp.dtb \
|
||||
|
|
@ -309,6 +313,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
|
|||
omap3-sbc-t3517.dtb \
|
||||
omap3-sbc-t3530.dtb \
|
||||
omap3-sbc-t3730.dtb \
|
||||
omap3-thunder.dtb \
|
||||
omap3-zoom3.dtb
|
||||
dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
|
||||
am335x-bone.dtb \
|
||||
|
|
|
|||
|
|
@ -227,6 +227,7 @@ tps: tps@24 {
|
|||
&tps {
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
regulator-name = "vdds_dpr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -249,18 +250,22 @@ dcdc3_reg: regulator@2 {
|
|||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
regulator-name = "vio,vrtc,vdds";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
regulator-name = "vdd_3v3aux";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
regulator-name = "vdd_1v8";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
regulator-name = "vdd_3v3a";
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -354,6 +354,10 @@ mailbox: mailbox@480C8000 {
|
|||
ti,hwmods = "mailbox";
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <8>;
|
||||
mbox_wkupm3: wkup_m3 {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <0 0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@44e31000 {
|
||||
|
|
|
|||
|
|
@ -58,10 +58,12 @@ l2-cache-controller@48242000 {
|
|||
};
|
||||
|
||||
am43xx_pinmux: pinmux@44e10800 {
|
||||
compatible = "pinctrl-single";
|
||||
compatible = "ti,am437-padconf", "pinctrl-single";
|
||||
reg = <0x44e10800 0x31c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
|
@ -168,6 +170,10 @@ mailbox: mailbox@480C8000 {
|
|||
ti,hwmods = "mailbox";
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <8>;
|
||||
mbox_wkupm3: wkup_m3 {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <0 0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@44e31000 {
|
||||
|
|
|
|||
|
|
@ -303,6 +303,8 @@ &uart1 {
|
|||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&dra7_pmx_core 0x3e0>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
|
|
|
|||
|
|
@ -217,10 +217,12 @@ pbias_mmc_reg: pbias_mmc_omap5 {
|
|||
};
|
||||
|
||||
dra7_pmx_core: pinmux@4a003400 {
|
||||
compatible = "pinctrl-single";
|
||||
compatible = "ti,dra7-padconf", "pinctrl-single";
|
||||
reg = <0x4a003400 0x0464>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x3fffffff>;
|
||||
};
|
||||
|
|
@ -245,7 +247,7 @@ gpio1: gpio@4ae10000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@48055000 {
|
||||
|
|
@ -256,7 +258,7 @@ gpio2: gpio@48055000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@48057000 {
|
||||
|
|
@ -267,7 +269,7 @@ gpio3: gpio@48057000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@48059000 {
|
||||
|
|
@ -278,7 +280,7 @@ gpio4: gpio@48059000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@4805b000 {
|
||||
|
|
@ -289,7 +291,7 @@ gpio5: gpio@4805b000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@4805d000 {
|
||||
|
|
@ -300,7 +302,7 @@ gpio6: gpio@4805d000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio7: gpio@48051000 {
|
||||
|
|
@ -311,7 +313,7 @@ gpio7: gpio@48051000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio8: gpio@48053000 {
|
||||
|
|
@ -322,13 +324,13 @@ gpio8: gpio@48053000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart1: serial@4806a000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806a000 0x100>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -337,7 +339,7 @@ uart1: serial@4806a000 {
|
|||
uart2: serial@4806c000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806c000 0x100>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -346,7 +348,7 @@ uart2: serial@4806c000 {
|
|||
uart3: serial@48020000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48020000 0x100>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -355,7 +357,7 @@ uart3: serial@48020000 {
|
|||
uart4: serial@4806e000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806e000 0x100>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -364,7 +366,7 @@ uart4: serial@4806e000 {
|
|||
uart5: serial@48066000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48066000 0x100>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart5";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -373,7 +375,7 @@ uart5: serial@48066000 {
|
|||
uart6: serial@48068000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48068000 0x100>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -382,7 +384,7 @@ uart6: serial@48068000 {
|
|||
uart7: serial@48420000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48420000 0x100>;
|
||||
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart7";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -391,7 +393,7 @@ uart7: serial@48420000 {
|
|||
uart8: serial@48422000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48422000 0x100>;
|
||||
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart8";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -400,7 +402,7 @@ uart8: serial@48422000 {
|
|||
uart9: serial@48424000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48424000 0x100>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart9";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
@ -409,7 +411,7 @@ uart9: serial@48424000 {
|
|||
uart10: serial@4ae2b000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4ae2b000 0x100>;
|
||||
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart10";
|
||||
clock-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -19,6 +19,126 @@ memory {
|
|||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
i2c1_pins: pinmux_i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
|
||||
0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps65917: tps65917@58 {
|
||||
compatible = "ti,tps65917";
|
||||
reg = <0x58>;
|
||||
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
tps65917_pmic {
|
||||
compatible = "ti,tps65917-pmic";
|
||||
|
||||
regulators {
|
||||
smps1_reg: smps1 {
|
||||
/* VDD_MPU */
|
||||
regulator-name = "smps1";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps2_reg: smps2 {
|
||||
/* VDD_CORE */
|
||||
regulator-name = "smps2";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1030000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_GPU IVA DSPEVE */
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
smps4_reg: smps4 {
|
||||
/* VDDS1V8 */
|
||||
regulator-name = "smps4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps5_reg: smps5 {
|
||||
/* VDD_DDR */
|
||||
regulator-name = "smps5";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* LDO1_OUT --> SDIO */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
/* LDO2_OUT --> TP1017 (UNUSED) */
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* VDDA_1V8_PHY */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
/* VDDA_1V8_PLL */
|
||||
regulator-name = "ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,6 +28,12 @@ MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
|
|||
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -38,6 +44,8 @@ &i2c1 {
|
|||
|
||||
pmic: mc34708@8 {
|
||||
compatible = "fsl,mc34708";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
reg = <0x08>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <23 0x8>;
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ reg_usbotg_vbus: usb-otg-vbus {
|
|||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
model = "On-board SPDIF";
|
||||
/* IMX6 doesn't implement this yet */
|
||||
spdif-controller = <&spdif>;
|
||||
spdif-out;
|
||||
|
|
@ -181,11 +181,13 @@ &spdif {
|
|||
};
|
||||
|
||||
&usbh1 {
|
||||
disable-over-current;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
disable-over-current;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ reg_usbotg_vbus: usb-otg-vbus {
|
|||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
model = "Integrated SPDIF";
|
||||
/* IMX6 doesn't implement this yet */
|
||||
spdif-controller = <&spdif>;
|
||||
spdif-out;
|
||||
|
|
@ -130,16 +130,23 @@ pinctrl_cubox_i_spdif: cubox-i-spdif {
|
|||
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbh1: cubox-i-usbh1 {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id {
|
||||
pinctrl_cubox_i_usbotg: cubox-i-usbotg {
|
||||
/*
|
||||
* The Cubox-i pulls this low, but as it's pointless
|
||||
* The Cubox-i pulls ID low, but as it's pointless
|
||||
* leaving it as a pull-up, even if it is just 10uA.
|
||||
*/
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
|
||||
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
|
||||
|
|
@ -173,13 +180,15 @@ &spdif {
|
|||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cubox_i_usbh1>;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>;
|
||||
pinctrl-0 = <&pinctrl_cubox_i_usbotg>;
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ &iomuxc {
|
|||
enet {
|
||||
pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
/* AR8035 reset */
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
|
||||
|
|
|
|||
|
|
@ -159,6 +159,14 @@ mailbox: mailbox@48094000 {
|
|||
ti,hwmods = "mailbox";
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <6>;
|
||||
mbox_dsp: dsp {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <1 0 0>;
|
||||
};
|
||||
mbox_iva: iva {
|
||||
ti,mbox-tx = <2 1 3>;
|
||||
ti,mbox-rx = <3 1 3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@48028000 {
|
||||
|
|
|
|||
|
|
@ -249,6 +249,10 @@ mailbox: mailbox@48094000 {
|
|||
ti,hwmods = "mailbox";
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <6>;
|
||||
mbox_dsp: dsp {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@49018000 {
|
||||
|
|
|
|||
|
|
@ -292,6 +292,7 @@ &twl_gpio {
|
|||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
|
|
|
|||
|
|
@ -26,6 +26,10 @@ memory {
|
|||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
display0 = &lcd;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
|
|
@ -74,9 +78,30 @@ lcd_in: endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
hsusb2_phy: hsusb2_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusb2_pins
|
||||
>;
|
||||
|
||||
hsusb2_pins: pinmux_hsusb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
|
||||
OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
|
||||
OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
|
||||
OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
|
||||
OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
|
||||
OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart1_pins: pinmux_uart1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
|
||||
|
|
@ -141,12 +166,31 @@ dss_dpi_pins: pinmux_dss_dpi_pins {
|
|||
0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusb2_2_pins
|
||||
>;
|
||||
|
||||
hsusb2_2_pins: pinmux_hsusb2_2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
|
||||
OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
|
||||
OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
|
||||
OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
|
||||
OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
|
||||
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
|
||||
>;
|
||||
};
|
||||
|
||||
spi_gpio_pins: spi_gpio_pinmux {
|
||||
pinctrl-single,pins = <0x5a8 (PIN_OUTPUT | MUX_MODE4) /* clk */
|
||||
0x5b6 (PIN_OUTPUT | MUX_MODE4) /* cs */
|
||||
0x5b8 (PIN_OUTPUT | MUX_MODE4) /* tx */
|
||||
0x5b4 (PIN_INPUT | MUX_MODE4) /* rx */
|
||||
pinctrl-single,pins = <
|
||||
OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */
|
||||
OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */
|
||||
OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */
|
||||
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -196,6 +240,9 @@ tca6507@45 {
|
|||
#size-cells = <0>;
|
||||
reg = <0x45>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
gta04_led0: red_aux@0 {
|
||||
label = "gta04:red:aux";
|
||||
reg = <0x0>;
|
||||
|
|
@ -216,11 +263,16 @@ gta04_led4: green_power@4 {
|
|||
label = "gta04:green:power";
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
wifi_reset: wifi_reset@6 {
|
||||
reg = <0x6>;
|
||||
compatible = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
/* compass aka magnetometer */
|
||||
hmc5843@1e {
|
||||
compatible = "honeywell,hmc5843";
|
||||
compatible = "honeywell,hmc5883l";
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
|
|
@ -248,6 +300,14 @@ &usb_otg_hs {
|
|||
power = <50>;
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
port2-mode = "ehci-phy";
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
phys = <0 &hsusb2_phy>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
|
|
@ -286,11 +346,37 @@ &charger {
|
|||
bb_uamp = <150>;
|
||||
};
|
||||
|
||||
/* spare */
|
||||
&vaux1 {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
/* sensors */
|
||||
&vaux2 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* camera */
|
||||
&vaux3 {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
};
|
||||
|
||||
/* WLAN/BT */
|
||||
&vaux4 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
};
|
||||
|
||||
/* GPS LNA */
|
||||
&vsim {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
};
|
||||
|
||||
/* Needed to power the DPI pins */
|
||||
&vpll2 {
|
||||
regulator-always-on;
|
||||
|
|
@ -309,3 +395,57 @@ dpi_out: endpoint {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
|
||||
|
||||
nand@0,0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
nand-bus-width = <16>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
gpmc,device-width = <2>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
x-loader@0 {
|
||||
label = "X-Loader";
|
||||
reg = <0 0x80000>;
|
||||
};
|
||||
|
||||
bootloaders@80000 {
|
||||
label = "U-Boot";
|
||||
reg = <0x80000 0x1e0000>;
|
||||
};
|
||||
|
||||
bootloaders_env@260000 {
|
||||
label = "U-Boot Env";
|
||||
reg = <0x260000 0x20000>;
|
||||
};
|
||||
|
||||
kernel@280000 {
|
||||
label = "Kernel";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
filesystem@680000 {
|
||||
label = "File System";
|
||||
reg = <0x680000 0xf980000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
48
arch/arm/boot/dts/omap3-gta04a3.dts
Normal file
48
arch/arm/boot/dts/omap3-gta04a3.dts
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-gta04.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Goldelico GTA04A3";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
|
||||
/* alternate accelerometer that might be installed on some GTA04A3 boards */
|
||||
lis302@1d {
|
||||
compatible = "st,lis331dlh", "st,lis3lv02d";
|
||||
reg = <0x1d>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
|
||||
Vdd-supply = <&vaux2>;
|
||||
Vdd_IO-supply = <&vaux2>;
|
||||
|
||||
st,click-single-x;
|
||||
st,click-single-y;
|
||||
st,click-single-z;
|
||||
st,click-thresh-x = <8>;
|
||||
st,click-thresh-y = <8>;
|
||||
st,click-thresh-z = <10>;
|
||||
st,click-click-time-limit = <9>;
|
||||
st,click-latency = <50>;
|
||||
st,irq1-click;
|
||||
st,wakeup-x-lo;
|
||||
st,wakeup-x-hi;
|
||||
st,wakeup-y-lo;
|
||||
st,wakeup-y-hi;
|
||||
st,wakeup-z-lo;
|
||||
st,wakeup-z-hi;
|
||||
st,min-limit-x = <32>;
|
||||
st,min-limit-y = <3>;
|
||||
st,min-limit-z = <3>;
|
||||
st,max-limit-x = <3>;
|
||||
st,max-limit-y = <32>;
|
||||
st,max-limit-z = <32>;
|
||||
};
|
||||
};
|
||||
13
arch/arm/boot/dts/omap3-gta04a4.dts
Normal file
13
arch/arm/boot/dts/omap3-gta04a4.dts
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Marek Belisko <marek@goldelico.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-gta04.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Goldelico GTA04A4";
|
||||
};
|
||||
17
arch/arm/boot/dts/omap3-gta04a5.dts
Normal file
17
arch/arm/boot/dts/omap3-gta04a5.dts
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-gta04.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Goldelico GTA04A5";
|
||||
|
||||
sound {
|
||||
ti,jack-det-gpio = <&twl_gpio 2 0>; /* GTA04A5 only */
|
||||
};
|
||||
};
|
||||
88
arch/arm/boot/dts/omap3-ha-common.dtsi
Normal file
88
arch/arm/boot/dts/omap3-ha-common.dtsi
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-tao3530.dtsi"
|
||||
|
||||
/ {
|
||||
gpio_poweroff {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&poweroff_pins>;
|
||||
|
||||
compatible = "gpio-poweroff";
|
||||
gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
sound2_pins: pinmux_sound2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */
|
||||
>;
|
||||
};
|
||||
|
||||
led_blue_pins: pinmux_led_blue_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */
|
||||
>;
|
||||
};
|
||||
|
||||
led_green_pins: pinmux_led_green_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */
|
||||
>;
|
||||
};
|
||||
|
||||
led_red_pins: pinmux_led_red_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */
|
||||
>;
|
||||
};
|
||||
|
||||
poweroff_pins: pinmux_poweroff_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */
|
||||
>;
|
||||
};
|
||||
|
||||
powerdown_input_pins: pinmux_powerdown_input_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */
|
||||
>;
|
||||
};
|
||||
|
||||
fpga_boot0_pins: fpga_boot0_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */
|
||||
OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */
|
||||
OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */
|
||||
OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */
|
||||
>;
|
||||
};
|
||||
|
||||
fpga_boot1_pins: fpga_boot1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */
|
||||
OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */
|
||||
OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */
|
||||
OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
|
||||
&i2c2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
};
|
||||
165
arch/arm/boot/dts/omap3-ha-lcd.dts
Normal file
165
arch/arm/boot/dts/omap3-ha-lcd.dts
Normal file
|
|
@ -0,0 +1,165 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-ha-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM";
|
||||
compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusbb2_pins
|
||||
&powerdown_input_pins
|
||||
&fpga_boot0_pins
|
||||
&fpga_boot1_pins
|
||||
&led_blue_pins
|
||||
&led_green_pins
|
||||
&led_red_pins
|
||||
&touchscreen_wake_pins
|
||||
>;
|
||||
|
||||
touchscreen_irq_pins: pinmux_touchscreen_irq_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
touchscreen_wake_pins: pinmux_touchscreen_wake_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */
|
||||
>;
|
||||
};
|
||||
|
||||
dss_dpi_pins: pinmux_dss_dpi_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
|
||||
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
|
||||
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
|
||||
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
|
||||
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
|
||||
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
|
||||
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
|
||||
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
|
||||
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
|
||||
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
|
||||
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
|
||||
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
|
||||
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
|
||||
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
|
||||
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
|
||||
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
|
||||
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
|
||||
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
|
||||
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
|
||||
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
|
||||
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
|
||||
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
|
||||
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
|
||||
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
|
||||
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
|
||||
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
|
||||
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
|
||||
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
|
||||
>;
|
||||
};
|
||||
|
||||
lte430_pins: pinmux_lte430_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
|
||||
>;
|
||||
};
|
||||
|
||||
backlight_pins: pinmux_backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */
|
||||
&i2c2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
};
|
||||
|
||||
/* Needed to power the DPI pins */
|
||||
&vpll2 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_dpi_pins>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint {
|
||||
remote-endpoint = <&lcd_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
display0 = &lcd0;
|
||||
};
|
||||
|
||||
lcd0: display@0 {
|
||||
compatible = "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <<e430_pins>;
|
||||
enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */
|
||||
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <31250000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <40>;
|
||||
hback-porch = <86>;
|
||||
hsync-len = <1>;
|
||||
vback-porch = <30>;
|
||||
vfront-porch = <13>;
|
||||
vsync-len = <3>;
|
||||
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "gpio-backlight";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&backlight_pins>;
|
||||
gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */
|
||||
|
||||
default-on;
|
||||
};
|
||||
};
|
||||
28
arch/arm/boot/dts/omap3-ha.dts
Normal file
28
arch/arm/boot/dts/omap3-ha.dts
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-ha-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM";
|
||||
compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&hsusbb2_pins
|
||||
&powerdown_input_pins
|
||||
&fpga_boot0_pins
|
||||
&fpga_boot1_pins
|
||||
&led_blue_pins
|
||||
&led_green_pins
|
||||
&led_red_pins
|
||||
>;
|
||||
};
|
||||
|
|
@ -353,7 +353,7 @@ twl_audio: audio {
|
|||
};
|
||||
|
||||
twl_power: power {
|
||||
compatible = "ti,twl4030-power-n900";
|
||||
compatible = "ti,twl4030-power-n900", "ti,twl4030-power-idle-osc-off";
|
||||
ti,use_poweroff;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
337
arch/arm/boot/dts/omap3-tao3530.dtsi
Normal file
337
arch/arm/boot/dts/omap3-tao3530.dtsi
Normal file
|
|
@ -0,0 +1,337 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "omap34xx-hs.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vcc>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
/* HS USB Port 2 Power */
|
||||
hsusb2_power: hsusb2_power_reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "hsusb2_vbus";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
|
||||
startup-delay-us = <70000>;
|
||||
};
|
||||
|
||||
/* HS USB Host PHY on PORT 2 */
|
||||
hsusb2_phy: hsusb2_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */
|
||||
vcc-supply = <&hsusb2_power>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,omap-twl4030";
|
||||
ti,model = "omap3beagle";
|
||||
|
||||
/* McBSP2 is used for onboard sound, same as on beagle */
|
||||
ti,mcbsp = <&mcbsp2>;
|
||||
ti,codec = <&twl_audio>;
|
||||
};
|
||||
|
||||
/* Regulator to enable/switch the vcc of the Wifi module */
|
||||
mmc2_sdio_poweron: regulator-mmc2-sdio-poweron {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "regulator-mmc2-sdio-poweron";
|
||||
regulator-min-microvolt = <3150000>;
|
||||
regulator-max-microvolt = <3150000>;
|
||||
gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */
|
||||
enable-active-low;
|
||||
startup-delay-us = <10000>;
|
||||
};
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
hsusbb2_pins: pinmux_hsusbb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
|
||||
OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
|
||||
OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
|
||||
OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
|
||||
OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
|
||||
OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
|
||||
OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
|
||||
OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
|
||||
OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
|
||||
OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
|
||||
OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
|
||||
OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
|
||||
OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
|
||||
OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
|
||||
OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
|
||||
OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */
|
||||
OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */
|
||||
OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
|
||||
OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins: pinmux_mmc2_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
|
||||
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
|
||||
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
|
||||
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
|
||||
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
|
||||
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
/* wlan GPIO output for WLAN_EN */
|
||||
wlan_gpio: pinmux_wlan_gpio {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins: pinmux_uart3_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
|
||||
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c3_pins: pinmux_i2c3_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */
|
||||
OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
mcspi1_pins: pinmux_mcspi1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
|
||||
OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
|
||||
OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
|
||||
OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcspi3_pins: pinmux_mcspi3_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */
|
||||
OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */
|
||||
OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */
|
||||
OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcbsp3_pins: pinmux_mcbsp3_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */
|
||||
OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */
|
||||
OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */
|
||||
OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */
|
||||
&mcbsp1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcbsp2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <2600000>;
|
||||
|
||||
twl: twl@48 {
|
||||
reg = <0x48>;
|
||||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
twl_audio: audio {
|
||||
compatible = "ti,twl4030-audio";
|
||||
codec {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
};
|
||||
|
||||
&mcspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcspi1_pins>;
|
||||
|
||||
spidev@0 {
|
||||
compatible = "spidev";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
&mcspi3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcspi3_pins>;
|
||||
|
||||
spidev@0 {
|
||||
compatible = "spidev";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
#include "twl4030.dtsi"
|
||||
#include "twl4030_omap3.dtsi"
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
vmmc-supply = <&vmmc1>;
|
||||
vmmc_aux-supply = <&vsim>;
|
||||
cd-gpios = <&twl_gpio 0 0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
// WiFi (Marvell 88W8686) on MMC2/SDIO
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins>;
|
||||
vmmc-supply = <&mmc2_sdio_poweron>;
|
||||
non-removable;
|
||||
bus-width = <4>;
|
||||
cap-power-off-card;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
port2-mode = "ehci-phy";
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
phys = <0 &hsusb2_phy>;
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
/* pullups: BIT(1) */
|
||||
ti,pullups = <0x000002>;
|
||||
/*
|
||||
* pulldowns:
|
||||
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
|
||||
* BIT(15), BIT(16), BIT(17)
|
||||
*/
|
||||
ti,pulldowns = <0x03a1c4>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
};
|
||||
|
||||
&mcbsp3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcbsp3_pins>;
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x00000000 0x01000000>;
|
||||
|
||||
nand@0,0 {
|
||||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
nand-bus-width = <16>;
|
||||
gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
|
||||
ti,nand-ecc-opt = "sw";
|
||||
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <36>;
|
||||
gpmc,cs-wr-off-ns = <36>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <24>;
|
||||
gpmc,adv-wr-off-ns = <36>;
|
||||
gpmc,oe-on-ns = <6>;
|
||||
gpmc,oe-off-ns = <48>;
|
||||
gpmc,we-on-ns = <6>;
|
||||
gpmc,we-off-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <72>;
|
||||
gpmc,wr-cycle-ns = <72>;
|
||||
gpmc,access-ns = <54>;
|
||||
gpmc,wr-access-ns = <30>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
x-loader@0 {
|
||||
label = "X-Loader";
|
||||
reg = <0 0x80000>;
|
||||
};
|
||||
|
||||
bootloaders@80000 {
|
||||
label = "U-Boot";
|
||||
reg = <0x80000 0x1e0000>;
|
||||
};
|
||||
|
||||
bootloaders_env@260000 {
|
||||
label = "U-Boot Env";
|
||||
reg = <0x260000 0x20000>;
|
||||
};
|
||||
|
||||
kernel@280000 {
|
||||
label = "Kernel";
|
||||
reg = <0x280000 0x400000>;
|
||||
};
|
||||
|
||||
filesystem@680000 {
|
||||
label = "File System";
|
||||
reg = <0x680000 0xf980000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_otg_hs {
|
||||
interface-type = <0>;
|
||||
usb-phy = <&usb2_phy>;
|
||||
phys = <&usb2_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
mode = <3>;
|
||||
power = <50>;
|
||||
};
|
||||
|
||||
&vaux2 {
|
||||
regulator-name = "vdd_ehci";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
129
arch/arm/boot/dts/omap3-thunder.dts
Normal file
129
arch/arm/boot/dts/omap3-thunder.dts
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-tao3530.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 Thunder baseboard with TAO3530 SOM";
|
||||
compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3";
|
||||
};
|
||||
|
||||
&omap3_pmx_core {
|
||||
dss_dpi_pins: pinmux_dss_dpi_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
|
||||
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
|
||||
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
|
||||
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
|
||||
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
|
||||
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
|
||||
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
|
||||
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
|
||||
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
|
||||
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
|
||||
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
|
||||
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
|
||||
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
|
||||
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
|
||||
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
|
||||
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
|
||||
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
|
||||
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
|
||||
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
|
||||
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
|
||||
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
|
||||
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
|
||||
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
|
||||
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
|
||||
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
|
||||
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
|
||||
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
|
||||
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
|
||||
>;
|
||||
};
|
||||
|
||||
lte430_pins: pinmux_lte430_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
|
||||
>;
|
||||
};
|
||||
|
||||
backlight_pins: pinmux_backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Needed to power the DPI pins */
|
||||
&vpll2 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_dpi_pins>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint {
|
||||
remote-endpoint = <&lcd_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
display0 = &lcd0;
|
||||
};
|
||||
|
||||
lcd0: display@0 {
|
||||
compatible = "samsung,lte430wq-f0c", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <<e430_pins>;
|
||||
enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */
|
||||
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <9000000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hfront-porch = <3>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <42>;
|
||||
vback-porch = <2>;
|
||||
vfront-porch = <3>;
|
||||
vsync-len = <11>;
|
||||
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "gpio-backlight";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&backlight_pins>;
|
||||
gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */
|
||||
|
||||
default-on;
|
||||
};
|
||||
};
|
||||
|
|
@ -334,6 +334,10 @@ mailbox: mailbox@48094000 {
|
|||
interrupts = <26>;
|
||||
ti,mbox-num-users = <2>;
|
||||
ti,mbox-num-fifos = <2>;
|
||||
mbox_dsp: dsp {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <1 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
mcspi1: spi@48098000 {
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ nand@1,0 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <1 0 0x08000000>;
|
||||
ti,nand-ecc-opt = "ham1";
|
||||
ti,nand-ecc-opt = "sw";
|
||||
nand-bus-width = <8>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <36>;
|
||||
|
|
|
|||
|
|
@ -656,6 +656,14 @@ mailbox: mailbox@4a0f4000 {
|
|||
ti,hwmods = "mailbox";
|
||||
ti,mbox-num-users = <3>;
|
||||
ti,mbox-num-fifos = <8>;
|
||||
mbox_ipu: mbox_ipu {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <1 0 0>;
|
||||
};
|
||||
mbox_dsp: mbox_dsp {
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@4a318000 {
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
/*
|
||||
* Suppport for CompuLab SBC-T54 with CM-T54
|
||||
* Suppport for CompuLab CM-T54 on SB-T54 baseboard
|
||||
*/
|
||||
|
||||
#include "omap5-cm-t54.dts"
|
||||
|
||||
/ {
|
||||
model = "CompuLab SBC-T54 with CM-T54";
|
||||
model = "CompuLab CM-T54 on SB-T54";
|
||||
compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -187,18 +187,22 @@ counter32k: counter@4ae04000 {
|
|||
};
|
||||
|
||||
omap5_pmx_core: pinmux@4a002840 {
|
||||
compatible = "ti,omap4-padconf", "pinctrl-single";
|
||||
compatible = "ti,omap5-padconf", "pinctrl-single";
|
||||
reg = <0x4a002840 0x01b6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0x7fff>;
|
||||
};
|
||||
omap5_pmx_wkup: pinmux@4ae0c840 {
|
||||
compatible = "ti,omap4-padconf", "pinctrl-single";
|
||||
compatible = "ti,omap5-padconf", "pinctrl-single";
|
||||
reg = <0x4ae0c840 0x0038>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0x7fff>;
|
||||
};
|
||||
|
|
@ -447,7 +451,7 @@ mcspi4: spi@480ba000 {
|
|||
uart1: serial@4806a000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806a000 0x100>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
|
@ -455,7 +459,7 @@ uart1: serial@4806a000 {
|
|||
uart2: serial@4806c000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806c000 0x100>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
|
@ -463,7 +467,7 @@ uart2: serial@4806c000 {
|
|||
uart3: serial@48020000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48020000 0x100>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
|
@ -471,7 +475,7 @@ uart3: serial@48020000 {
|
|||
uart4: serial@4806e000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x4806e000 0x100>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
|
@ -479,7 +483,7 @@ uart4: serial@4806e000 {
|
|||
uart5: serial@48066000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48066000 0x100>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart5";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
|
@ -487,7 +491,7 @@ uart5: serial@48066000 {
|
|||
uart6: serial@48068000 {
|
||||
compatible = "ti,omap4-uart";
|
||||
reg = <0x48068000 0x100>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
|
@ -642,6 +646,14 @@ mailbox: mailbox@4a0f4000 {
|
|||
ti,hwmods = "mailbox";
|
||||
ti,mbox-num-users = <3>;
|
||||
ti,mbox-num-fifos = <8>;
|
||||
mbox_ipu: mbox_ipu {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <1 0 0>;
|
||||
};
|
||||
mbox_dsp: mbox_dsp {
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@4ae18000 {
|
||||
|
|
@ -945,6 +957,15 @@ dispc@58001000 {
|
|||
clock-names = "fck";
|
||||
};
|
||||
|
||||
rfbi: encoder@58002000 {
|
||||
compatible = "ti,omap5-rfbi";
|
||||
reg = <0x58002000 0x100>;
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_rfbi";
|
||||
clocks = <&dss_dss_clk>, <&l3_iclk_div>;
|
||||
clock-names = "fck", "ick";
|
||||
};
|
||||
|
||||
dsi1: encoder@58004000 {
|
||||
compatible = "ti,omap5-dsi";
|
||||
reg = <0x58004000 0x200>,
|
||||
|
|
|
|||
|
|
@ -367,10 +367,12 @@ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
|
|||
|
||||
l3_iclk_div: l3_iclk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
compatible = "ti,divider-clock";
|
||||
ti,max-div = <2>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x100>;
|
||||
clocks = <&dpll_core_h12x2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
ti,index-power-of-two;
|
||||
};
|
||||
|
||||
gpu_l3_iclk: gpu_l3_iclk {
|
||||
|
|
@ -383,10 +385,12 @@ gpu_l3_iclk: gpu_l3_iclk {
|
|||
|
||||
l4_root_clk_div: l4_root_clk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
compatible = "ti,divider-clock";
|
||||
ti,max-div = <2>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x100>;
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
ti,index-power-of-two;
|
||||
};
|
||||
|
||||
slimbus1_slimbus_clk: slimbus1_slimbus_clk {
|
||||
|
|
|
|||
|
|
@ -83,10 +83,6 @@ v2v1: regulator-v2v1 {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
clk32kg: regulator-clk32kg {
|
||||
compatible = "ti,twl6030-clk32kg";
|
||||
};
|
||||
|
||||
twl_usb_comparator: usb-comparator {
|
||||
compatible = "ti,twl6030-usb";
|
||||
interrupts = <4>, <10>;
|
||||
|
|
|
|||
|
|
@ -472,7 +472,6 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
|
|||
"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
|
||||
"isb \n\t" \
|
||||
"bl v7_flush_dcache_"__stringify(level)" \n\t" \
|
||||
"clrex \n\t" \
|
||||
"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
|
||||
"bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
|
||||
"mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@
|
|||
#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0
|
||||
#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0
|
||||
#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
|
||||
#define ARM_CPU_PART_MASK 0xff00fff0
|
||||
|
||||
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
|
||||
#define ARM_CPU_XSCALE_ARCH_V1 0x2000
|
||||
|
|
@ -179,7 +180,7 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
|
|||
*/
|
||||
static inline unsigned int __attribute_const__ read_cpuid_part(void)
|
||||
{
|
||||
return read_cpuid_id() & 0xff00fff0;
|
||||
return read_cpuid_id() & ARM_CPU_PART_MASK;
|
||||
}
|
||||
|
||||
static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ typedef struct user_fp elf_fpregset_t;
|
|||
#define R_ARM_ABS32 2
|
||||
#define R_ARM_CALL 28
|
||||
#define R_ARM_JUMP24 29
|
||||
#define R_ARM_TARGET1 38
|
||||
#define R_ARM_V4BX 40
|
||||
#define R_ARM_PREL31 42
|
||||
#define R_ARM_MOVW_ABS_NC 43
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include <linux/cpumask.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cputype.h>
|
||||
|
||||
/*
|
||||
|
|
@ -25,6 +26,20 @@ static inline bool is_smp(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* smp_cpuid_part() - return part id for a given cpu
|
||||
* @cpu: logical cpu id.
|
||||
*
|
||||
* Return: part id of logical cpu passed as argument.
|
||||
*/
|
||||
static inline unsigned int smp_cpuid_part(int cpu)
|
||||
{
|
||||
struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpu);
|
||||
|
||||
return is_smp() ? cpu_info->cpuid & ARM_CPU_PART_MASK :
|
||||
read_cpuid_part();
|
||||
}
|
||||
|
||||
/* all SMP configurations have the extended CPUID registers */
|
||||
#ifndef CONFIG_MMU
|
||||
#define tlb_ops_need_broadcast() 0
|
||||
|
|
|
|||
|
|
@ -208,26 +208,21 @@
|
|||
#endif
|
||||
.endif
|
||||
msr spsr_cxsf, \rpsr
|
||||
#if defined(CONFIG_CPU_V6)
|
||||
ldr r0, [sp]
|
||||
strex r1, r2, [sp] @ clear the exclusive monitor
|
||||
ldmib sp, {r1 - pc}^ @ load r1 - pc, cpsr
|
||||
#elif defined(CONFIG_CPU_32v6K)
|
||||
clrex @ clear the exclusive monitor
|
||||
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
|
||||
#else
|
||||
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
|
||||
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
sub r0, sp, #4 @ uninhabited address
|
||||
strex r1, r2, [r0] @ clear the exclusive monitor
|
||||
#endif
|
||||
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
|
||||
.endm
|
||||
|
||||
.macro restore_user_regs, fast = 0, offset = 0
|
||||
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
|
||||
ldr lr, [sp, #\offset + S_PC]! @ get pc
|
||||
msr spsr_cxsf, r1 @ save in spsr_svc
|
||||
#if defined(CONFIG_CPU_V6)
|
||||
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
strex r1, r2, [sp] @ clear the exclusive monitor
|
||||
#elif defined(CONFIG_CPU_32v6K)
|
||||
clrex @ clear the exclusive monitor
|
||||
#endif
|
||||
.if \fast
|
||||
ldmdb sp, {r1 - lr}^ @ get calling r1 - lr
|
||||
|
|
@ -261,7 +256,10 @@
|
|||
.endif
|
||||
ldr lr, [sp, #S_SP] @ top of the stack
|
||||
ldrd r0, r1, [sp, #S_LR] @ calling lr and pc
|
||||
clrex @ clear the exclusive monitor
|
||||
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
strex r2, r1, [sp, #S_LR] @ clear the exclusive monitor
|
||||
|
||||
stmdb lr!, {r0, r1, \rpsr} @ calling lr and rfe context
|
||||
ldmia sp, {r0 - r12}
|
||||
mov sp, lr
|
||||
|
|
@ -282,13 +280,16 @@
|
|||
.endm
|
||||
#else /* ifdef CONFIG_CPU_V7M */
|
||||
.macro restore_user_regs, fast = 0, offset = 0
|
||||
clrex @ clear the exclusive monitor
|
||||
mov r2, sp
|
||||
load_user_sp_lr r2, r3, \offset + S_SP @ calling sp, lr
|
||||
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
|
||||
ldr lr, [sp, #\offset + S_PC] @ get pc
|
||||
add sp, sp, #\offset + S_SP
|
||||
msr spsr_cxsf, r1 @ save in spsr_svc
|
||||
|
||||
@ We must avoid clrex due to Cortex-A15 erratum #830321
|
||||
strex r1, r2, [sp] @ clear the exclusive monitor
|
||||
|
||||
.if \fast
|
||||
ldmdb sp, {r1 - r12} @ get calling r1 - r12
|
||||
.else
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
|
|||
break;
|
||||
|
||||
case R_ARM_ABS32:
|
||||
case R_ARM_TARGET1:
|
||||
*(u32 *)loc += sym->st_value;
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -36,5 +36,4 @@ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
|
|||
|
||||
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
|
||||
obj-y += brcmstb.o
|
||||
obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,19 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2013-2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __BRCMSTB_H__
|
||||
#define __BRCMSTB_H__
|
||||
|
||||
void brcmstb_secondary_startup(void);
|
||||
|
||||
#endif /* __BRCMSTB_H__ */
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
/*
|
||||
* SMP boot code for secondary CPUs
|
||||
* Based on arch/arm/mach-tegra/headsmp.S
|
||||
*
|
||||
* Copyright (C) 2010 NVIDIA, Inc.
|
||||
* Copyright (C) 2013-2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <asm/assembler.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
.section ".text.head", "ax"
|
||||
|
||||
ENTRY(brcmstb_secondary_startup)
|
||||
/*
|
||||
* Ensure CPU is in a sane state by disabling all IRQs and switching
|
||||
* into SVC mode.
|
||||
*/
|
||||
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
|
||||
|
||||
bl v7_invalidate_l1
|
||||
b secondary_startup
|
||||
ENDPROC(brcmstb_secondary_startup)
|
||||
|
|
@ -1,363 +0,0 @@
|
|||
/*
|
||||
* Broadcom STB CPU SMP and hotplug support for ARM
|
||||
*
|
||||
* Copyright (C) 2013-2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/printk.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cp15.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "brcmstb.h"
|
||||
|
||||
enum {
|
||||
ZONE_MAN_CLKEN_MASK = BIT(0),
|
||||
ZONE_MAN_RESET_CNTL_MASK = BIT(1),
|
||||
ZONE_MAN_MEM_PWR_MASK = BIT(4),
|
||||
ZONE_RESERVED_1_MASK = BIT(5),
|
||||
ZONE_MAN_ISO_CNTL_MASK = BIT(6),
|
||||
ZONE_MANUAL_CONTROL_MASK = BIT(7),
|
||||
ZONE_PWR_DN_REQ_MASK = BIT(9),
|
||||
ZONE_PWR_UP_REQ_MASK = BIT(10),
|
||||
ZONE_BLK_RST_ASSERT_MASK = BIT(12),
|
||||
ZONE_PWR_OFF_STATE_MASK = BIT(25),
|
||||
ZONE_PWR_ON_STATE_MASK = BIT(26),
|
||||
ZONE_DPG_PWR_STATE_MASK = BIT(28),
|
||||
ZONE_MEM_PWR_STATE_MASK = BIT(29),
|
||||
ZONE_RESET_STATE_MASK = BIT(31),
|
||||
CPU0_PWR_ZONE_CTRL_REG = 1,
|
||||
CPU_RESET_CONFIG_REG = 2,
|
||||
};
|
||||
|
||||
static void __iomem *cpubiuctrl_block;
|
||||
static void __iomem *hif_cont_block;
|
||||
static u32 cpu0_pwr_zone_ctrl_reg;
|
||||
static u32 cpu_rst_cfg_reg;
|
||||
static u32 hif_cont_reg;
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
|
||||
|
||||
static int per_cpu_sw_state_rd(u32 cpu)
|
||||
{
|
||||
sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
|
||||
return per_cpu(per_cpu_sw_state, cpu);
|
||||
}
|
||||
|
||||
static void per_cpu_sw_state_wr(u32 cpu, int val)
|
||||
{
|
||||
per_cpu(per_cpu_sw_state, cpu) = val;
|
||||
dmb();
|
||||
sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
|
||||
dsb_sev();
|
||||
}
|
||||
#else
|
||||
static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
|
||||
#endif
|
||||
|
||||
static void __iomem *pwr_ctrl_get_base(u32 cpu)
|
||||
{
|
||||
void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
|
||||
base += (cpu_logical_map(cpu) * 4);
|
||||
return base;
|
||||
}
|
||||
|
||||
static u32 pwr_ctrl_rd(u32 cpu)
|
||||
{
|
||||
void __iomem *base = pwr_ctrl_get_base(cpu);
|
||||
return readl_relaxed(base);
|
||||
}
|
||||
|
||||
static void pwr_ctrl_wr(u32 cpu, u32 val)
|
||||
{
|
||||
void __iomem *base = pwr_ctrl_get_base(cpu);
|
||||
writel(val, base);
|
||||
}
|
||||
|
||||
static void cpu_rst_cfg_set(u32 cpu, int set)
|
||||
{
|
||||
u32 val;
|
||||
val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
|
||||
if (set)
|
||||
val |= BIT(cpu_logical_map(cpu));
|
||||
else
|
||||
val &= ~BIT(cpu_logical_map(cpu));
|
||||
writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
|
||||
}
|
||||
|
||||
static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
|
||||
{
|
||||
const int reg_ofs = cpu_logical_map(cpu) * 8;
|
||||
writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
|
||||
writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
|
||||
}
|
||||
|
||||
static void brcmstb_cpu_boot(u32 cpu)
|
||||
{
|
||||
pr_info("SMP: Booting CPU%d...\n", cpu);
|
||||
|
||||
/*
|
||||
* set the reset vector to point to the secondary_startup
|
||||
* routine
|
||||
*/
|
||||
cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
|
||||
|
||||
/* unhalt the cpu */
|
||||
cpu_rst_cfg_set(cpu, 0);
|
||||
}
|
||||
|
||||
static void brcmstb_cpu_power_on(u32 cpu)
|
||||
{
|
||||
/*
|
||||
* The secondary cores power was cut, so we must go through
|
||||
* power-on initialization.
|
||||
*/
|
||||
u32 tmp;
|
||||
|
||||
pr_info("SMP: Powering up CPU%d...\n", cpu);
|
||||
|
||||
/* Request zone power up */
|
||||
pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
|
||||
|
||||
/* Wait for the power up FSM to complete */
|
||||
do {
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
} while (!(tmp & ZONE_PWR_ON_STATE_MASK));
|
||||
|
||||
per_cpu_sw_state_wr(cpu, 1);
|
||||
}
|
||||
|
||||
static int brcmstb_cpu_get_power_state(u32 cpu)
|
||||
{
|
||||
int tmp = pwr_ctrl_rd(cpu);
|
||||
return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
|
||||
static void brcmstb_cpu_die(u32 cpu)
|
||||
{
|
||||
v7_exit_coherency_flush(all);
|
||||
|
||||
/* Prevent all interrupts from reaching this CPU. */
|
||||
arch_local_irq_disable();
|
||||
|
||||
/*
|
||||
* Final full barrier to ensure everything before this instruction has
|
||||
* quiesced.
|
||||
*/
|
||||
isb();
|
||||
dsb();
|
||||
|
||||
per_cpu_sw_state_wr(cpu, 0);
|
||||
|
||||
/* Sit and wait to die */
|
||||
wfi();
|
||||
|
||||
/* We should never get here... */
|
||||
panic("Spurious interrupt on CPU %d received!\n", cpu);
|
||||
}
|
||||
|
||||
static int brcmstb_cpu_kill(u32 cpu)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
pr_info("SMP: Powering down CPU%d...\n", cpu);
|
||||
|
||||
while (per_cpu_sw_state_rd(cpu))
|
||||
;
|
||||
|
||||
/* Program zone reset */
|
||||
pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
|
||||
ZONE_PWR_DN_REQ_MASK);
|
||||
|
||||
/* Verify zone reset */
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
if (!(tmp & ZONE_RESET_STATE_MASK))
|
||||
pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
|
||||
__func__, cpu);
|
||||
|
||||
/* Wait for power down */
|
||||
do {
|
||||
tmp = pwr_ctrl_rd(cpu);
|
||||
} while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
|
||||
|
||||
/* Settle-time from Broadcom-internal DVT reference code */
|
||||
udelay(7);
|
||||
|
||||
/* Assert reset on the CPU */
|
||||
cpu_rst_cfg_set(cpu, 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HOTPLUG_CPU */
|
||||
|
||||
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
|
||||
{
|
||||
int rc = 0;
|
||||
char *name;
|
||||
struct device_node *syscon_np = NULL;
|
||||
|
||||
name = "syscon-cpu";
|
||||
|
||||
syscon_np = of_parse_phandle(np, name, 0);
|
||||
if (!syscon_np) {
|
||||
pr_err("can't find phandle %s\n", name);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cpubiuctrl_block = of_iomap(syscon_np, 0);
|
||||
if (!cpubiuctrl_block) {
|
||||
pr_err("iomap failed for cpubiuctrl_block\n");
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
|
||||
&cpu0_pwr_zone_ctrl_reg);
|
||||
if (rc) {
|
||||
pr_err("failed to read 1st entry from %s property (%d)\n", name,
|
||||
rc);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
|
||||
&cpu_rst_cfg_reg);
|
||||
if (rc) {
|
||||
pr_err("failed to read 2nd entry from %s property (%d)\n", name,
|
||||
rc);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
if (syscon_np)
|
||||
of_node_put(syscon_np);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int __init setup_hifcont_regs(struct device_node *np)
|
||||
{
|
||||
int rc = 0;
|
||||
char *name;
|
||||
struct device_node *syscon_np = NULL;
|
||||
|
||||
name = "syscon-cont";
|
||||
|
||||
syscon_np = of_parse_phandle(np, name, 0);
|
||||
if (!syscon_np) {
|
||||
pr_err("can't find phandle %s\n", name);
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
hif_cont_block = of_iomap(syscon_np, 0);
|
||||
if (!hif_cont_block) {
|
||||
pr_err("iomap failed for hif_cont_block\n");
|
||||
rc = -EINVAL;
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
/* offset is at top of hif_cont_block */
|
||||
hif_cont_reg = 0;
|
||||
|
||||
cleanup:
|
||||
if (syscon_np)
|
||||
of_node_put(syscon_np);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
|
||||
{
|
||||
int rc;
|
||||
struct device_node *np;
|
||||
char *name;
|
||||
|
||||
name = "brcm,brcmstb-smpboot";
|
||||
np = of_find_compatible_node(NULL, NULL, name);
|
||||
if (!np) {
|
||||
pr_err("can't find compatible node %s\n", name);
|
||||
return;
|
||||
}
|
||||
|
||||
rc = setup_hifcpubiuctrl_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
rc = setup_hifcont_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(boot_lock);
|
||||
|
||||
static void brcmstb_secondary_init(unsigned int cpu)
|
||||
{
|
||||
/*
|
||||
* Synchronise with the boot thread.
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
}
|
||||
|
||||
static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
||||
/*
|
||||
* set synchronisation state between this boot processor
|
||||
* and the secondary one
|
||||
*/
|
||||
spin_lock(&boot_lock);
|
||||
|
||||
/* Bring up power to the core if necessary */
|
||||
if (brcmstb_cpu_get_power_state(cpu) == 0)
|
||||
brcmstb_cpu_power_on(cpu);
|
||||
|
||||
brcmstb_cpu_boot(cpu);
|
||||
|
||||
/*
|
||||
* now the secondary core is starting up let it run its
|
||||
* calibrations, then wait for it to finish
|
||||
*/
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct smp_operations brcmstb_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
|
||||
.smp_secondary_init = brcmstb_secondary_init,
|
||||
.smp_boot_secondary = brcmstb_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_kill = brcmstb_cpu_kill,
|
||||
.cpu_die = brcmstb_cpu_die,
|
||||
#endif
|
||||
};
|
||||
|
||||
CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
|
||||
|
|
@ -43,7 +43,6 @@
|
|||
"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
|
||||
"isb\n\t"\
|
||||
"bl v7_flush_dcache_"__stringify(level)"\n\t" \
|
||||
"clrex\n\t"\
|
||||
"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
|
||||
"bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
|
||||
/* Dummy Load of a device register to avoid Erratum 799270 */ \
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
|
|||
board_nand_data.nr_parts = nr_parts;
|
||||
board_nand_data.devsize = nand_type;
|
||||
|
||||
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
|
||||
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
|
||||
gpmc_nand_init(&board_nand_data, gpmc_t);
|
||||
}
|
||||
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
|
||||
|
|
|
|||
|
|
@ -241,6 +241,8 @@ MACHINE_END
|
|||
|
||||
#ifdef CONFIG_SOC_DRA7XX
|
||||
static const char *dra74x_boards_compat[] __initconst = {
|
||||
"ti,am5728",
|
||||
"ti,am5726",
|
||||
"ti,dra742",
|
||||
"ti,dra7",
|
||||
NULL,
|
||||
|
|
@ -260,6 +262,8 @@ DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
|
|||
MACHINE_END
|
||||
|
||||
static const char *dra72x_boards_compat[] __initconst = {
|
||||
"ti,am5718",
|
||||
"ti,am5716",
|
||||
"ti,dra722",
|
||||
NULL,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -49,7 +49,8 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
|
|||
return 0;
|
||||
|
||||
/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
|
||||
if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
|
||||
if (ecc_opt == OMAP_ECC_HAM1_CODE_HW ||
|
||||
ecc_opt == OMAP_ECC_HAM1_CODE_SW)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -1403,8 +1403,11 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
|
|||
pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
if (!strcmp(s, "ham1") || !strcmp(s, "sw") ||
|
||||
!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
|
||||
|
||||
if (!strcmp(s, "sw"))
|
||||
gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
|
||||
else if (!strcmp(s, "ham1") ||
|
||||
!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
|
||||
gpmc_nand_data->ecc_opt =
|
||||
OMAP_ECC_HAM1_CODE_HW;
|
||||
else if (!strcmp(s, "bch4"))
|
||||
|
|
|
|||
|
|
@ -663,7 +663,7 @@ void __init dra7xxx_check_revision(void)
|
|||
|
||||
default:
|
||||
/* Unknown default to latest silicon rev as default*/
|
||||
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
|
||||
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
|
||||
__func__, idcode, hawkeye, rev);
|
||||
omap_revision = DRA752_REV_ES1_1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
|
|||
|
||||
r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
|
||||
if (!IS_ERR(r)) {
|
||||
dev_warn(&od->pdev->dev,
|
||||
dev_dbg(&od->pdev->dev,
|
||||
"alias %s already exists\n", clk_alias);
|
||||
clk_put(r);
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -2185,6 +2185,8 @@ static int _enable(struct omap_hwmod *oh)
|
|||
oh->mux->pads_dynamic))) {
|
||||
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
|
||||
_reconfigure_io_chain();
|
||||
} else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
|
||||
_reconfigure_io_chain();
|
||||
}
|
||||
|
||||
_add_initiator_dep(oh, mpu_oh);
|
||||
|
|
@ -2291,6 +2293,8 @@ static int _idle(struct omap_hwmod *oh)
|
|||
if (oh->mux && oh->mux->pads_dynamic) {
|
||||
omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
|
||||
_reconfigure_io_chain();
|
||||
} else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
|
||||
_reconfigure_io_chain();
|
||||
}
|
||||
|
||||
oh->_state = _HWMOD_STATE_IDLE;
|
||||
|
|
@ -3345,6 +3349,9 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
|
|||
if (!ois)
|
||||
return 0;
|
||||
|
||||
if (ois[0] == NULL) /* Empty list */
|
||||
return 0;
|
||||
|
||||
if (!linkspace) {
|
||||
if (_alloc_linkspace(ois)) {
|
||||
pr_err("omap_hwmod: could not allocate link space\n");
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
#include "i2c.h"
|
||||
#include "mmc.h"
|
||||
#include "wd_timer.h"
|
||||
#include "soc.h"
|
||||
|
||||
/* Base offset for all DRA7XX interrupts external to MPUSS */
|
||||
#define DRA7XX_IRQ_GIC_START 32
|
||||
|
|
@ -3261,7 +3262,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|||
&dra7xx_l4_per3__usb_otg_ss1,
|
||||
&dra7xx_l4_per3__usb_otg_ss2,
|
||||
&dra7xx_l4_per3__usb_otg_ss3,
|
||||
&dra7xx_l4_per3__usb_otg_ss4,
|
||||
&dra7xx_l3_main_1__vcp1,
|
||||
&dra7xx_l4_per2__vcp1,
|
||||
&dra7xx_l3_main_1__vcp2,
|
||||
|
|
@ -3270,8 +3270,26 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|||
NULL,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
|
||||
&dra7xx_l4_per3__usb_otg_ss4,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
|
||||
NULL,
|
||||
};
|
||||
|
||||
int __init dra7xx_hwmod_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
omap_hwmod_init();
|
||||
return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
|
||||
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
|
||||
|
||||
if (!ret && soc_is_dra74x())
|
||||
return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
|
||||
else if (!ret && soc_is_dra72x())
|
||||
return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -253,6 +253,11 @@ static void __init nokia_n900_legacy_init(void)
|
|||
|
||||
}
|
||||
}
|
||||
|
||||
static void __init omap3_tao3530_legacy_init(void)
|
||||
{
|
||||
hsmmc2_internal_input_clk();
|
||||
}
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
|
|
@ -377,6 +382,7 @@ static struct pdata_init pdata_quirks[] __initdata = {
|
|||
{ "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
|
||||
{ "ti,omap3-zoom3", omap3_zoom_legacy_init, },
|
||||
{ "ti,am3517-evm", am3517_evm_legacy_init, },
|
||||
{ "technexion,omap3-tao3530", omap3_tao3530_legacy_init, },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
{ "ti,omap4-sdp", omap4_sdp_legacy_init, },
|
||||
|
|
|
|||
|
|
@ -245,6 +245,8 @@ IS_AM_SUBCLASS(437x, 0x437)
|
|||
#define soc_is_omap54xx() 0
|
||||
#define soc_is_omap543x() 0
|
||||
#define soc_is_dra7xx() 0
|
||||
#define soc_is_dra74x() 0
|
||||
#define soc_is_dra72x() 0
|
||||
|
||||
#if defined(MULTI_OMAP2)
|
||||
# if defined(CONFIG_ARCH_OMAP2)
|
||||
|
|
@ -393,7 +395,11 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||
|
||||
#if defined(CONFIG_SOC_DRA7XX)
|
||||
#undef soc_is_dra7xx
|
||||
#undef soc_is_dra74x
|
||||
#undef soc_is_dra72x
|
||||
#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
|
||||
#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
|
||||
#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
|
||||
#endif
|
||||
|
||||
/* Various silicon revisions for omap2 */
|
||||
|
|
|
|||
|
|
@ -183,8 +183,8 @@ enum {
|
|||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
/* DIV6 clocks */
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ enum {
|
|||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
/* DIV6 clocks */
|
||||
|
|
|
|||
|
|
@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
|
||||
CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
|
||||
|
|
|
|||
|
|
@ -426,9 +426,15 @@ static int ve_spc_populate_opps(uint32_t cluster)
|
|||
|
||||
static int ve_init_opp_table(struct device *cpu_dev)
|
||||
{
|
||||
int cluster = topology_physical_package_id(cpu_dev->id);
|
||||
int idx, ret = 0, max_opp = info->num_opps[cluster];
|
||||
struct ve_spc_opp *opps = info->opps[cluster];
|
||||
int cluster;
|
||||
int idx, ret = 0, max_opp;
|
||||
struct ve_spc_opp *opps;
|
||||
|
||||
cluster = topology_physical_package_id(cpu_dev->id);
|
||||
cluster = cluster < 0 ? 0 : cluster;
|
||||
|
||||
max_opp = info->num_opps[cluster];
|
||||
opps = info->opps[cluster];
|
||||
|
||||
for (idx = 0; idx < max_opp; idx++, opps++) {
|
||||
ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
|
||||
|
|
@ -537,6 +543,8 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev)
|
|||
spc->hw.init = &init;
|
||||
spc->cluster = topology_physical_package_id(cpu_dev->id);
|
||||
|
||||
spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
|
||||
|
||||
init.name = dev_name(cpu_dev);
|
||||
init.ops = &clk_spc_ops;
|
||||
init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
|
||||
|
|
|
|||
|
|
@ -17,12 +17,6 @@
|
|||
*/
|
||||
.align 5
|
||||
ENTRY(v6_early_abort)
|
||||
#ifdef CONFIG_CPU_V6
|
||||
sub r1, sp, #4 @ Get unused stack location
|
||||
strex r0, r1, [r1] @ Clear the exclusive monitor
|
||||
#elif defined(CONFIG_CPU_32v6K)
|
||||
clrex
|
||||
#endif
|
||||
mrc p15, 0, r1, c5, c0, 0 @ get FSR
|
||||
mrc p15, 0, r0, c6, c0, 0 @ get FAR
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -13,12 +13,6 @@
|
|||
*/
|
||||
.align 5
|
||||
ENTRY(v7_early_abort)
|
||||
/*
|
||||
* The effect of data aborts on on the exclusive access monitor are
|
||||
* UNPREDICTABLE. Do a CLREX to clear the state
|
||||
*/
|
||||
clrex
|
||||
|
||||
mrc p15, 0, r1, c5, c0, 0 @ get FSR
|
||||
mrc p15, 0, r0, c6, c0, 0 @ get FAR
|
||||
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
|
|||
);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL(flush_icache_range);
|
||||
|
||||
void hexagon_clean_dcache_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -549,8 +549,6 @@ source "drivers/sn/Kconfig"
|
|||
config KEXEC
|
||||
bool "kexec system call"
|
||||
depends on !IA64_HP_SIM && (!SMP || HOTPLUG_CPU)
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -91,8 +91,6 @@ config MMU_SUN3
|
|||
config KEXEC
|
||||
bool "kexec system call"
|
||||
depends on M68KCLASSIC
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -2396,8 +2396,6 @@ source "kernel/Kconfig.preempt"
|
|||
|
||||
config KEXEC
|
||||
bool "Kexec system call"
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -399,8 +399,6 @@ config PPC64_SUPPORTS_MEMORY_FAILURE
|
|||
config KEXEC
|
||||
bool "kexec system call"
|
||||
depends on (PPC_BOOK3S || FSL_BOOKE || (44x && !SMP))
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -48,8 +48,6 @@ config ARCH_SUPPORTS_DEBUG_PAGEALLOC
|
|||
|
||||
config KEXEC
|
||||
def_bool y
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
|
||||
config AUDIT_ARCH
|
||||
def_bool y
|
||||
|
|
|
|||
|
|
@ -283,7 +283,10 @@
|
|||
#define __NR_sched_setattr 345
|
||||
#define __NR_sched_getattr 346
|
||||
#define __NR_renameat2 347
|
||||
#define NR_syscalls 348
|
||||
#define __NR_seccomp 348
|
||||
#define __NR_getrandom 349
|
||||
#define __NR_memfd_create 350
|
||||
#define NR_syscalls 351
|
||||
|
||||
/*
|
||||
* There are some system calls that are not present on 64 bit, some
|
||||
|
|
|
|||
|
|
@ -214,3 +214,6 @@ COMPAT_SYSCALL_WRAP3(finit_module, int, fd, const char __user *, uargs, int, fla
|
|||
COMPAT_SYSCALL_WRAP3(sched_setattr, pid_t, pid, struct sched_attr __user *, attr, unsigned int, flags);
|
||||
COMPAT_SYSCALL_WRAP4(sched_getattr, pid_t, pid, struct sched_attr __user *, attr, unsigned int, size, unsigned int, flags);
|
||||
COMPAT_SYSCALL_WRAP5(renameat2, int, olddfd, const char __user *, oldname, int, newdfd, const char __user *, newname, unsigned int, flags);
|
||||
COMPAT_SYSCALL_WRAP3(seccomp, unsigned int, op, unsigned int, flags, const char __user *, uargs)
|
||||
COMPAT_SYSCALL_WRAP3(getrandom, char __user *, buf, size_t, count, unsigned int, flags)
|
||||
COMPAT_SYSCALL_WRAP2(memfd_create, const char __user *, uname, unsigned int, flags)
|
||||
|
|
|
|||
|
|
@ -2060,6 +2060,13 @@ void s390_reset_system(void (*func)(void *), void *data)
|
|||
S390_lowcore.program_new_psw.addr =
|
||||
PSW_ADDR_AMODE | (unsigned long) s390_base_pgm_handler;
|
||||
|
||||
/*
|
||||
* Clear subchannel ID and number to signal new kernel that no CCW or
|
||||
* SCSI IPL has been done (for kexec and kdump)
|
||||
*/
|
||||
S390_lowcore.subchannel_id = 0;
|
||||
S390_lowcore.subchannel_nr = 0;
|
||||
|
||||
/* Store status at absolute zero */
|
||||
store_status();
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/stddef.h>
|
||||
#include <linux/unistd.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/ioport.h>
|
||||
|
|
@ -61,6 +62,7 @@
|
|||
#include <asm/diag.h>
|
||||
#include <asm/os_info.h>
|
||||
#include <asm/sclp.h>
|
||||
#include <asm/sysinfo.h>
|
||||
#include "entry.h"
|
||||
|
||||
/*
|
||||
|
|
@ -766,6 +768,7 @@ static void __init setup_hwcaps(void)
|
|||
#endif
|
||||
|
||||
get_cpu_id(&cpu_id);
|
||||
add_device_randomness(&cpu_id, sizeof(cpu_id));
|
||||
switch (cpu_id.machine) {
|
||||
case 0x9672:
|
||||
#if !defined(CONFIG_64BIT)
|
||||
|
|
@ -803,6 +806,19 @@ static void __init setup_hwcaps(void)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Add system information as device randomness
|
||||
*/
|
||||
static void __init setup_randomness(void)
|
||||
{
|
||||
struct sysinfo_3_2_2 *vmms;
|
||||
|
||||
vmms = (struct sysinfo_3_2_2 *) alloc_page(GFP_KERNEL);
|
||||
if (vmms && stsi(vmms, 3, 2, 2) == 0 && vmms->count)
|
||||
add_device_randomness(&vmms, vmms->count);
|
||||
free_page((unsigned long) vmms);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup function called from init/main.c just after the banner
|
||||
* was printed.
|
||||
|
|
@ -901,6 +917,9 @@ void __init setup_arch(char **cmdline_p)
|
|||
|
||||
/* Setup zfcpdump support */
|
||||
setup_zfcpdump();
|
||||
|
||||
/* Add system specific data to the random pool */
|
||||
setup_randomness();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
|
|
|
|||
|
|
@ -356,3 +356,6 @@ SYSCALL(sys_finit_module,sys_finit_module,compat_sys_finit_module)
|
|||
SYSCALL(sys_sched_setattr,sys_sched_setattr,compat_sys_sched_setattr) /* 345 */
|
||||
SYSCALL(sys_sched_getattr,sys_sched_getattr,compat_sys_sched_getattr)
|
||||
SYSCALL(sys_renameat2,sys_renameat2,compat_sys_renameat2)
|
||||
SYSCALL(sys_seccomp,sys_seccomp,compat_sys_seccomp)
|
||||
SYSCALL(sys_getrandom,sys_getrandom,compat_sys_getrandom)
|
||||
SYSCALL(sys_memfd_create,sys_memfd_create,compat_sys_memfd_create) /* 350 */
|
||||
|
|
|
|||
|
|
@ -598,8 +598,6 @@ source kernel/Kconfig.hz
|
|||
config KEXEC
|
||||
bool "kexec system call (EXPERIMENTAL)"
|
||||
depends on SUPERH32 && MMU
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
help
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -229,6 +229,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
|
|||
|
||||
cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
|
||||
}
|
||||
EXPORT_SYMBOL(flush_icache_range);
|
||||
|
||||
void flush_icache_page(struct vm_area_struct *vma, struct page *page)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -191,8 +191,6 @@ source "kernel/Kconfig.hz"
|
|||
|
||||
config KEXEC
|
||||
bool "kexec system call"
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
---help---
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
|
|||
|
|
@ -183,6 +183,7 @@ void flush_icache_range(unsigned long start, unsigned long end)
|
|||
preempt_enable();
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(flush_icache_range);
|
||||
|
||||
|
||||
/* Called when smp_send_reschedule() triggers IRQ_RESCHEDULE. */
|
||||
|
|
|
|||
|
|
@ -254,7 +254,8 @@ static int setup_frame(struct ksignal *ksig, sigset_t *set,
|
|||
|
||||
err |= setup_sigframe(frame, regs, set);
|
||||
if (err == 0)
|
||||
err |= setup_return(regs, &ksig->ka, frame->retcode, frame, usig);
|
||||
err |= setup_return(regs, &ksig->ka, frame->retcode, frame,
|
||||
ksig->sig);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
@ -276,7 +277,8 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
|
|||
err |= __save_altstack(&frame->sig.uc.uc_stack, regs->UCreg_sp);
|
||||
err |= setup_sigframe(&frame->sig, regs, set);
|
||||
if (err == 0)
|
||||
err |= setup_return(regs, &ksig->ka, frame->sig.retcode, frame, usig);
|
||||
err |= setup_return(regs, &ksig->ka, frame->sig.retcode, frame,
|
||||
ksig->sig);
|
||||
|
||||
if (err == 0) {
|
||||
/*
|
||||
|
|
@ -303,7 +305,6 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs,
|
|||
int syscall)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct task_struct *tsk = current;
|
||||
sigset_t *oldset = sigmask_to_save();
|
||||
int usig = ksig->sig;
|
||||
int ret;
|
||||
|
|
@ -373,7 +374,7 @@ static void do_signal(struct pt_regs *regs, int syscall)
|
|||
if (!user_mode(regs))
|
||||
return;
|
||||
|
||||
if (get_signsl(&ksig)) {
|
||||
if (get_signal(&ksig)) {
|
||||
handle_signal(&ksig, regs, syscall);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,6 +17,4 @@ obj-$(CONFIG_IA32_EMULATION) += ia32/
|
|||
obj-y += platform/
|
||||
obj-y += net/
|
||||
|
||||
ifeq ($(CONFIG_X86_64),y)
|
||||
obj-$(CONFIG_KEXEC) += purgatory/
|
||||
endif
|
||||
obj-$(CONFIG_KEXEC_FILE) += purgatory/
|
||||
|
|
|
|||
|
|
@ -1585,9 +1585,6 @@ source kernel/Kconfig.hz
|
|||
|
||||
config KEXEC
|
||||
bool "kexec system call"
|
||||
select BUILD_BIN2C
|
||||
select CRYPTO
|
||||
select CRYPTO_SHA256
|
||||
---help---
|
||||
kexec is a system call that implements the ability to shutdown your
|
||||
current kernel, and to start another kernel. It is like a reboot
|
||||
|
|
@ -1602,9 +1599,22 @@ config KEXEC
|
|||
interface is strongly in flux, so no good recommendation can be
|
||||
made.
|
||||
|
||||
config KEXEC_FILE
|
||||
bool "kexec file based system call"
|
||||
select BUILD_BIN2C
|
||||
depends on KEXEC
|
||||
depends on X86_64
|
||||
depends on CRYPTO=y
|
||||
depends on CRYPTO_SHA256=y
|
||||
---help---
|
||||
This is new version of kexec system call. This system call is
|
||||
file based and takes file descriptors as system call argument
|
||||
for kernel and initramfs as opposed to list of segments as
|
||||
accepted by previous system call.
|
||||
|
||||
config KEXEC_VERIFY_SIG
|
||||
bool "Verify kernel signature during kexec_file_load() syscall"
|
||||
depends on KEXEC
|
||||
depends on KEXEC_FILE
|
||||
---help---
|
||||
This option makes kernel signature verification mandatory for
|
||||
kexec_file_load() syscall. If kernel is signature can not be
|
||||
|
|
|
|||
|
|
@ -184,11 +184,8 @@ archheaders:
|
|||
$(Q)$(MAKE) $(build)=arch/x86/syscalls all
|
||||
|
||||
archprepare:
|
||||
ifeq ($(CONFIG_KEXEC),y)
|
||||
# Build only for 64bit. No loaders for 32bit yet.
|
||||
ifeq ($(CONFIG_X86_64),y)
|
||||
ifeq ($(CONFIG_KEXEC_FILE),y)
|
||||
$(Q)$(MAKE) $(build)=arch/x86/purgatory arch/x86/purgatory/kexec-purgatory.c
|
||||
endif
|
||||
endif
|
||||
|
||||
###
|
||||
|
|
@ -254,6 +251,7 @@ archclean:
|
|||
$(Q)rm -rf $(objtree)/arch/x86_64
|
||||
$(Q)$(MAKE) $(clean)=$(boot)
|
||||
$(Q)$(MAKE) $(clean)=arch/x86/tools
|
||||
$(Q)$(MAKE) $(clean)=arch/x86/purgatory
|
||||
|
||||
PHONY += kvmconfig
|
||||
kvmconfig:
|
||||
|
|
|
|||
|
|
@ -227,6 +227,8 @@ static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned
|
|||
|
||||
extern void io_apic_eoi(unsigned int apic, unsigned int vector);
|
||||
|
||||
extern bool mp_should_keep_irq(struct device *dev);
|
||||
|
||||
#else /* !CONFIG_X86_IO_APIC */
|
||||
|
||||
#define io_apic_assign_pci_irqs 0
|
||||
|
|
|
|||
|
|
@ -131,8 +131,13 @@ static inline int pte_exec(pte_t pte)
|
|||
|
||||
static inline int pte_special(pte_t pte)
|
||||
{
|
||||
return (pte_flags(pte) & (_PAGE_PRESENT|_PAGE_SPECIAL)) ==
|
||||
(_PAGE_PRESENT|_PAGE_SPECIAL);
|
||||
/*
|
||||
* See CONFIG_NUMA_BALANCING pte_numa in include/asm-generic/pgtable.h.
|
||||
* On x86 we have _PAGE_BIT_NUMA == _PAGE_BIT_GLOBAL+1 ==
|
||||
* __PAGE_BIT_SOFTW1 == _PAGE_BIT_SPECIAL.
|
||||
*/
|
||||
return (pte_flags(pte) & _PAGE_SPECIAL) &&
|
||||
(pte_flags(pte) & (_PAGE_PRESENT|_PAGE_PROTNONE));
|
||||
}
|
||||
|
||||
static inline unsigned long pte_pfn(pte_t pte)
|
||||
|
|
|
|||
|
|
@ -71,6 +71,7 @@ obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
|
|||
obj-$(CONFIG_X86_TSC) += trace_clock.o
|
||||
obj-$(CONFIG_KEXEC) += machine_kexec_$(BITS).o
|
||||
obj-$(CONFIG_KEXEC) += relocate_kernel_$(BITS).o crash.o
|
||||
obj-$(CONFIG_KEXEC_FILE) += kexec-bzimage64.o
|
||||
obj-$(CONFIG_CRASH_DUMP) += crash_dump_$(BITS).o
|
||||
obj-y += kprobes/
|
||||
obj-$(CONFIG_MODULES) += module.o
|
||||
|
|
@ -118,5 +119,4 @@ ifeq ($(CONFIG_X86_64),y)
|
|||
|
||||
obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o
|
||||
obj-y += vsmp_64.o
|
||||
obj-$(CONFIG_KEXEC) += kexec-bzimage64.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1070,6 +1070,11 @@ static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
|
|||
}
|
||||
|
||||
if (flags & IOAPIC_MAP_ALLOC) {
|
||||
/* special handling for legacy IRQs */
|
||||
if (irq < nr_legacy_irqs() && info->count == 1 &&
|
||||
mp_irqdomain_map(domain, irq, pin) != 0)
|
||||
irq = -1;
|
||||
|
||||
if (irq > 0)
|
||||
info->count++;
|
||||
else if (info->count == 0)
|
||||
|
|
@ -3896,7 +3901,15 @@ int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
|
|||
info->polarity = 1;
|
||||
}
|
||||
info->node = NUMA_NO_NODE;
|
||||
info->set = 1;
|
||||
|
||||
/*
|
||||
* setup_IO_APIC_irqs() programs all legacy IRQs with default
|
||||
* trigger and polarity attributes. Don't set the flag for that
|
||||
* case so the first legacy IRQ user could reprogram the pin
|
||||
* with real trigger and polarity attributes.
|
||||
*/
|
||||
if (virq >= nr_legacy_irqs() || info->count)
|
||||
info->set = 1;
|
||||
}
|
||||
set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger,
|
||||
info->polarity);
|
||||
|
|
@ -3946,6 +3959,18 @@ int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node)
|
|||
return ret;
|
||||
}
|
||||
|
||||
bool mp_should_keep_irq(struct device *dev)
|
||||
{
|
||||
if (dev->power.is_prepared)
|
||||
return true;
|
||||
#ifdef CONFIG_PM_RUNTIME
|
||||
if (dev->power.runtime_status == RPM_SUSPENDING)
|
||||
return true;
|
||||
#endif
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Enable IOAPIC early just for system timer */
|
||||
void __init pre_init_apic_IRQ0(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -182,8 +182,7 @@ void native_machine_crash_shutdown(struct pt_regs *regs)
|
|||
crash_save_cpu(regs, safe_smp_processor_id());
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
|
||||
#ifdef CONFIG_KEXEC_FILE
|
||||
static int get_nr_ram_ranges_callback(unsigned long start_pfn,
|
||||
unsigned long nr_pfn, void *arg)
|
||||
{
|
||||
|
|
@ -696,5 +695,4 @@ int crash_load_segments(struct kimage *image)
|
|||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_X86_64 */
|
||||
#endif /* CONFIG_KEXEC_FILE */
|
||||
|
|
|
|||
|
|
@ -203,7 +203,7 @@ void __init native_init_IRQ(void)
|
|||
set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]);
|
||||
}
|
||||
|
||||
if (!acpi_ioapic && !of_ioapic)
|
||||
if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
|
||||
setup_irq(2, &irq2);
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
|
|
|
|||
|
|
@ -25,9 +25,11 @@
|
|||
#include <asm/debugreg.h>
|
||||
#include <asm/kexec-bzimage64.h>
|
||||
|
||||
#ifdef CONFIG_KEXEC_FILE
|
||||
static struct kexec_file_ops *kexec_file_loaders[] = {
|
||||
&kexec_bzImage64_ops,
|
||||
};
|
||||
#endif
|
||||
|
||||
static void free_transition_pgtable(struct kimage *image)
|
||||
{
|
||||
|
|
@ -178,6 +180,7 @@ static void load_segments(void)
|
|||
);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_KEXEC_FILE
|
||||
/* Update purgatory as needed after various image segments have been prepared */
|
||||
static int arch_update_purgatory(struct kimage *image)
|
||||
{
|
||||
|
|
@ -209,6 +212,12 @@ static int arch_update_purgatory(struct kimage *image)
|
|||
|
||||
return ret;
|
||||
}
|
||||
#else /* !CONFIG_KEXEC_FILE */
|
||||
static inline int arch_update_purgatory(struct kimage *image)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_KEXEC_FILE */
|
||||
|
||||
int machine_kexec_prepare(struct kimage *image)
|
||||
{
|
||||
|
|
@ -329,6 +338,7 @@ void arch_crash_save_vmcoreinfo(void)
|
|||
|
||||
/* arch-dependent functionality related to kexec file-based syscall */
|
||||
|
||||
#ifdef CONFIG_KEXEC_FILE
|
||||
int arch_kexec_kernel_image_probe(struct kimage *image, void *buf,
|
||||
unsigned long buf_len)
|
||||
{
|
||||
|
|
@ -522,3 +532,4 @@ int arch_kexec_apply_relocations_add(const Elf64_Ehdr *ehdr,
|
|||
(int)ELF64_R_TYPE(rel[i].r_info), value);
|
||||
return -ENOEXEC;
|
||||
}
|
||||
#endif /* CONFIG_KEXEC_FILE */
|
||||
|
|
|
|||
|
|
@ -68,6 +68,8 @@ static struct irqaction irq0 = {
|
|||
|
||||
void __init setup_default_timer_irq(void)
|
||||
{
|
||||
if (!nr_legacy_irqs())
|
||||
return;
|
||||
setup_irq(0, &irq0);
|
||||
}
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue