mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-04 16:15:11 +00:00
Merge branch 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'for-2.6.25' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (454 commits) [POWERPC] Cell IOMMU fixed mapping support [POWERPC] Split out the ioid fetching/checking logic [POWERPC] Add support to cell_iommu_setup_page_tables() for multiple windows [POWERPC] Split out the IOMMU logic from cell_dma_dev_setup() [POWERPC] Split cell_iommu_setup_hardware() into two parts [POWERPC] Split out the logic that allocates struct iommus [POWERPC] Allocate the hash table under 1G on cell [POWERPC] Add set_dma_ops() to match get_dma_ops() [POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format. [POWERPC] 85xx: Only invalidate TLB0 and TLB1 [POWERPC] 83xx: Fix typo in mpc837x compatible entries [POWERPC] 85xx: convert sbc85* boards to use machine_device_initcall [POWERPC] 83xx: rework platform Kconfig [POWERPC] 85xx: rework platform Kconfig [POWERPC] 86xx: Remove unused IRQ defines [POWERPC] QE: Explicitly set address-cells and size cells for muram [POWERPC] Convert StorCenter DTS file to /dts-v1/ format. [POWERPC] 86xx: Convert all 86xx DTS files to /dts-v1/ format. [PPC] Remove 85xx from arch/ppc [PPC] Remove 83xx from arch/ppc ...
This commit is contained in:
Linus Torvalds
commit
8af03e782c
612 changed files with 59681 additions and 24382 deletions
|
|
@ -717,6 +717,7 @@ and is between 256 and 4096 characters. It is defined in the file
|
|||
See Documentation/isdn/README.HiSax.
|
||||
|
||||
hugepages= [HW,X86-32,IA-64] Maximal number of HugeTLB pages.
|
||||
hugepagesz= [HW,IA-64,PPC] The size of the HugeTLB pages.
|
||||
|
||||
i8042.direct [HW] Put keyboard port into non-translated mode
|
||||
i8042.dumbkbd [HW] Pretend that controller can only read data from
|
||||
|
|
|
|||
|
|
@ -28,3 +28,6 @@ sound.txt
|
|||
- info on sound support under Linux/PPC
|
||||
zImage_layout.txt
|
||||
- info on the kernel images for Linux/PPC
|
||||
qe_firmware.txt
|
||||
- describes the layout of firmware binaries for the Freescale QUICC
|
||||
Engine and the code that parses and uploads the microcode therein.
|
||||
|
|
|
|||
|
|
@ -52,7 +52,11 @@ Table of Contents
|
|||
i) Freescale QUICC Engine module (QE)
|
||||
j) CFI or JEDEC memory-mapped NOR flash
|
||||
k) Global Utilities Block
|
||||
l) Xilinx IP cores
|
||||
l) Freescale Communications Processor Module
|
||||
m) Chipselect/Local Bus
|
||||
n) 4xx/Axon EMAC ethernet nodes
|
||||
o) Xilinx IP cores
|
||||
p) Freescale Synchronous Serial Interface
|
||||
|
||||
VII - Specifying interrupt information for devices
|
||||
1) interrupts property
|
||||
|
|
@ -671,10 +675,10 @@ device or bus to be described by the device tree.
|
|||
|
||||
In general, the format of an address for a device is defined by the
|
||||
parent bus type, based on the #address-cells and #size-cells
|
||||
property. In the absence of such a property, the parent's parent
|
||||
values are used, etc... The kernel requires the root node to have
|
||||
those properties defining addresses format for devices directly mapped
|
||||
on the processor bus.
|
||||
properties. Note that the parent's parent definitions of #address-cells
|
||||
and #size-cells are not inhereted so every node with children must specify
|
||||
them. The kernel requires the root node to have those properties defining
|
||||
addresses format for devices directly mapped on the processor bus.
|
||||
|
||||
Those 2 properties define 'cells' for representing an address and a
|
||||
size. A "cell" is a 32-bit number. For example, if both contain 2
|
||||
|
|
@ -711,13 +715,14 @@ define a bus type with a more complex address format, including things
|
|||
like address space bits, you'll have to add a bus translator to the
|
||||
prom_parse.c file of the recent kernels for your bus type.
|
||||
|
||||
The "reg" property only defines addresses and sizes (if #size-cells
|
||||
is non-0) within a given bus. In order to translate addresses upward
|
||||
The "reg" property only defines addresses and sizes (if #size-cells is
|
||||
non-0) within a given bus. In order to translate addresses upward
|
||||
(that is into parent bus addresses, and possibly into CPU physical
|
||||
addresses), all busses must contain a "ranges" property. If the
|
||||
"ranges" property is missing at a given level, it's assumed that
|
||||
translation isn't possible. The format of the "ranges" property for a
|
||||
bus is a list of:
|
||||
translation isn't possible, i.e., the registers are not visible on the
|
||||
parent bus. The format of the "ranges" property for a bus is a list
|
||||
of:
|
||||
|
||||
bus address, parent bus address, size
|
||||
|
||||
|
|
@ -735,6 +740,10 @@ fit in a single 32-bit word. New 32-bit powerpc boards should use a
|
|||
1/1 format, unless the processor supports physical addresses greater
|
||||
than 32-bits, in which case a 2/1 format is recommended.
|
||||
|
||||
Alternatively, the "ranges" property may be empty, indicating that the
|
||||
registers are visible on the parent bus using an identity mapping
|
||||
translation. In other words, the parent bus address space is the same
|
||||
as the child bus address space.
|
||||
|
||||
2) Note about "compatible" properties
|
||||
-------------------------------------
|
||||
|
|
@ -1218,16 +1227,14 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
Required properties:
|
||||
- reg : Offset and length of the register set for the device
|
||||
- device_type : Should be "mdio"
|
||||
- compatible : Should define the compatible device type for the
|
||||
mdio. Currently, this is most likely to be "gianfar"
|
||||
mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
|
||||
|
||||
Example:
|
||||
|
||||
mdio@24520 {
|
||||
reg = <24520 20>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
|
||||
ethernet-phy@0 {
|
||||
......
|
||||
|
|
@ -1254,6 +1261,10 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
services interrupts for this device.
|
||||
- phy-handle : The phandle for the PHY connected to this ethernet
|
||||
controller.
|
||||
- fixed-link : <a b c d e> where a is emulated phy id - choose any,
|
||||
but unique to the all specified fixed-links, b is duplex - 0 half,
|
||||
1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
|
||||
pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
|
||||
|
||||
Recommended properties:
|
||||
|
||||
|
|
@ -1408,7 +1419,6 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
Example multi port host USB controller device node :
|
||||
usb@22000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <22000 1000>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1422,7 +1432,6 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
Example dual role USB controller device node :
|
||||
usb@23000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <23000 1000>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1534,7 +1543,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
i) Root QE device
|
||||
|
||||
Required properties:
|
||||
- device_type : should be "qe";
|
||||
- compatible : should be "fsl,qe";
|
||||
- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
|
||||
- reg : offset and length of the device registers.
|
||||
- bus-frequency : the clock frequency for QUICC Engine.
|
||||
|
|
@ -1548,8 +1557,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "qe";
|
||||
model = "QE";
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0 e0100000 00100000>;
|
||||
reg = <e0100000 480>;
|
||||
brg-frequency = <0>;
|
||||
|
|
@ -1560,8 +1568,8 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
ii) SPI (Serial Peripheral Interface)
|
||||
|
||||
Required properties:
|
||||
- device_type : should be "spi".
|
||||
- compatible : should be "fsl_spi".
|
||||
- cell-index : SPI controller index.
|
||||
- compatible : should be "fsl,spi".
|
||||
- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
|
|
@ -1574,8 +1582,8 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
Example:
|
||||
spi@4c0 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <4c0 40>;
|
||||
interrupts = <82 0>;
|
||||
interrupt-parent = <700>;
|
||||
|
|
@ -1586,7 +1594,6 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
iii) USB (Universal Serial Bus Controller)
|
||||
|
||||
Required properties:
|
||||
- device_type : should be "usb".
|
||||
- compatible : could be "qe_udc" or "fhci-hcd".
|
||||
- mode : the could be "host" or "slave".
|
||||
- reg : Offset and length of the register set for the device
|
||||
|
|
@ -1600,7 +1607,6 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
Example(slave):
|
||||
usb@6c0 {
|
||||
device_type = "usb";
|
||||
compatible = "qe_udc";
|
||||
reg = <6c0 40>;
|
||||
interrupts = <8b 0>;
|
||||
|
|
@ -1613,7 +1619,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
Required properties:
|
||||
- device_type : should be "network", "hldc", "uart", "transparent"
|
||||
"bisync" or "atm".
|
||||
"bisync", "atm", or "serial".
|
||||
- compatible : could be "ucc_geth" or "fsl_atm" and so on.
|
||||
- model : should be "UCC".
|
||||
- device-id : the ucc number(1-8), corresponding to UCCx in UM.
|
||||
|
|
@ -1626,6 +1632,26 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- pio-handle : The phandle for the Parallel I/O port configuration.
|
||||
- port-number : for UART drivers, the port number to use, between 0 and 3.
|
||||
This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
|
||||
The port number is added to the minor number of the device. Unlike the
|
||||
CPM UART driver, the port-number is required for the QE UART driver.
|
||||
- soft-uart : for UART drivers, if specified this means the QE UART device
|
||||
driver should use "Soft-UART" mode, which is needed on some SOCs that have
|
||||
broken UART hardware. Soft-UART is provided via a microcode upload.
|
||||
- rx-clock-name: the UCC receive clock source
|
||||
"none": clock source is disabled
|
||||
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
||||
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
||||
- tx-clock-name: the UCC transmit clock source
|
||||
"none": clock source is disabled
|
||||
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
||||
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
||||
The following two properties are deprecated. rx-clock has been replaced
|
||||
with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
|
||||
Drivers that currently use the deprecated properties should continue to
|
||||
do so, in order to support older device trees, but they should be updated
|
||||
to check for the new properties first.
|
||||
- rx-clock : represents the UCC receive clock source.
|
||||
0x00 : clock source is disabled;
|
||||
0x1~0x10 : clock source is BRG1~BRG16 respectively;
|
||||
|
|
@ -1754,7 +1780,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
vii) Multi-User RAM (MURAM)
|
||||
|
||||
Required properties:
|
||||
- device_type : should be "muram".
|
||||
- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
|
||||
- mode : the could be "host" or "slave".
|
||||
- ranges : Should be defined as specified in 1) to describe the
|
||||
translation of MURAM addresses.
|
||||
|
|
@ -1764,14 +1790,42 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
Example:
|
||||
|
||||
muram@10000 {
|
||||
device_type = "muram";
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0 00010000 0000c000>;
|
||||
|
||||
data-only@0{
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0 c000>;
|
||||
};
|
||||
};
|
||||
|
||||
viii) Uploaded QE firmware
|
||||
|
||||
If a new firwmare has been uploaded to the QE (usually by the
|
||||
boot loader), then a 'firmware' child node should be added to the QE
|
||||
node. This node provides information on the uploaded firmware that
|
||||
device drivers may need.
|
||||
|
||||
Required properties:
|
||||
- id: The string name of the firmware. This is taken from the 'id'
|
||||
member of the qe_firmware structure of the uploaded firmware.
|
||||
Device drivers can search this string to determine if the
|
||||
firmware they want is already present.
|
||||
- extended-modes: The Extended Modes bitfield, taken from the
|
||||
firmware binary. It is a 64-bit number represented
|
||||
as an array of two 32-bit numbers.
|
||||
- virtual-traps: The virtual traps, taken from the firmware binary.
|
||||
It is an array of 8 32-bit numbers.
|
||||
|
||||
Example:
|
||||
|
||||
firmware {
|
||||
id = "Soft-UART";
|
||||
extended-modes = <0 0>;
|
||||
virtual-traps = <0 0 0 0 0 0 0 0>;
|
||||
}
|
||||
|
||||
j) CFI or JEDEC memory-mapped NOR flash
|
||||
|
||||
Flash chips (Memory Technology Devices) are often used for solid state
|
||||
|
|
@ -2075,8 +2129,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
Example:
|
||||
localbus@f0010100 {
|
||||
compatible = "fsl,mpc8272ads-localbus",
|
||||
"fsl,mpc8272-localbus",
|
||||
compatible = "fsl,mpc8272-localbus",
|
||||
"fsl,pq2-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -2254,7 +2307,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
available.
|
||||
For Axon: 0x0000012a
|
||||
|
||||
l) Xilinx IP cores
|
||||
o) Xilinx IP cores
|
||||
|
||||
The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
|
||||
in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
|
||||
|
|
@ -2276,7 +2329,7 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
properties of the device node. In general, device nodes for IP-cores
|
||||
will take the following form:
|
||||
|
||||
(name)@(base-address) {
|
||||
(name): (generic-name)@(base-address) {
|
||||
compatible = "xlnx,(ip-core-name)-(HW_VER)"
|
||||
[, (list of compatible devices), ...];
|
||||
reg = <(baseaddr) (size)>;
|
||||
|
|
@ -2286,6 +2339,9 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
xlnx,(parameter2) = <(int-value)>;
|
||||
};
|
||||
|
||||
(generic-name): an open firmware-style name that describes the
|
||||
generic class of device. Preferably, this is one word, such
|
||||
as 'serial' or 'ethernet'.
|
||||
(ip-core-name): the name of the ip block (given after the BEGIN
|
||||
directive in system.mhs). Should be in lowercase
|
||||
and all underscores '_' converted to dashes '-'.
|
||||
|
|
@ -2294,9 +2350,9 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
dropped from the parameter name, the name is converted
|
||||
to lowercase and all underscore '_' characters are
|
||||
converted to dashes '-'.
|
||||
(baseaddr): the C_BASEADDR parameter.
|
||||
(baseaddr): the baseaddr parameter value (often named C_BASEADDR).
|
||||
(HW_VER): from the HW_VER parameter.
|
||||
(size): equals C_HIGHADDR - C_BASEADDR + 1
|
||||
(size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
|
||||
|
||||
Typically, the compatible list will include the exact IP core version
|
||||
followed by an older IP core version which implements the same
|
||||
|
|
@ -2326,11 +2382,11 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
becomes the following device tree node:
|
||||
|
||||
opb-uartlite-0@ec100000 {
|
||||
opb_uartlite_0: serial@ec100000 {
|
||||
device_type = "serial";
|
||||
compatible = "xlnx,opb-uartlite-1.00.b";
|
||||
reg = <ec100000 10000>;
|
||||
interrupt-parent = <&opb-intc>;
|
||||
interrupt-parent = <&opb_intc_0>;
|
||||
interrupts = <1 0>; // got this from the opb_intc parameters
|
||||
current-speed = <d#115200>; // standard serial device prop
|
||||
clock-frequency = <d#50000000>; // standard serial device prop
|
||||
|
|
@ -2339,16 +2395,19 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
xlnx,use-parity = <0>;
|
||||
};
|
||||
|
||||
Some IP cores actually implement 2 or more logical devices. In this case,
|
||||
the device should still describe the whole IP core with a single node
|
||||
and add a child node for each logical device. The ranges property can
|
||||
be used to translate from parent IP-core to the registers of each device.
|
||||
(Note: this makes the assumption that both logical devices have the same
|
||||
bus binding. If this is not true, then separate nodes should be used for
|
||||
each logical device). The 'cell-index' property can be used to enumerate
|
||||
logical devices within an IP core. For example, the following is the
|
||||
system.mhs entry for the dual ps2 controller found on the ml403 reference
|
||||
design.
|
||||
Some IP cores actually implement 2 or more logical devices. In
|
||||
this case, the device should still describe the whole IP core with
|
||||
a single node and add a child node for each logical device. The
|
||||
ranges property can be used to translate from parent IP-core to the
|
||||
registers of each device. In addition, the parent node should be
|
||||
compatible with the bus type 'xlnx,compound', and should contain
|
||||
#address-cells and #size-cells, as with any other bus. (Note: this
|
||||
makes the assumption that both logical devices have the same bus
|
||||
binding. If this is not true, then separate nodes should be used
|
||||
for each logical device). The 'cell-index' property can be used to
|
||||
enumerate logical devices within an IP core. For example, the
|
||||
following is the system.mhs entry for the dual ps2 controller found
|
||||
on the ml403 reference design.
|
||||
|
||||
BEGIN opb_ps2_dual_ref
|
||||
PARAMETER INSTANCE = opb_ps2_dual_ref_0
|
||||
|
|
@ -2370,21 +2429,24 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
It would result in the following device tree nodes:
|
||||
|
||||
opb_ps2_dual_ref_0@a9000000 {
|
||||
opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,compound";
|
||||
ranges = <0 a9000000 2000>;
|
||||
// If this device had extra parameters, then they would
|
||||
// go here.
|
||||
ps2@0 {
|
||||
compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
|
||||
reg = <0 40>;
|
||||
interrupt-parent = <&opb-intc>;
|
||||
interrupt-parent = <&opb_intc_0>;
|
||||
interrupts = <3 0>;
|
||||
cell-index = <0>;
|
||||
};
|
||||
ps2@1000 {
|
||||
compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
|
||||
reg = <1000 40>;
|
||||
interrupt-parent = <&opb-intc>;
|
||||
interrupt-parent = <&opb_intc_0>;
|
||||
interrupts = <3 0>;
|
||||
cell-index = <0>;
|
||||
};
|
||||
|
|
@ -2447,17 +2509,18 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
|
||||
Gives this device tree (some properties removed for clarity):
|
||||
|
||||
plb-v34-0 {
|
||||
plb@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "xlnx,plb-v34-1.02.a";
|
||||
device_type = "ibm,plb";
|
||||
ranges; // 1:1 translation
|
||||
|
||||
plb-bram-if-cntrl-0@ffff0000 {
|
||||
plb_bram_if_cntrl_0: bram@ffff0000 {
|
||||
reg = <ffff0000 10000>;
|
||||
}
|
||||
|
||||
opb-v20-0 {
|
||||
opb@20000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <20000000 20000000 20000000
|
||||
|
|
@ -2465,11 +2528,11 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
80000000 80000000 40000000
|
||||
c0000000 c0000000 20000000>;
|
||||
|
||||
opb-uart16550-0@a0000000 {
|
||||
opb_uart16550_0: serial@a0000000 {
|
||||
reg = <a00000000 2000>;
|
||||
};
|
||||
|
||||
opb-intc-0@d1000fc0 {
|
||||
opb_intc_0: interrupt-controller@d1000fc0 {
|
||||
reg = <d1000fc0 20>;
|
||||
};
|
||||
};
|
||||
|
|
@ -2514,6 +2577,204 @@ platforms are moved over to use the flattened-device-tree model.
|
|||
Requred properties:
|
||||
- current-speed : Baud rate of uartlite
|
||||
|
||||
p) Freescale Synchronous Serial Interface
|
||||
|
||||
The SSI is a serial device that communicates with audio codecs. It can
|
||||
be programmed in AC97, I2S, left-justified, or right-justified modes.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, containing "fsl,ssi"
|
||||
- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
|
||||
- reg : offset and length of the register set for the device
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and
|
||||
level information for the interrupt. This should be
|
||||
encoded based on the information in section 2)
|
||||
depending on the type of interrupt controller you
|
||||
have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- fsl,mode : the operating mode for the SSI interface
|
||||
"i2s-slave" - I2S mode, SSI is clock slave
|
||||
"i2s-master" - I2S mode, SSI is clock master
|
||||
"lj-slave" - left-justified mode, SSI is clock slave
|
||||
"lj-master" - l.j. mode, SSI is clock master
|
||||
"rj-slave" - right-justified mode, SSI is clock slave
|
||||
"rj-master" - r.j., SSI is clock master
|
||||
"ac97-slave" - AC97 mode, SSI is clock slave
|
||||
"ac97-master" - AC97 mode, SSI is clock master
|
||||
|
||||
Optional properties:
|
||||
- codec-handle : phandle to a 'codec' node that defines an audio
|
||||
codec connected to this SSI. This node is typically
|
||||
a child of an I2C or other control node.
|
||||
|
||||
Child 'codec' node required properties:
|
||||
- compatible : compatible list, contains the name of the codec
|
||||
|
||||
Child 'codec' node optional properties:
|
||||
- clock-frequency : The frequency of the input clock, which typically
|
||||
comes from an on-board dedicated oscillator.
|
||||
|
||||
* Freescale 83xx DMA Controller
|
||||
|
||||
Freescale PowerPC 83xx have on chip general purpose DMA controllers.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-dma", where CHIP is the processor
|
||||
(mpc8349, mpc8360, etc.) and the second is
|
||||
"fsl,elo-dma"
|
||||
- reg : <registers mapping for DMA general status reg>
|
||||
- ranges : Should be defined as specified in 1) to describe the
|
||||
DMA controller channels.
|
||||
- cell-index : controller index. 0 for controller @ 0x8100
|
||||
- interrupts : <interrupt mapping for DMA IRQ>
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
|
||||
|
||||
- DMA channel nodes:
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-dma-channel", where CHIP is the processor
|
||||
(mpc8349, mpc8350, etc.) and the second is
|
||||
"fsl,elo-dma-channel"
|
||||
- reg : <registers mapping for channel>
|
||||
- cell-index : dma channel index starts at 0.
|
||||
|
||||
Optional properties:
|
||||
- interrupts : <interrupt mapping for DMA channel IRQ>
|
||||
(on 83xx this is expected to be identical to
|
||||
the interrupts property of the parent node)
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
|
||||
Example:
|
||||
dma@82a8 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
|
||||
reg = <82a8 4>;
|
||||
ranges = <0 8100 1a4>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <47 8>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
cell-index = <0>;
|
||||
reg = <0 80>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
cell-index = <1>;
|
||||
reg = <80 80>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
cell-index = <2>;
|
||||
reg = <100 80>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
|
||||
cell-index = <3>;
|
||||
reg = <180 80>;
|
||||
};
|
||||
};
|
||||
|
||||
* Freescale 85xx/86xx DMA Controller
|
||||
|
||||
Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-dma", where CHIP is the processor
|
||||
(mpc8540, mpc8540, etc.) and the second is
|
||||
"fsl,eloplus-dma"
|
||||
- reg : <registers mapping for DMA general status reg>
|
||||
- cell-index : controller index. 0 for controller @ 0x21000,
|
||||
1 for controller @ 0xc000
|
||||
- ranges : Should be defined as specified in 1) to describe the
|
||||
DMA controller channels.
|
||||
|
||||
- DMA channel nodes:
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-dma-channel", where CHIP is the processor
|
||||
(mpc8540, mpc8560, etc.) and the second is
|
||||
"fsl,eloplus-dma-channel"
|
||||
- cell-index : dma channel index starts at 0.
|
||||
- reg : <registers mapping for channel>
|
||||
- interrupts : <interrupt mapping for DMA channel IRQ>
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
|
||||
Example:
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
|
||||
reg = <21300 4>;
|
||||
ranges = <0 21100 200>;
|
||||
cell-index = <0>;
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <0 80>;
|
||||
cell-index = <0>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <14 2>;
|
||||
};
|
||||
dma-channel@80 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <80 80>;
|
||||
cell-index = <1>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <15 2>;
|
||||
};
|
||||
dma-channel@100 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <100 80>;
|
||||
cell-index = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
dma-channel@180 {
|
||||
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
|
||||
reg = <180 80>;
|
||||
cell-index = <3>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <17 2>;
|
||||
};
|
||||
};
|
||||
|
||||
* Freescale 8xxx/3.0 Gb/s SATA nodes
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA port should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains 2 entries, first is
|
||||
"fsl,CHIP-sata", where CHIP is the processor
|
||||
(mpc8315, mpc8379, etc.) and the second is
|
||||
"fsl,pq-sata"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- cell-index : controller index.
|
||||
1 for controller @ 0x18000
|
||||
2 for controller @ 0x19000
|
||||
3 for controller @ 0x1a000
|
||||
4 for controller @ 0x1b000
|
||||
|
||||
Optional properties:
|
||||
- interrupt-parent : optional, if needed for interrupt mapping
|
||||
- reg : <registers mapping>
|
||||
|
||||
Example:
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
cell-index = <1>;
|
||||
interrupts = <2c 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
More devices will be defined as this spec matures.
|
||||
|
||||
VII - Specifying interrupt information for devices
|
||||
|
|
|
|||
295
Documentation/powerpc/qe_firmware.txt
Normal file
295
Documentation/powerpc/qe_firmware.txt
Normal file
|
|
@ -0,0 +1,295 @@
|
|||
Freescale QUICC Engine Firmware Uploading
|
||||
-----------------------------------------
|
||||
|
||||
(c) 2007 Timur Tabi <timur at freescale.com>,
|
||||
Freescale Semiconductor
|
||||
|
||||
Table of Contents
|
||||
=================
|
||||
|
||||
I - Software License for Firmware
|
||||
|
||||
II - Microcode Availability
|
||||
|
||||
III - Description and Terminology
|
||||
|
||||
IV - Microcode Programming Details
|
||||
|
||||
V - Firmware Structure Layout
|
||||
|
||||
VI - Sample Code for Creating Firmware Files
|
||||
|
||||
Revision Information
|
||||
====================
|
||||
|
||||
November 30, 2007: Rev 1.0 - Initial version
|
||||
|
||||
I - Software License for Firmware
|
||||
=================================
|
||||
|
||||
Each firmware file comes with its own software license. For information on
|
||||
the particular license, please see the license text that is distributed with
|
||||
the firmware.
|
||||
|
||||
II - Microcode Availability
|
||||
===========================
|
||||
|
||||
Firmware files are distributed through various channels. Some are available on
|
||||
http://opensource.freescale.com. For other firmware files, please contact
|
||||
your Freescale representative or your operating system vendor.
|
||||
|
||||
III - Description and Terminology
|
||||
================================
|
||||
|
||||
In this document, the term 'microcode' refers to the sequence of 32-bit
|
||||
integers that compose the actual QE microcode.
|
||||
|
||||
The term 'firmware' refers to a binary blob that contains the microcode as
|
||||
well as other data that
|
||||
|
||||
1) describes the microcode's purpose
|
||||
2) describes how and where to upload the microcode
|
||||
3) specifies the values of various registers
|
||||
4) includes additional data for use by specific device drivers
|
||||
|
||||
Firmware files are binary files that contain only a firmware.
|
||||
|
||||
IV - Microcode Programming Details
|
||||
===================================
|
||||
|
||||
The QE architecture allows for only one microcode present in I-RAM for each
|
||||
RISC processor. To replace any current microcode, a full QE reset (which
|
||||
disables the microcode) must be performed first.
|
||||
|
||||
QE microcode is uploaded using the following procedure:
|
||||
|
||||
1) The microcode is placed into I-RAM at a specific location, using the
|
||||
IRAM.IADD and IRAM.IDATA registers.
|
||||
|
||||
2) The CERCR.CIR bit is set to 0 or 1, depending on whether the firmware
|
||||
needs split I-RAM. Split I-RAM is only meaningful for SOCs that have
|
||||
QEs with multiple RISC processors, such as the 8360. Splitting the I-RAM
|
||||
allows each processor to run a different microcode, effectively creating an
|
||||
asymmetric multiprocessing (AMP) system.
|
||||
|
||||
3) The TIBCR trap registers are loaded with the addresses of the trap handlers
|
||||
in the microcode.
|
||||
|
||||
4) The RSP.ECCR register is programmed with the value provided.
|
||||
|
||||
5) If necessary, device drivers that need the virtual traps and extended mode
|
||||
data will use them.
|
||||
|
||||
Virtual Microcode Traps
|
||||
|
||||
These virtual traps are conditional branches in the microcode. These are
|
||||
"soft" provisional introduced in the ROMcode in order to enable higher
|
||||
flexibility and save h/w traps If new features are activated or an issue is
|
||||
being fixed in the RAM package utilizing they should be activated. This data
|
||||
structure signals the microcode which of these virtual traps is active.
|
||||
|
||||
This structure contains 6 words that the application should copy to some
|
||||
specific been defined. This table describes the structure.
|
||||
|
||||
---------------------------------------------------------------
|
||||
| Offset in | | Destination Offset | Size of |
|
||||
| array | Protocol | within PRAM | Operand |
|
||||
--------------------------------------------------------------|
|
||||
| 0 | Ethernet | 0xF8 | 4 bytes |
|
||||
| | interworking | | |
|
||||
---------------------------------------------------------------
|
||||
| 4 | ATM | 0xF8 | 4 bytes |
|
||||
| | interworking | | |
|
||||
---------------------------------------------------------------
|
||||
| 8 | PPP | 0xF8 | 4 bytes |
|
||||
| | interworking | | |
|
||||
---------------------------------------------------------------
|
||||
| 12 | Ethernet RX | 0x22 | 1 byte |
|
||||
| | Distributor Page | | |
|
||||
---------------------------------------------------------------
|
||||
| 16 | ATM Globtal | 0x28 | 1 byte |
|
||||
| | Params Table | | |
|
||||
---------------------------------------------------------------
|
||||
| 20 | Insert Frame | 0xF8 | 4 bytes |
|
||||
---------------------------------------------------------------
|
||||
|
||||
|
||||
Extended Modes
|
||||
|
||||
This is a double word bit array (64 bits) that defines special functionality
|
||||
which has an impact on the softwarew drivers. Each bit has its own impact
|
||||
and has special instructions for the s/w associated with it. This structure is
|
||||
described in this table:
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
| Bit # | Name | Description |
|
||||
-----------------------------------------------------------------------
|
||||
| 0 | General | Indicates that prior to each host command |
|
||||
| | push command | given by the application, the software must |
|
||||
| | | assert a special host command (push command)|
|
||||
| | | CECDR = 0x00800000. |
|
||||
| | | CECR = 0x01c1000f. |
|
||||
-----------------------------------------------------------------------
|
||||
| 1 | UCC ATM | Indicates that after issuing ATM RX INIT |
|
||||
| | RX INIT | command, the host must issue another special|
|
||||
| | push command | command (push command) and immediately |
|
||||
| | | following that re-issue the ATM RX INIT |
|
||||
| | | command. (This makes the sequence of |
|
||||
| | | initializing the ATM receiver a sequence of |
|
||||
| | | three host commands) |
|
||||
| | | CECDR = 0x00800000. |
|
||||
| | | CECR = 0x01c1000f. |
|
||||
-----------------------------------------------------------------------
|
||||
| 2 | Add/remove | Indicates that following the specific host |
|
||||
| | command | command: "Add/Remove entry in Hash Lookup |
|
||||
| | validation | Table" used in Interworking setup, the user |
|
||||
| | | must issue another command. |
|
||||
| | | CECDR = 0xce000003. |
|
||||
| | | CECR = 0x01c10f58. |
|
||||
-----------------------------------------------------------------------
|
||||
| 3 | General push | Indicates that the s/w has to initialize |
|
||||
| | command | some pointers in the Ethernet thread pages |
|
||||
| | | which are used when Header Compression is |
|
||||
| | | activated. The full details of these |
|
||||
| | | pointers is located in the software drivers.|
|
||||
-----------------------------------------------------------------------
|
||||
| 4 | General push | Indicates that after issuing Ethernet TX |
|
||||
| | command | INIT command, user must issue this command |
|
||||
| | | for each SNUM of Ethernet TX thread. |
|
||||
| | | CECDR = 0x00800003. |
|
||||
| | | CECR = 0x7'b{0}, 8'b{Enet TX thread SNUM}, |
|
||||
| | | 1'b{1}, 12'b{0}, 4'b{1} |
|
||||
-----------------------------------------------------------------------
|
||||
| 5 - 31 | N/A | Reserved, set to zero. |
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
V - Firmware Structure Layout
|
||||
==============================
|
||||
|
||||
QE microcode from Freescale is typically provided as a header file. This
|
||||
header file contains macros that define the microcode binary itself as well as
|
||||
some other data used in uploading that microcode. The format of these files
|
||||
do not lend themselves to simple inclusion into other code. Hence,
|
||||
the need for a more portable format. This section defines that format.
|
||||
|
||||
Instead of distributing a header file, the microcode and related data are
|
||||
embedded into a binary blob. This blob is passed to the qe_upload_firmware()
|
||||
function, which parses the blob and performs everything necessary to upload
|
||||
the microcode.
|
||||
|
||||
All integers are big-endian. See the comments for function
|
||||
qe_upload_firmware() for up-to-date implementation information.
|
||||
|
||||
This structure supports versioning, where the version of the structure is
|
||||
embedded into the structure itself. To ensure forward and backwards
|
||||
compatibility, all versions of the structure must use the same 'qe_header'
|
||||
structure at the beginning.
|
||||
|
||||
'header' (type: struct qe_header):
|
||||
The 'length' field is the size, in bytes, of the entire structure,
|
||||
including all the microcode embedded in it, as well as the CRC (if
|
||||
present).
|
||||
|
||||
The 'magic' field is an array of three bytes that contains the letters
|
||||
'Q', 'E', and 'F'. This is an identifier that indicates that this
|
||||
structure is a QE Firmware structure.
|
||||
|
||||
The 'version' field is a single byte that indicates the version of this
|
||||
structure. If the layout of the structure should ever need to be
|
||||
changed to add support for additional types of microcode, then the
|
||||
version number should also be changed.
|
||||
|
||||
The 'id' field is a null-terminated string(suitable for printing) that
|
||||
identifies the firmware.
|
||||
|
||||
The 'count' field indicates the number of 'microcode' structures. There
|
||||
must be one and only one 'microcode' structure for each RISC processor.
|
||||
Therefore, this field also represents the number of RISC processors for this
|
||||
SOC.
|
||||
|
||||
The 'soc' structure contains the SOC numbers and revisions used to match
|
||||
the microcode to the SOC itself. Normally, the microcode loader should
|
||||
check the data in this structure with the SOC number and revisions, and
|
||||
only upload the microcode if there's a match. However, this check is not
|
||||
made on all platforms.
|
||||
|
||||
Although it is not recommended, you can specify '0' in the soc.model
|
||||
field to skip matching SOCs altogether.
|
||||
|
||||
The 'model' field is a 16-bit number that matches the actual SOC. The
|
||||
'major' and 'minor' fields are the major and minor revision numbrs,
|
||||
respectively, of the SOC.
|
||||
|
||||
For example, to match the 8323, revision 1.0:
|
||||
soc.model = 8323
|
||||
soc.major = 1
|
||||
soc.minor = 0
|
||||
|
||||
'padding' is neccessary for structure alignment. This field ensures that the
|
||||
'extended_modes' field is aligned on a 64-bit boundary.
|
||||
|
||||
'extended_modes' is a bitfield that defines special functionality which has an
|
||||
impact on the device drivers. Each bit has its own impact and has special
|
||||
instructions for the driver associated with it. This field is stored in
|
||||
the QE library and available to any driver that calles qe_get_firmware_info().
|
||||
|
||||
'vtraps' is an array of 8 words that contain virtual trap values for each
|
||||
virtual traps. As with 'extended_modes', this field is stored in the QE
|
||||
library and available to any driver that calles qe_get_firmware_info().
|
||||
|
||||
'microcode' (type: struct qe_microcode):
|
||||
For each RISC processor there is one 'microcode' structure. The first
|
||||
'microcode' structure is for the first RISC, and so on.
|
||||
|
||||
The 'id' field is a null-terminated string suitable for printing that
|
||||
identifies this particular microcode.
|
||||
|
||||
'traps' is an array of 16 words that contain hardware trap values
|
||||
for each of the 16 traps. If trap[i] is 0, then this particular
|
||||
trap is to be ignored (i.e. not written to TIBCR[i]). The entire value
|
||||
is written as-is to the TIBCR[i] register, so be sure to set the EN
|
||||
and T_IBP bits if necessary.
|
||||
|
||||
'eccr' is the value to program into the ECCR register.
|
||||
|
||||
'iram_offset' is the offset into IRAM to start writing the
|
||||
microcode.
|
||||
|
||||
'count' is the number of 32-bit words in the microcode.
|
||||
|
||||
'code_offset' is the offset, in bytes, from the beginning of this
|
||||
structure where the microcode itself can be found. The first
|
||||
microcode binary should be located immediately after the 'microcode'
|
||||
array.
|
||||
|
||||
'major', 'minor', and 'revision' are the major, minor, and revision
|
||||
version numbers, respectively, of the microcode. If all values are 0,
|
||||
then these fields are ignored.
|
||||
|
||||
'reserved' is necessary for structure alignment. Since 'microcode'
|
||||
is an array, the 64-bit 'extended_modes' field needs to be aligned
|
||||
on a 64-bit boundary, and this can only happen if the size of
|
||||
'microcode' is a multiple of 8 bytes. To ensure that, we add
|
||||
'reserved'.
|
||||
|
||||
After the last microcode is a 32-bit CRC. It can be calculated using
|
||||
this algorithm:
|
||||
|
||||
u32 crc32(const u8 *p, unsigned int len)
|
||||
{
|
||||
unsigned int i;
|
||||
u32 crc = 0;
|
||||
|
||||
while (len--) {
|
||||
crc ^= *p++;
|
||||
for (i = 0; i < 8; i++)
|
||||
crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
|
||||
}
|
||||
return crc;
|
||||
}
|
||||
|
||||
VI - Sample Code for Creating Firmware Files
|
||||
============================================
|
||||
|
||||
A Python program that creates firmware binaries from the header files normally
|
||||
distributed by Freescale can be found on http://opensource.freescale.com.
|
||||
|
|
@ -148,6 +148,9 @@ config DEFAULT_UIMAGE
|
|||
Used to allow a board to specify it wants a uImage built by default
|
||||
default n
|
||||
|
||||
config REDBOOT
|
||||
bool
|
||||
|
||||
config PPC64_SWSUSP
|
||||
bool
|
||||
depends on PPC64 && (BROKEN || (PPC_PMAC64 && EXPERIMENTAL))
|
||||
|
|
@ -168,11 +171,13 @@ config PPC_DCR
|
|||
|
||||
config PPC_OF_PLATFORM_PCI
|
||||
bool
|
||||
depends on PCI
|
||||
depends on PPC64 # not supported on 32 bits yet
|
||||
default n
|
||||
|
||||
source "init/Kconfig"
|
||||
|
||||
source "arch/powerpc/sysdev/Kconfig"
|
||||
source "arch/powerpc/platforms/Kconfig"
|
||||
|
||||
menu "Kernel options"
|
||||
|
|
@ -348,6 +353,14 @@ config PPC_64K_PAGES
|
|||
while on hardware with such support, it will be used to map
|
||||
normal application pages.
|
||||
|
||||
config PPC_SUBPAGE_PROT
|
||||
bool "Support setting protections for 4k subpages"
|
||||
depends on PPC_64K_PAGES
|
||||
help
|
||||
This option adds support for a system call to allow user programs
|
||||
to set access permissions (read/write, readonly, or no access)
|
||||
on the 4k subpages of each 64k page.
|
||||
|
||||
config SCHED_SMT
|
||||
bool "SMT (Hyperthreading) scheduler support"
|
||||
depends on PPC64 && SMP
|
||||
|
|
@ -425,7 +438,7 @@ endmenu
|
|||
|
||||
config ISA_DMA_API
|
||||
bool
|
||||
default y
|
||||
default !PPC_ISERIES || PCI
|
||||
|
||||
menu "Bus options"
|
||||
|
||||
|
|
@ -475,7 +488,7 @@ config MCA
|
|||
config PCI
|
||||
bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_86xx \
|
||||
|| PPC_MPC52xx || (EMBEDDED && (PPC_PSERIES || PPC_ISERIES)) \
|
||||
|| PPC_PS3
|
||||
|| PPC_PS3 || 44x
|
||||
default y if !40x && !CPM2 && !8xx && !PPC_83xx \
|
||||
&& !PPC_85xx && !PPC_86xx
|
||||
default PCI_PERMEDIA if !4xx && !CPM2 && !8xx
|
||||
|
|
|
|||
|
|
@ -151,6 +151,13 @@ config BOOTX_TEXT
|
|||
|
||||
config PPC_EARLY_DEBUG
|
||||
bool "Early debugging (dangerous)"
|
||||
help
|
||||
Say Y to enable some early debugging facilities that may be available
|
||||
for your processor/board combination. Those facilities are hacks
|
||||
intended to debug problems early during boot, this should not be
|
||||
enabled in a production kernel.
|
||||
Note that enabling this will also cause the kernel default log level
|
||||
to be pushed to max automatically very early during boot
|
||||
|
||||
choice
|
||||
prompt "Early debugging console"
|
||||
|
|
@ -218,7 +225,16 @@ config PPC_EARLY_DEBUG_44x
|
|||
depends on 44x
|
||||
help
|
||||
Select this to enable early debugging for IBM 44x chips via the
|
||||
inbuilt serial port.
|
||||
inbuilt serial port. If you enable this, ensure you set
|
||||
PPC_EARLY_DEBUG_44x_PHYSLOW below to suit your target board.
|
||||
|
||||
config PPC_EARLY_DEBUG_40x
|
||||
bool "Early serial debugging for IBM/AMCC 40x CPUs"
|
||||
depends on 40x
|
||||
help
|
||||
Select this to enable early debugging for IBM 40x chips via the
|
||||
inbuilt serial port. This works on chips with a 16550 compatible
|
||||
UART. Xilinx chips with uartlite cannot use this option.
|
||||
|
||||
config PPC_EARLY_DEBUG_CPM
|
||||
bool "Early serial debugging for Freescale CPM-based serial ports"
|
||||
|
|
@ -235,12 +251,20 @@ config PPC_EARLY_DEBUG_44x_PHYSLOW
|
|||
hex "Low 32 bits of early debug UART physical address"
|
||||
depends on PPC_EARLY_DEBUG_44x
|
||||
default "0x40000200"
|
||||
help
|
||||
You probably want 0x40000200 for ebony boards and
|
||||
0x40000300 for taishan
|
||||
|
||||
config PPC_EARLY_DEBUG_44x_PHYSHIGH
|
||||
hex "EPRN of early debug UART physical address"
|
||||
depends on PPC_EARLY_DEBUG_44x
|
||||
default "0x1"
|
||||
|
||||
config PPC_EARLY_DEBUG_40x_PHYSADDR
|
||||
hex "Early debug UART physical address"
|
||||
depends on PPC_EARLY_DEBUG_40x
|
||||
default "0xef600300"
|
||||
|
||||
config PPC_EARLY_DEBUG_CPM_ADDR
|
||||
hex "CPM UART early debug transmit descriptor address"
|
||||
depends on PPC_EARLY_DEBUG_CPM
|
||||
|
|
|
|||
|
|
@ -167,6 +167,9 @@ boot := arch/$(ARCH)/boot
|
|||
$(BOOT_TARGETS): vmlinux
|
||||
$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
|
||||
|
||||
bootwrapper_install:
|
||||
$(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
|
||||
|
||||
define archhelp
|
||||
@echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
|
||||
@echo ' install - Install kernel using'
|
||||
|
|
|
|||
2
arch/powerpc/boot/.gitignore
vendored
2
arch/powerpc/boot/.gitignore
vendored
|
|
@ -1,4 +1,5 @@
|
|||
addnote
|
||||
dtc
|
||||
empty.c
|
||||
hack-coff
|
||||
infblock.c
|
||||
|
|
@ -30,6 +31,7 @@ zImage.*lds
|
|||
zImage.miboot
|
||||
zImage.pmac
|
||||
zImage.pseries
|
||||
zImage.redboot*
|
||||
zImage.sandpoint
|
||||
zImage.vmode
|
||||
zconf.h
|
||||
|
|
|
|||
|
|
@ -22,16 +22,14 @@
|
|||
#include "dcr.h"
|
||||
|
||||
/* Read the 4xx SDRAM controller to get size of system memory. */
|
||||
void ibm4xx_fixup_memsize(void)
|
||||
void ibm4xx_sdram_fixup_memsize(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long memsize, bank_config;
|
||||
|
||||
memsize = 0;
|
||||
for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
|
||||
mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
|
||||
bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
|
||||
|
||||
bank_config = SDRAM0_READ(sdram_bxcr[i]);
|
||||
if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
|
||||
memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
|
||||
}
|
||||
|
|
@ -39,6 +37,69 @@ void ibm4xx_fixup_memsize(void)
|
|||
dt_fixup_memory(0, memsize);
|
||||
}
|
||||
|
||||
/* Read the 440SPe MQ controller to get size of system memory. */
|
||||
#define DCRN_MQ0_B0BAS 0x40
|
||||
#define DCRN_MQ0_B1BAS 0x41
|
||||
#define DCRN_MQ0_B2BAS 0x42
|
||||
#define DCRN_MQ0_B3BAS 0x43
|
||||
|
||||
static u64 ibm440spe_decode_bas(u32 bas)
|
||||
{
|
||||
u64 base = ((u64)(bas & 0xFFE00000u)) << 2;
|
||||
|
||||
/* open coded because I'm paranoid about invalid values */
|
||||
switch ((bas >> 4) & 0xFFF) {
|
||||
case 0:
|
||||
return 0;
|
||||
case 0xffc:
|
||||
return base + 0x000800000ull;
|
||||
case 0xff8:
|
||||
return base + 0x001000000ull;
|
||||
case 0xff0:
|
||||
return base + 0x002000000ull;
|
||||
case 0xfe0:
|
||||
return base + 0x004000000ull;
|
||||
case 0xfc0:
|
||||
return base + 0x008000000ull;
|
||||
case 0xf80:
|
||||
return base + 0x010000000ull;
|
||||
case 0xf00:
|
||||
return base + 0x020000000ull;
|
||||
case 0xe00:
|
||||
return base + 0x040000000ull;
|
||||
case 0xc00:
|
||||
return base + 0x080000000ull;
|
||||
case 0x800:
|
||||
return base + 0x100000000ull;
|
||||
}
|
||||
printf("Memory BAS value 0x%08x unsupported !\n", bas);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ibm440spe_fixup_memsize(void)
|
||||
{
|
||||
u64 banktop, memsize = 0;
|
||||
|
||||
/* Ultimately, we should directly construct the memory node
|
||||
* so we are able to handle holes in the memory address space
|
||||
*/
|
||||
banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));
|
||||
if (banktop > memsize)
|
||||
memsize = banktop;
|
||||
banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));
|
||||
if (banktop > memsize)
|
||||
memsize = banktop;
|
||||
banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));
|
||||
if (banktop > memsize)
|
||||
memsize = banktop;
|
||||
banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));
|
||||
if (banktop > memsize)
|
||||
memsize = banktop;
|
||||
|
||||
dt_fixup_memory(0, memsize);
|
||||
}
|
||||
|
||||
|
||||
/* 4xx DDR1/2 Denali memory controller support */
|
||||
/* DDR0 registers */
|
||||
#define DDR0_02 2
|
||||
|
|
@ -77,19 +138,13 @@ void ibm4xx_fixup_memsize(void)
|
|||
|
||||
#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
|
||||
|
||||
static inline u32 mfdcr_sdram0(u32 reg)
|
||||
{
|
||||
mtdcr(DCRN_SDRAM0_CFGADDR, reg);
|
||||
return mfdcr(DCRN_SDRAM0_CFGDATA);
|
||||
}
|
||||
|
||||
void ibm4xx_denali_fixup_memsize(void)
|
||||
{
|
||||
u32 val, max_cs, max_col, max_row;
|
||||
u32 cs, col, row, bank, dpath;
|
||||
unsigned long memsize;
|
||||
|
||||
val = mfdcr_sdram0(DDR0_02);
|
||||
val = SDRAM0_READ(DDR0_02);
|
||||
if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
|
||||
fatal("DDR controller is not initialized\n");
|
||||
|
||||
|
|
@ -99,12 +154,12 @@ void ibm4xx_denali_fixup_memsize(void)
|
|||
max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
|
||||
|
||||
/* get CS value */
|
||||
val = mfdcr_sdram0(DDR0_10);
|
||||
val = SDRAM0_READ(DDR0_10);
|
||||
|
||||
val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
|
||||
cs = 0;
|
||||
while (val) {
|
||||
if (val && 0x1)
|
||||
if (val & 0x1)
|
||||
cs++;
|
||||
val = val >> 1;
|
||||
}
|
||||
|
|
@ -115,15 +170,15 @@ void ibm4xx_denali_fixup_memsize(void)
|
|||
fatal("DDR wrong CS configuration\n");
|
||||
|
||||
/* get data path bytes */
|
||||
val = mfdcr_sdram0(DDR0_14);
|
||||
val = SDRAM0_READ(DDR0_14);
|
||||
|
||||
if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
|
||||
dpath = 8; /* 64 bits */
|
||||
else
|
||||
dpath = 4; /* 32 bits */
|
||||
|
||||
/* get adress pins (rows) */
|
||||
val = mfdcr_sdram0(DDR0_42);
|
||||
/* get address pins (rows) */
|
||||
val = SDRAM0_READ(DDR0_42);
|
||||
|
||||
row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
|
||||
if (row > max_row)
|
||||
|
|
@ -131,7 +186,7 @@ void ibm4xx_denali_fixup_memsize(void)
|
|||
row = max_row - row;
|
||||
|
||||
/* get collomn size and banks */
|
||||
val = mfdcr_sdram0(DDR0_43);
|
||||
val = SDRAM0_READ(DDR0_43);
|
||||
|
||||
col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
|
||||
if (col > max_col)
|
||||
|
|
@ -179,13 +234,17 @@ void ibm40x_dbcr_reset(void)
|
|||
#define EMAC_RESET 0x20000000
|
||||
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
|
||||
{
|
||||
/* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */
|
||||
/* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
|
||||
* do this for us
|
||||
*/
|
||||
if (emac0)
|
||||
*emac0 = EMAC_RESET;
|
||||
if (emac1)
|
||||
*emac1 = EMAC_RESET;
|
||||
|
||||
mtdcr(DCRN_MAL0_CFG, MAL_RESET);
|
||||
while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
|
||||
; /* loop until reset takes effect */
|
||||
}
|
||||
|
||||
/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
|
||||
|
|
@ -217,84 +276,335 @@ void ibm4xx_fixup_ebc_ranges(const char *ebc)
|
|||
setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
|
||||
}
|
||||
|
||||
#define SPRN_CCR1 0x378
|
||||
void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
|
||||
/* Calculate 440GP clocks */
|
||||
void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
|
||||
{
|
||||
u32 cpu, plb, opb, ebc, tb, uart0, m, vco;
|
||||
u32 reg;
|
||||
u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp;
|
||||
u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
|
||||
u32 cr0 = mfdcr(DCRN_CPC0_CR0);
|
||||
u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
|
||||
u32 opdv = CPC0_SYS0_OPDV(sys0);
|
||||
u32 epdv = CPC0_SYS0_EPDV(sys0);
|
||||
|
||||
mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0);
|
||||
reg = mfdcr(DCRN_CPR0_DATA);
|
||||
tmp = (reg & 0x000F0000) >> 16;
|
||||
fwdva = tmp ? tmp : 16;
|
||||
tmp = (reg & 0x00000700) >> 8;
|
||||
fwdvb = tmp ? tmp : 8;
|
||||
tmp = (reg & 0x1F000000) >> 24;
|
||||
fbdv = tmp ? tmp : 32;
|
||||
lfbdv = (reg & 0x0000007F);
|
||||
|
||||
mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0);
|
||||
reg = mfdcr(DCRN_CPR0_DATA);
|
||||
tmp = (reg & 0x03000000) >> 24;
|
||||
opbdv0 = tmp ? tmp : 4;
|
||||
|
||||
mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0);
|
||||
reg = mfdcr(DCRN_CPR0_DATA);
|
||||
tmp = (reg & 0x07000000) >> 24;
|
||||
perdv0 = tmp ? tmp : 8;
|
||||
|
||||
mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0);
|
||||
reg = mfdcr(DCRN_CPR0_DATA);
|
||||
tmp = (reg & 0x07000000) >> 24;
|
||||
prbdv0 = tmp ? tmp : 8;
|
||||
|
||||
mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID);
|
||||
reg = mfdcr(DCRN_CPR0_DATA);
|
||||
tmp = (reg & 0x03000000) >> 24;
|
||||
spcid0 = tmp ? tmp : 4;
|
||||
|
||||
/* Calculate M */
|
||||
mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0);
|
||||
reg = mfdcr(DCRN_CPR0_DATA);
|
||||
tmp = (reg & 0x03000000) >> 24;
|
||||
if (tmp == 0) { /* PLL output */
|
||||
tmp = (reg & 0x20000000) >> 29;
|
||||
if (!tmp) /* PLLOUTA */
|
||||
m = fbdv * lfbdv * fwdva;
|
||||
if (sys0 & CPC0_SYS0_BYPASS) {
|
||||
/* Bypass system PLL */
|
||||
cpu = plb = sys_clk;
|
||||
} else {
|
||||
if (sys0 & CPC0_SYS0_EXTSL)
|
||||
/* PerClk */
|
||||
m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
|
||||
else
|
||||
m = fbdv * lfbdv * fwdvb;
|
||||
/* CPU clock */
|
||||
m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
|
||||
cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0);
|
||||
plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0);
|
||||
}
|
||||
else if (tmp == 1) /* CPU output */
|
||||
m = fbdv * fwdva;
|
||||
|
||||
opb = plb / opdv;
|
||||
ebc = opb / epdv;
|
||||
|
||||
/* FIXME: Check if this is for all 440GP, or just Ebony */
|
||||
if ((mfpvr() & 0xf0000fff) == 0x40000440)
|
||||
/* Rev. B 440GP, use external system clock */
|
||||
tb = sys_clk;
|
||||
else
|
||||
m = perdv0 * opbdv0 * fwdvb;
|
||||
/* Rev. C 440GP, errata force us to use internal clock */
|
||||
tb = cpu;
|
||||
|
||||
vco = (m * sysclk) + (m >> 1);
|
||||
cpu = vco / fwdva;
|
||||
plb = vco / fwdvb / prbdv0;
|
||||
if (cr0 & CPC0_CR0_U0EC)
|
||||
/* External UART clock */
|
||||
uart0 = ser_clk;
|
||||
else
|
||||
/* Internal UART clock */
|
||||
uart0 = plb / CPC0_CR0_UDIV(cr0);
|
||||
|
||||
if (cr0 & CPC0_CR0_U1EC)
|
||||
/* External UART clock */
|
||||
uart1 = ser_clk;
|
||||
else
|
||||
/* Internal UART clock */
|
||||
uart1 = plb / CPC0_CR0_UDIV(cr0);
|
||||
|
||||
printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
|
||||
(sys_clk + 500000) / 1000000, sys_clk);
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/opb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@40000200", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@40000300", uart1);
|
||||
}
|
||||
|
||||
#define SPRN_CCR1 0x378
|
||||
|
||||
static inline u32 __fix_zero(u32 v, u32 def)
|
||||
{
|
||||
return v ? v : def;
|
||||
}
|
||||
|
||||
static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk,
|
||||
unsigned int tmr_clk,
|
||||
int per_clk_from_opb)
|
||||
{
|
||||
/* PLL config */
|
||||
u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
|
||||
u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
|
||||
|
||||
/* Dividers */
|
||||
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
|
||||
u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
|
||||
u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
|
||||
u32 lfbdv = __fix_zero(plld & 0x3f, 64);
|
||||
u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8);
|
||||
u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8);
|
||||
u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4);
|
||||
u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4);
|
||||
|
||||
/* Input clocks for primary dividers */
|
||||
u32 clk_a, clk_b;
|
||||
|
||||
/* Resulting clocks */
|
||||
u32 cpu, plb, opb, ebc, vco;
|
||||
|
||||
/* Timebase */
|
||||
u32 ccr1, tb = tmr_clk;
|
||||
|
||||
if (pllc & 0x40000000) {
|
||||
u32 m;
|
||||
|
||||
/* Feedback path */
|
||||
switch ((pllc >> 24) & 7) {
|
||||
case 0:
|
||||
/* PLLOUTx */
|
||||
m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
|
||||
break;
|
||||
case 1:
|
||||
/* CPU */
|
||||
m = fwdva * pradv0;
|
||||
break;
|
||||
case 5:
|
||||
/* PERClk */
|
||||
m = fwdvb * prbdv0 * opbdv0 * perdv0;
|
||||
break;
|
||||
default:
|
||||
printf("WARNING ! Invalid PLL feedback source !\n");
|
||||
goto bypass;
|
||||
}
|
||||
m *= fbdv;
|
||||
vco = sys_clk * m;
|
||||
clk_a = vco / fwdva;
|
||||
clk_b = vco / fwdvb;
|
||||
} else {
|
||||
bypass:
|
||||
/* Bypass system PLL */
|
||||
vco = 0;
|
||||
clk_a = clk_b = sys_clk;
|
||||
}
|
||||
|
||||
cpu = clk_a / pradv0;
|
||||
plb = clk_b / prbdv0;
|
||||
opb = plb / opbdv0;
|
||||
ebc = plb / perdv0;
|
||||
|
||||
/* FIXME */
|
||||
uart0 = ser_clk;
|
||||
ebc = (per_clk_from_opb ? opb : plb) / perdv0;
|
||||
|
||||
/* Figure out timebase. Either CPU or default TmrClk */
|
||||
asm volatile (
|
||||
"mfspr %0,%1\n"
|
||||
:
|
||||
"=&r"(reg) : "i"(SPRN_CCR1));
|
||||
if (reg & 0x0080)
|
||||
tb = 25000000; /* TmrClk is 25MHz */
|
||||
else
|
||||
ccr1 = mfspr(SPRN_CCR1);
|
||||
|
||||
/* If passed a 0 tmr_clk, force CPU clock */
|
||||
if (tb == 0) {
|
||||
ccr1 &= ~0x80u;
|
||||
mtspr(SPRN_CCR1, ccr1);
|
||||
}
|
||||
if ((ccr1 & 0x0080) == 0)
|
||||
tb = cpu;
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/opb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
|
||||
|
||||
return plb;
|
||||
}
|
||||
|
||||
static void eplike_fixup_uart_clk(int index, const char *path,
|
||||
unsigned int ser_clk,
|
||||
unsigned int plb_clk)
|
||||
{
|
||||
unsigned int sdr;
|
||||
unsigned int clock;
|
||||
|
||||
switch (index) {
|
||||
case 0:
|
||||
sdr = SDR0_READ(DCRN_SDR0_UART0);
|
||||
break;
|
||||
case 1:
|
||||
sdr = SDR0_READ(DCRN_SDR0_UART1);
|
||||
break;
|
||||
case 2:
|
||||
sdr = SDR0_READ(DCRN_SDR0_UART2);
|
||||
break;
|
||||
case 3:
|
||||
sdr = SDR0_READ(DCRN_SDR0_UART3);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
if (sdr & 0x00800000u)
|
||||
clock = ser_clk;
|
||||
else
|
||||
clock = plb_clk / __fix_zero(sdr & 0xff, 256);
|
||||
|
||||
dt_fixup_clock(path, clock);
|
||||
}
|
||||
|
||||
void ibm440ep_fixup_clocks(unsigned int sys_clk,
|
||||
unsigned int ser_clk,
|
||||
unsigned int tmr_clk)
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
|
||||
|
||||
/* serial clocks beed fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
|
||||
}
|
||||
|
||||
void ibm440gx_fixup_clocks(unsigned int sys_clk,
|
||||
unsigned int ser_clk,
|
||||
unsigned int tmr_clk)
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
|
||||
|
||||
/* serial clocks beed fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
|
||||
}
|
||||
|
||||
void ibm440spe_fixup_clocks(unsigned int sys_clk,
|
||||
unsigned int ser_clk,
|
||||
unsigned int tmr_clk)
|
||||
{
|
||||
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
|
||||
|
||||
/* serial clocks beed fixup based on int/ext */
|
||||
eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk);
|
||||
eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk);
|
||||
}
|
||||
|
||||
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
|
||||
{
|
||||
u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
|
||||
u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
|
||||
u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
|
||||
u32 psr = mfdcr(DCRN_405_CPC0_PSR);
|
||||
u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
|
||||
u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
|
||||
|
||||
fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
|
||||
fbdv = (pllmr & 0x1e000000) >> 25;
|
||||
if (fbdv == 0)
|
||||
fbdv = 16;
|
||||
cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
|
||||
opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
|
||||
ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
|
||||
epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
|
||||
udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
|
||||
|
||||
/* check for 405GPr */
|
||||
if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
|
||||
fwdvb = 8 - (pllmr & 0x00000007);
|
||||
if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
|
||||
if (psr & 0x00000020) /* New mode enable */
|
||||
m = fwdvb * 2 * ppdv;
|
||||
else
|
||||
m = fwdvb * cbdv * ppdv;
|
||||
else if (psr & 0x00000020) /* New mode enable */
|
||||
if (psr & 0x00000800) /* PerClk synch mode */
|
||||
m = fwdvb * 2 * epdv;
|
||||
else
|
||||
m = fbdv * fwdv;
|
||||
else if (epdv == fbdv)
|
||||
m = fbdv * cbdv * epdv;
|
||||
else
|
||||
m = fbdv * fwdvb * cbdv;
|
||||
|
||||
cpu = sys_clk * m / fwdv;
|
||||
plb = sys_clk * m / (fwdvb * cbdv);
|
||||
} else {
|
||||
m = fwdv * fbdv * cbdv;
|
||||
cpu = sys_clk * m / fwdv;
|
||||
plb = cpu / cbdv;
|
||||
}
|
||||
opb = plb / opdv;
|
||||
ebc = plb / epdv;
|
||||
|
||||
if (cpc0_cr0 & 0x80)
|
||||
/* uart0 uses the external clock */
|
||||
uart0 = ser_clk;
|
||||
else
|
||||
uart0 = cpu / udiv;
|
||||
|
||||
if (cpc0_cr0 & 0x40)
|
||||
/* uart1 uses the external clock */
|
||||
uart1 = ser_clk;
|
||||
else
|
||||
uart1 = cpu / udiv;
|
||||
|
||||
/* setup the timebase clock to tick at the cpu frequency */
|
||||
cpc0_cr1 = cpc0_cr1 & ~0x00800000;
|
||||
mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
|
||||
tb = cpu;
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
|
||||
}
|
||||
|
||||
|
||||
void ibm405ep_fixup_clocks(unsigned int sys_clk)
|
||||
{
|
||||
u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
|
||||
u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
|
||||
u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
|
||||
u32 cpu, plb, opb, ebc, uart0, uart1;
|
||||
u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
|
||||
u32 pllmr0_ccdv, tb, m;
|
||||
|
||||
fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
|
||||
fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
|
||||
fbdv = (pllmr1 & 0x00f00000) >> 20;
|
||||
if (fbdv == 0)
|
||||
fbdv = 16;
|
||||
|
||||
cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
|
||||
epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */
|
||||
opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
|
||||
|
||||
m = fbdv * fwdvb;
|
||||
|
||||
pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
|
||||
if (pllmr1 & 0x80000000)
|
||||
cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
|
||||
else
|
||||
cpu = sys_clk / pllmr0_ccdv;
|
||||
|
||||
plb = cpu / cbdv;
|
||||
opb = plb / opdv;
|
||||
ebc = plb / epdv;
|
||||
tb = cpu;
|
||||
uart0 = cpu / (cpc0_ucr & 0x0000007f);
|
||||
uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
|
||||
|
||||
dt_fixup_cpu_clocks(cpu, tb, 0);
|
||||
dt_fixup_clock("/plb", plb);
|
||||
dt_fixup_clock("/plb/opb", opb);
|
||||
dt_fixup_clock("/plb/ebc", ebc);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
|
||||
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,12 +11,22 @@
|
|||
#ifndef _POWERPC_BOOT_4XX_H_
|
||||
#define _POWERPC_BOOT_4XX_H_
|
||||
|
||||
void ibm4xx_fixup_memsize(void);
|
||||
void ibm4xx_sdram_fixup_memsize(void);
|
||||
void ibm440spe_fixup_memsize(void);
|
||||
void ibm4xx_denali_fixup_memsize(void);
|
||||
void ibm44x_dbcr_reset(void);
|
||||
void ibm40x_dbcr_reset(void);
|
||||
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
|
||||
void ibm4xx_fixup_ebc_ranges(const char *ebc);
|
||||
void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
|
||||
|
||||
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
|
||||
void ibm405ep_fixup_clocks(unsigned int sys_clk);
|
||||
void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
|
||||
void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
|
||||
unsigned int tmr_clk);
|
||||
void ibm440gx_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
|
||||
unsigned int tmr_clk);
|
||||
void ibm440spe_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
|
||||
unsigned int tmr_clk);
|
||||
|
||||
#endif /* _POWERPC_BOOT_4XX_H_ */
|
||||
|
|
|
|||
|
|
@ -33,12 +33,15 @@ ifeq ($(call cc-option-yn, -fstack-protector),y)
|
|||
BOOTCFLAGS += -fno-stack-protector
|
||||
endif
|
||||
|
||||
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj)
|
||||
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) -I$(srctree)/$(src)/libfdt
|
||||
|
||||
$(obj)/4xx.o: BOOTCFLAGS += -mcpu=440
|
||||
$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440
|
||||
$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=440
|
||||
$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440
|
||||
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
|
||||
|
||||
|
||||
zlib := inffast.c inflate.c inftrees.c
|
||||
zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
|
||||
zliblinuxheader := zlib.h zconf.h zutil.h
|
||||
|
|
@ -46,17 +49,21 @@ zliblinuxheader := zlib.h zconf.h zutil.h
|
|||
$(addprefix $(obj)/,$(zlib) gunzip_util.o main.o): \
|
||||
$(addprefix $(obj)/,$(zliblinuxheader)) $(addprefix $(obj)/,$(zlibheader))
|
||||
|
||||
src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \
|
||||
src-libfdt := fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c
|
||||
src-wlib := string.S crt0.S stdio.c main.c \
|
||||
$(addprefix libfdt/,$(src-libfdt)) libfdt-wrapper.c \
|
||||
ns16550.c serial.c simple_alloc.c div64.S util.S \
|
||||
gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
|
||||
4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
|
||||
cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
|
||||
fsl-soc.c mpc8xx.c pq2.c
|
||||
src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
|
||||
src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \
|
||||
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
|
||||
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
|
||||
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
|
||||
fixed-head.S ep88xc.c cuboot-hpc2.c
|
||||
fixed-head.S ep88xc.c cuboot-hpc2.c ep405.c cuboot-taishan.c \
|
||||
cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
|
||||
cuboot-warp.c cuboot-85xx-cpm2.c
|
||||
src-boot := $(src-wlib) $(src-plat) empty.c
|
||||
|
||||
src-boot := $(addprefix $(obj)/, $(src-boot))
|
||||
|
|
@ -101,23 +108,60 @@ quiet_cmd_bootar = BOOTAR $@
|
|||
cmd_bootar = $(CROSS32AR) -cr $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
|
||||
|
||||
$(patsubst %.c,%.o, $(filter %.c, $(src-boot))): %.o: %.c FORCE
|
||||
$(Q)mkdir -p $(dir $@)
|
||||
$(call if_changed_dep,bootcc)
|
||||
$(patsubst %.S,%.o, $(filter %.S, $(src-boot))): %.o: %.S FORCE
|
||||
$(Q)mkdir -p $(dir $@)
|
||||
$(call if_changed_dep,bootas)
|
||||
|
||||
$(obj)/wrapper.a: $(obj-wlib) FORCE
|
||||
$(call if_changed,bootar)
|
||||
|
||||
hostprogs-y := addnote addRamDisk hack-coff mktree
|
||||
hostprogs-y := addnote addRamDisk hack-coff mktree dtc
|
||||
|
||||
targets += $(patsubst $(obj)/%,%,$(obj-boot) wrapper.a)
|
||||
extra-y := $(obj)/wrapper.a $(obj-plat) $(obj)/empty.o \
|
||||
$(obj)/zImage.lds $(obj)/zImage.coff.lds $(obj)/zImage.ps3.lds
|
||||
|
||||
wrapper :=$(srctree)/$(src)/wrapper
|
||||
wrapperbits := $(extra-y) $(addprefix $(obj)/,addnote hack-coff mktree) \
|
||||
wrapperbits := $(extra-y) $(addprefix $(obj)/,addnote hack-coff mktree dtc) \
|
||||
$(wrapper) FORCE
|
||||
|
||||
#############
|
||||
# Bits for building dtc
|
||||
# DTC_GENPARSER := 1 # Uncomment to rebuild flex/bison output
|
||||
|
||||
dtc-objs := dtc.o flattree.o fstree.o data.o livetree.o treesource.o srcpos.o checks.o
|
||||
dtc-objs += dtc-lexer.lex.o dtc-parser.tab.o
|
||||
dtc-objs := $(addprefix dtc-src/, $(dtc-objs))
|
||||
|
||||
# prerequisites on generated files needs to be explicit
|
||||
$(obj)/dtc-src/dtc-parser.tab.o: $(obj)/dtc-src/dtc-parser.tab.c $(obj)/dtc-src/dtc-parser.tab.h
|
||||
$(obj)/dtc-src/dtc-lexer.lex.o: $(obj)/dtc-src/dtc-lexer.lex.c $(obj)/dtc-src/dtc-parser.tab.h
|
||||
|
||||
HOSTCFLAGS += -I$(src)/dtc-src/ -I$(src)/libfdt/
|
||||
|
||||
targets += dtc-src/dtc-parser.tab.c
|
||||
targets += dtc-src/dtc-lexer.lex.c
|
||||
|
||||
ifdef DTC_GENPARSER
|
||||
BISON = bison
|
||||
FLEX = flex
|
||||
|
||||
quiet_cmd_bison = BISON $@
|
||||
cmd_bison = $(BISON) -o$@ -d $<; cp $@ $@_shipped
|
||||
quiet_cmd_flex = FLEX $@
|
||||
cmd_flex = $(FLEX) -o$@ $<; cp $@ $@_shipped
|
||||
|
||||
$(obj)/dtc-src/dtc-parser.tab.c: $(src)/dtc-src/dtc-parser.y FORCE
|
||||
$(call if_changed,bison)
|
||||
|
||||
$(obj)/dtc-src/dtc-parser.tab.h: $(obj)/dtc-src/dtc-parser.tab.c
|
||||
|
||||
$(obj)/dtc-src/dtc-lexer.lex.c: $(src)/dtc-src/dtc-lexer.l FORCE
|
||||
$(call if_changed,flex)
|
||||
endif
|
||||
|
||||
#############
|
||||
# Bits for building various flavours of zImage
|
||||
|
||||
|
|
@ -150,15 +194,29 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImage
|
|||
ifneq ($(CONFIG_DEVICE_TREE),"")
|
||||
image-$(CONFIG_PPC_8xx) += cuImage.8xx
|
||||
image-$(CONFIG_PPC_EP88XC) += zImage.ep88xc
|
||||
image-$(CONFIG_EP405) += zImage.ep405
|
||||
image-$(CONFIG_8260) += cuImage.pq2
|
||||
image-$(CONFIG_EP8248E) += zImage.ep8248e
|
||||
image-$(CONFIG_PPC_MPC52xx) += cuImage.52xx
|
||||
image-$(CONFIG_STORCENTER) += cuImage.824x
|
||||
image-$(CONFIG_PPC_83xx) += cuImage.83xx
|
||||
image-$(CONFIG_PPC_85xx) += cuImage.85xx
|
||||
ifeq ($(CONFIG_CPM2),y)
|
||||
image-$(CONFIG_PPC_85xx) += cuImage.85xx-cpm2
|
||||
endif
|
||||
image-$(CONFIG_MPC7448HPC2) += cuImage.hpc2
|
||||
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
|
||||
image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo
|
||||
image-$(CONFIG_SEQUOIA) += cuImage.sequoia
|
||||
image-$(CONFIG_RAINIER) += cuImage.rainier
|
||||
image-$(CONFIG_WALNUT) += treeImage.walnut
|
||||
image-$(CONFIG_TAISHAN) += cuImage.taishan
|
||||
image-$(CONFIG_KATMAI) += cuImage.katmai
|
||||
image-$(CONFIG_WARP) += cuImage.warp
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_REDBOOT),"")
|
||||
image-$(CONFIG_PPC_8xx) += zImage.redboot-8xx
|
||||
endif
|
||||
|
||||
# For 32-bit powermacs, build the COFF and miboot images
|
||||
|
|
@ -243,3 +301,51 @@ clean-kernel := vmlinux.strip vmlinux.bin
|
|||
clean-kernel += $(addsuffix .gz,$(clean-kernel))
|
||||
# If not absolute clean-files are relative to $(obj).
|
||||
clean-files += $(addprefix $(objtree)/, $(clean-kernel))
|
||||
|
||||
WRAPPER_OBJDIR := /usr/lib/kernel-wrapper
|
||||
WRAPPER_DTSDIR := /usr/lib/kernel-wrapper/dts
|
||||
WRAPPER_BINDIR := /usr/sbin
|
||||
INSTALL := install
|
||||
|
||||
extra-installed := $(patsubst $(obj)/%, $(DESTDIR)$(WRAPPER_OBJDIR)/%, $(extra-y))
|
||||
hostprogs-installed := $(patsubst %, $(DESTDIR)$(WRAPPER_BINDIR)/%, $(hostprogs-y))
|
||||
wrapper-installed := $(DESTDIR)$(WRAPPER_BINDIR)/wrapper
|
||||
dts-installed := $(patsubst $(obj)/dts/%, $(DESTDIR)$(WRAPPER_DTSDIR)/%, $(wildcard $(obj)/dts/*.dts))
|
||||
|
||||
all-installed := $(extra-installed) $(hostprogs-installed) $(wrapper-installed) $(dts-installed)
|
||||
|
||||
quiet_cmd_mkdir = MKDIR $(patsubst $(INSTALL_HDR_PATH)/%,%,$@)
|
||||
cmd_mkdir = mkdir -p $@
|
||||
|
||||
quiet_cmd_install = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_OBJDIR)/%,%,$@)
|
||||
cmd_install = $(INSTALL) -m0644 $(patsubst $(DESTDIR)$(WRAPPER_OBJDIR)/%,$(obj)/%,$@) $@
|
||||
|
||||
quiet_cmd_install_dts = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_DTSDIR)/%,dts/%,$@)
|
||||
cmd_install_dts = $(INSTALL) -m0644 $(patsubst $(DESTDIR)$(WRAPPER_DTSDIR)/%,$(srctree)/$(obj)/dts/%,$@) $@
|
||||
|
||||
quiet_cmd_install_exe = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,%,$@)
|
||||
cmd_install_exe = $(INSTALL) -m0755 $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,$(obj)/%,$@) $@
|
||||
|
||||
quiet_cmd_install_wrapper = INSTALL $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,%,$@)
|
||||
cmd_install_wrapper = $(INSTALL) -m0755 $(patsubst $(DESTDIR)$(WRAPPER_BINDIR)/%,$(srctree)/$(obj)/%,$@) $@ ;\
|
||||
sed -i $@ -e 's%^object=.*%object=$(WRAPPER_OBJDIR)%' \
|
||||
-e 's%^objbin=.*%objbin=$(WRAPPER_BINDIR)%' \
|
||||
|
||||
|
||||
$(DESTDIR)$(WRAPPER_OBJDIR) $(DESTDIR)$(WRAPPER_DTSDIR) $(DESTDIR)$(WRAPPER_BINDIR):
|
||||
$(call cmd,mkdir)
|
||||
|
||||
$(extra-installed) : $(DESTDIR)$(WRAPPER_OBJDIR)/% : $(obj)/% | $(DESTDIR)$(WRAPPER_OBJDIR)
|
||||
$(call cmd,install)
|
||||
|
||||
$(hostprogs-installed) : $(DESTDIR)$(WRAPPER_BINDIR)/% : $(obj)/% | $(DESTDIR)$(WRAPPER_BINDIR)
|
||||
$(call cmd,install_exe)
|
||||
|
||||
$(dts-installed) : $(DESTDIR)$(WRAPPER_DTSDIR)/% : $(srctree)/$(obj)/dts/% | $(DESTDIR)$(WRAPPER_DTSDIR)
|
||||
$(call cmd,install_dts)
|
||||
|
||||
$(wrapper-installed): $(DESTDIR)$(WRAPPER_BINDIR) $(srctree)/$(obj)/wrapper | $(DESTDIR)$(WRAPPER_BINDIR)
|
||||
$(call cmd,install_wrapper)
|
||||
|
||||
$(obj)/bootwrapper_install: $(all-installed)
|
||||
|
||||
|
|
|
|||
|
|
@ -30,8 +30,8 @@ static void bamboo_fixups(void)
|
|||
{
|
||||
unsigned long sysclk = 33333333;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200);
|
||||
ibm4xx_fixup_memsize();
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
|
||||
dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
|
||||
}
|
||||
|
|
@ -42,6 +42,6 @@ void bamboo_init(void *mac0, void *mac1)
|
|||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
bamboo_mac0 = mac0;
|
||||
bamboo_mac1 = mac1;
|
||||
ft_init(_dtb_start, 0, 32);
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
|
|
|
|||
53
arch/powerpc/boot/cuboot-824x.c
Normal file
53
arch/powerpc/boot/cuboot-824x.c
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Old U-boot compatibility for 824x
|
||||
*
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_824x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *soc;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||
|
||||
soc = find_node_by_devtype(NULL, "soc");
|
||||
if (soc) {
|
||||
void *serial = NULL;
|
||||
|
||||
setprop(soc, "bus-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
|
||||
while ((serial = find_node_by_devtype(serial, "serial"))) {
|
||||
if (get_parent(serial) != soc)
|
||||
continue;
|
||||
|
||||
setprop(serial, "clock-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
|
|
@ -24,7 +24,8 @@ static void platform_fixups(void)
|
|||
void *soc;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
|
||||
|
||||
/* Unfortunately, the specific model number is encoded in the
|
||||
|
|
@ -52,7 +53,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
|
|
|
|||
66
arch/powerpc/boot/cuboot-85xx-cpm2.c
Normal file
66
arch/powerpc/boot/cuboot-85xx-cpm2.c
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Old U-boot compatibility for 85xx
|
||||
*
|
||||
* Author: Scott Wood <scottwood@freescale.com>
|
||||
*
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_85xx
|
||||
#define TARGET_CPM2
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void platform_fixups(void)
|
||||
{
|
||||
void *devp;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq);
|
||||
|
||||
/* Unfortunately, the specific model number is encoded in the
|
||||
* soc node name in existing dts files -- once that is fixed,
|
||||
* this can do a simple path lookup.
|
||||
*/
|
||||
devp = find_node_by_devtype(NULL, "soc");
|
||||
if (devp) {
|
||||
void *serial = NULL;
|
||||
|
||||
setprop(devp, "bus-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
|
||||
while ((serial = find_node_by_devtype(serial, "serial"))) {
|
||||
if (get_parent(serial) != devp)
|
||||
continue;
|
||||
|
||||
setprop(serial, "clock-frequency", &bd.bi_busfreq,
|
||||
sizeof(bd.bi_busfreq));
|
||||
}
|
||||
}
|
||||
|
||||
devp = find_node_by_compatible(NULL, "fsl,cpm2-brg");
|
||||
if (devp)
|
||||
setprop(devp, "clock-frequency", &bd.bi_brgfreq,
|
||||
sizeof(bd.bi_brgfreq));
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
|
|
@ -24,8 +24,9 @@ static void platform_fixups(void)
|
|||
void *soc;
|
||||
|
||||
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr,
|
||||
bd.bi_enet2addr);
|
||||
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
|
||||
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
|
||||
dt_fixup_mac_address_by_alias("ethernet2", bd.bi_enet2addr);
|
||||
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 8, bd.bi_busfreq);
|
||||
|
||||
/* Unfortunately, the specific model number is encoded in the
|
||||
|
|
@ -53,7 +54,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = platform_fixups;
|
||||
}
|
||||
|
|
|
|||
56
arch/powerpc/boot/cuboot-katmai.c
Normal file
56
arch/powerpc/boot/cuboot-katmai.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Katmai
|
||||
*
|
||||
* Author: Hugh Blemings <hugh@au.ibm.com>
|
||||
*
|
||||
* Copyright 2007 Hugh Blemings, IBM Corporation.
|
||||
* Based on cuboot-ebony.c which is:
|
||||
* Copyright 2007 David Gibson, IBM Corporation.
|
||||
* Based on cuboot-83xx.c, which is:
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "reg.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
BSS_STACK(4096);
|
||||
|
||||
static void katmai_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 33333000;
|
||||
|
||||
/* 440SP Clock logic is all but identical to 440GX
|
||||
* so we just use that code for now at least
|
||||
*/
|
||||
ibm440spe_fixup_clocks(sysclk, 6 * 1843200, 0);
|
||||
|
||||
ibm440spe_fixup_memsize();
|
||||
|
||||
dt_fixup_mac_address(0, bd.bi_enetaddr);
|
||||
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
platform_ops.fixups = katmai_fixups;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
|
|
@ -255,7 +255,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
platform_ops.fixups = pq2_platform_fixups;
|
||||
}
|
||||
|
|
|
|||
56
arch/powerpc/boot/cuboot-rainier.c
Normal file
56
arch/powerpc/boot/cuboot-rainier.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Rainier
|
||||
*
|
||||
* Valentine Barshak <vbarshak@ru.mvista.com>
|
||||
* Copyright 2007 MontaVista Software, Inc
|
||||
*
|
||||
* Based on Ebony code by David Gibson <david@gibson.dropbear.id.au>
|
||||
* Copyright IBM Corporation, 2007
|
||||
*
|
||||
* Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
* Copyright IBM Corporation, 2007
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; version 2 of the License
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "types.h"
|
||||
#include "elf.h"
|
||||
#include "string.h"
|
||||
#include "stdio.h"
|
||||
#include "page.h"
|
||||
#include "ops.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
#include "44x.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_4xx
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
|
||||
static void rainier_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 33333333;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
ibm4xx_denali_fixup_memsize();
|
||||
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
platform_ops.fixups = rainier_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
|
|
@ -39,7 +39,7 @@ static void sequoia_fixups(void)
|
|||
{
|
||||
unsigned long sysclk = 33333333;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200);
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
ibm4xx_denali_fixup_memsize();
|
||||
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
|
||||
|
|
@ -51,6 +51,6 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
|||
CUBOOT_INIT();
|
||||
platform_ops.fixups = sequoia_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
ft_init(_dtb_start, 0, 32);
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
|
|
|
|||
54
arch/powerpc/boot/cuboot-taishan.c
Normal file
54
arch/powerpc/boot/cuboot-taishan.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Old U-boot compatibility for Taishan
|
||||
*
|
||||
* Author: Hugh Blemings <hugh@au.ibm.com>
|
||||
*
|
||||
* Copyright 2007 Hugh Blemings, IBM Corporation.
|
||||
* Based on cuboot-ebony.c which is:
|
||||
* Copyright 2007 David Gibson, IBM Corporation.
|
||||
* Based on cuboot-83xx.c, which is:
|
||||
* Copyright (c) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "stdio.h"
|
||||
#include "cuboot.h"
|
||||
#include "reg.h"
|
||||
#include "dcr.h"
|
||||
#include "4xx.h"
|
||||
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
BSS_STACK(4096);
|
||||
|
||||
static void taishan_fixups(void)
|
||||
{
|
||||
/* FIXME: sysclk should be derived by reading the FPGA
|
||||
registers */
|
||||
unsigned long sysclk = 33000000;
|
||||
|
||||
ibm440gx_fixup_clocks(sysclk, 6 * 1843200, 25000000);
|
||||
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
|
||||
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
|
||||
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
}
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
platform_ops.fixups = taishan_fixups;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
39
arch/powerpc/boot/cuboot-warp.c
Normal file
39
arch/powerpc/boot/cuboot-warp.c
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2008 PIKA Technologies
|
||||
* Sean MacLennan <smaclennan@pikatech.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "ops.h"
|
||||
#include "4xx.h"
|
||||
#include "cuboot.h"
|
||||
|
||||
#define TARGET_44x
|
||||
#include "ppcboot.h"
|
||||
|
||||
static bd_t bd;
|
||||
|
||||
static void warp_fixups(void)
|
||||
{
|
||||
unsigned long sysclk = 66000000;
|
||||
|
||||
ibm440ep_fixup_clocks(sysclk, 11059200, 50000000);
|
||||
ibm4xx_sdram_fixup_memsize();
|
||||
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
|
||||
dt_fixup_mac_addresses(&bd.bi_enetaddr);
|
||||
}
|
||||
|
||||
|
||||
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7)
|
||||
{
|
||||
CUBOOT_INIT();
|
||||
|
||||
platform_ops.fixups = warp_fixups;
|
||||
platform_ops.exit = ibm44x_dbcr_reset;
|
||||
fdt_init(_dtb_start);
|
||||
serial_console_init();
|
||||
}
|
||||
|
|
@ -14,12 +14,20 @@
|
|||
#define DCRN_SDRAM0_CFGADDR 0x010
|
||||
#define DCRN_SDRAM0_CFGDATA 0x011
|
||||
|
||||
#define SDRAM0_READ(offset) ({\
|
||||
mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
|
||||
mfdcr(DCRN_SDRAM0_CFGDATA); })
|
||||
#define SDRAM0_WRITE(offset, data) ({\
|
||||
mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
|
||||
mtdcr(DCRN_SDRAM0_CFGDATA, data); })
|
||||
|
||||
#define SDRAM0_B0CR 0x40
|
||||
#define SDRAM0_B1CR 0x44
|
||||
#define SDRAM0_B2CR 0x48
|
||||
#define SDRAM0_B3CR 0x4c
|
||||
|
||||
static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR };
|
||||
static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
|
||||
SDRAM0_B2CR, SDRAM0_B3CR };
|
||||
|
||||
#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
|
||||
#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
|
||||
|
|
@ -138,5 +146,54 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C
|
|||
#define DCRN_CPC0_PLLMR 0xb0
|
||||
#define DCRN_405_CPC0_CR0 0xb1
|
||||
#define DCRN_405_CPC0_CR1 0xb2
|
||||
#define DCRN_405_CPC0_PSR 0xb4
|
||||
|
||||
/* 405EP Clocking/Power Management/Chip Control regs */
|
||||
#define DCRN_CPC0_PLLMR0 0xf0
|
||||
#define DCRN_CPC0_PLLMR1 0xf4
|
||||
#define DCRN_CPC0_UCR 0xf5
|
||||
|
||||
/* 440GX Clock control etc */
|
||||
|
||||
|
||||
#define DCRN_CPR0_CLKUPD 0x020
|
||||
#define DCRN_CPR0_PLLC 0x040
|
||||
#define DCRN_CPR0_PLLD 0x060
|
||||
#define DCRN_CPR0_PRIMAD 0x080
|
||||
#define DCRN_CPR0_PRIMBD 0x0a0
|
||||
#define DCRN_CPR0_OPBD 0x0c0
|
||||
#define DCRN_CPR0_PERD 0x0e0
|
||||
#define DCRN_CPR0_MALD 0x100
|
||||
|
||||
#define DCRN_SDR0_CONFIG_ADDR 0xe
|
||||
#define DCRN_SDR0_CONFIG_DATA 0xf
|
||||
|
||||
/* SDR read/write helper macros */
|
||||
#define SDR0_READ(offset) ({\
|
||||
mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
|
||||
mfdcr(DCRN_SDR0_CONFIG_DATA); })
|
||||
#define SDR0_WRITE(offset, data) ({\
|
||||
mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
|
||||
mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
|
||||
|
||||
#define DCRN_SDR0_UART0 0x0120
|
||||
#define DCRN_SDR0_UART1 0x0121
|
||||
#define DCRN_SDR0_UART2 0x0122
|
||||
#define DCRN_SDR0_UART3 0x0123
|
||||
|
||||
|
||||
/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
|
||||
|
||||
#define DCRN_CPR0_CFGADDR 0xc
|
||||
#define DCRN_CPR0_CFGDATA 0xd
|
||||
|
||||
#define CPR0_READ(offset) ({\
|
||||
mtdcr(DCRN_CPR0_CFGADDR, offset); \
|
||||
mfdcr(DCRN_CPR0_CFGDATA); })
|
||||
#define CPR0_WRITE(offset, data) ({\
|
||||
mtdcr(DCRN_CPR0_CFGADDR, offset); \
|
||||
mtdcr(DCRN_CPR0_CFGDATA, data); })
|
||||
|
||||
|
||||
|
||||
#endif /* _PPC_BOOT_DCR_H_ */
|
||||
|
|
|
|||
|
|
@ -88,6 +88,20 @@ void dt_fixup_clock(const char *path, u32 freq)
|
|||
}
|
||||
}
|
||||
|
||||
void dt_fixup_mac_address_by_alias(const char *alias, const u8 *addr)
|
||||
{
|
||||
void *devp = find_node_by_alias(alias);
|
||||
|
||||
if (devp) {
|
||||
printf("%s: local-mac-address <-"
|
||||
" %02x:%02x:%02x:%02x:%02x:%02x\n\r", alias,
|
||||
addr[0], addr[1], addr[2],
|
||||
addr[3], addr[4], addr[5]);
|
||||
|
||||
setprop(devp, "local-mac-address", addr, 6);
|
||||
}
|
||||
}
|
||||
|
||||
void dt_fixup_mac_address(u32 index, const u8 *addr)
|
||||
{
|
||||
void *devp = find_node_by_prop_value(NULL, "linux,network-index",
|
||||
|
|
|
|||
3
arch/powerpc/boot/dtc-src/.gitignore
vendored
Normal file
3
arch/powerpc/boot/dtc-src/.gitignore
vendored
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
dtc-lexer.lex.c
|
||||
dtc-parser.tab.c
|
||||
dtc-parser.tab.h
|
||||
25
arch/powerpc/boot/dtc-src/Makefile.dtc
Normal file
25
arch/powerpc/boot/dtc-src/Makefile.dtc
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
# Makefile.dtc
|
||||
#
|
||||
# This is not a complete Makefile of itself. Instead, it is designed to
|
||||
# be easily embeddable into other systems of Makefiles.
|
||||
#
|
||||
DTC_SRCS = dtc.c flattree.c fstree.c data.c livetree.c treesource.c srcpos.c \
|
||||
checks.c
|
||||
DTC_EXTRA = dtc.h srcpos.h
|
||||
DTC_LEXFILES = dtc-lexer.l
|
||||
DTC_BISONFILES = dtc-parser.y
|
||||
|
||||
DTC_LEX_SRCS = $(DTC_LEXFILES:%.l=%.lex.c)
|
||||
DTC_BISON_SRCS = $(DTC_BISONFILES:%.y=%.tab.c)
|
||||
DTC_BISON_INCLUDES = $(DTC_BISONFILES:%.y=%.tab.h)
|
||||
|
||||
DTC_GEN_SRCS = $(DTC_LEX_SRCS) $(DTC_BISON_SRCS)
|
||||
DTC_GEN_ALL = $(DTC_GEN_SRCS) $(DTC_BISON_INCLUDES)
|
||||
DTC_OBJS = $(DTC_SRCS:%.c=%.o) $(DTC_GEN_SRCS:%.c=%.o)
|
||||
|
||||
DTC_CLEANFILES = $(DTC_GEN_ALL)
|
||||
|
||||
# We assume the containing Makefile system can do auto-dependencies for most
|
||||
# things, but we supply the dependencies on generated header files explicitly
|
||||
|
||||
$(addprefix $(DTC_objdir)/,$(DTC_GEN_SRCS:%.c=%.o)): $(addprefix $(DTC_objdir)/,$(DTC_BISON_INCLUDES))
|
||||
750
arch/powerpc/boot/dtc-src/checks.c
Normal file
750
arch/powerpc/boot/dtc-src/checks.c
Normal file
|
|
@ -0,0 +1,750 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2007.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "dtc.h"
|
||||
|
||||
#ifdef TRACE_CHECKS
|
||||
#define TRACE(c, ...) \
|
||||
do { \
|
||||
fprintf(stderr, "=== %s: ", (c)->name); \
|
||||
fprintf(stderr, __VA_ARGS__); \
|
||||
fprintf(stderr, "\n"); \
|
||||
} while (0)
|
||||
#else
|
||||
#define TRACE(c, fmt, ...) do { } while (0)
|
||||
#endif
|
||||
|
||||
enum checklevel {
|
||||
IGNORE = 0,
|
||||
WARN = 1,
|
||||
ERROR = 2,
|
||||
};
|
||||
|
||||
enum checkstatus {
|
||||
UNCHECKED = 0,
|
||||
PREREQ,
|
||||
PASSED,
|
||||
FAILED,
|
||||
};
|
||||
|
||||
struct check;
|
||||
|
||||
typedef void (*tree_check_fn)(struct check *c, struct node *dt);
|
||||
typedef void (*node_check_fn)(struct check *c, struct node *dt, struct node *node);
|
||||
typedef void (*prop_check_fn)(struct check *c, struct node *dt,
|
||||
struct node *node, struct property *prop);
|
||||
|
||||
struct check {
|
||||
const char *name;
|
||||
tree_check_fn tree_fn;
|
||||
node_check_fn node_fn;
|
||||
prop_check_fn prop_fn;
|
||||
void *data;
|
||||
enum checklevel level;
|
||||
enum checkstatus status;
|
||||
int inprogress;
|
||||
int num_prereqs;
|
||||
struct check **prereq;
|
||||
};
|
||||
|
||||
#define CHECK(nm, tfn, nfn, pfn, d, lvl, ...) \
|
||||
static struct check *nm##_prereqs[] = { __VA_ARGS__ }; \
|
||||
static struct check nm = { \
|
||||
.name = #nm, \
|
||||
.tree_fn = (tfn), \
|
||||
.node_fn = (nfn), \
|
||||
.prop_fn = (pfn), \
|
||||
.data = (d), \
|
||||
.level = (lvl), \
|
||||
.status = UNCHECKED, \
|
||||
.num_prereqs = ARRAY_SIZE(nm##_prereqs), \
|
||||
.prereq = nm##_prereqs, \
|
||||
};
|
||||
|
||||
#define TREE_CHECK(nm, d, lvl, ...) \
|
||||
CHECK(nm, check_##nm, NULL, NULL, d, lvl, __VA_ARGS__)
|
||||
#define NODE_CHECK(nm, d, lvl, ...) \
|
||||
CHECK(nm, NULL, check_##nm, NULL, d, lvl, __VA_ARGS__)
|
||||
#define PROP_CHECK(nm, d, lvl, ...) \
|
||||
CHECK(nm, NULL, NULL, check_##nm, d, lvl, __VA_ARGS__)
|
||||
#define BATCH_CHECK(nm, lvl, ...) \
|
||||
CHECK(nm, NULL, NULL, NULL, NULL, lvl, __VA_ARGS__)
|
||||
|
||||
#ifdef __GNUC__
|
||||
static inline void check_msg(struct check *c, const char *fmt, ...) __attribute__((format (printf, 2, 3)));
|
||||
#endif
|
||||
static inline void check_msg(struct check *c, const char *fmt, ...)
|
||||
{
|
||||
va_list ap;
|
||||
va_start(ap, fmt);
|
||||
|
||||
if ((c->level < WARN) || (c->level <= quiet))
|
||||
return; /* Suppress message */
|
||||
|
||||
fprintf(stderr, "%s (%s): ",
|
||||
(c->level == ERROR) ? "ERROR" : "Warning", c->name);
|
||||
vfprintf(stderr, fmt, ap);
|
||||
fprintf(stderr, "\n");
|
||||
}
|
||||
|
||||
#define FAIL(c, ...) \
|
||||
do { \
|
||||
TRACE((c), "\t\tFAILED at %s:%d", __FILE__, __LINE__); \
|
||||
(c)->status = FAILED; \
|
||||
check_msg((c), __VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
static void check_nodes_props(struct check *c, struct node *dt, struct node *node)
|
||||
{
|
||||
struct node *child;
|
||||
struct property *prop;
|
||||
|
||||
TRACE(c, "%s", node->fullpath);
|
||||
if (c->node_fn)
|
||||
c->node_fn(c, dt, node);
|
||||
|
||||
if (c->prop_fn)
|
||||
for_each_property(node, prop) {
|
||||
TRACE(c, "%s\t'%s'", node->fullpath, prop->name);
|
||||
c->prop_fn(c, dt, node, prop);
|
||||
}
|
||||
|
||||
for_each_child(node, child)
|
||||
check_nodes_props(c, dt, child);
|
||||
}
|
||||
|
||||
static int run_check(struct check *c, struct node *dt)
|
||||
{
|
||||
int error = 0;
|
||||
int i;
|
||||
|
||||
assert(!c->inprogress);
|
||||
|
||||
if (c->status != UNCHECKED)
|
||||
goto out;
|
||||
|
||||
c->inprogress = 1;
|
||||
|
||||
for (i = 0; i < c->num_prereqs; i++) {
|
||||
struct check *prq = c->prereq[i];
|
||||
error |= run_check(prq, dt);
|
||||
if (prq->status != PASSED) {
|
||||
c->status = PREREQ;
|
||||
check_msg(c, "Failed prerequisite '%s'",
|
||||
c->prereq[i]->name);
|
||||
}
|
||||
}
|
||||
|
||||
if (c->status != UNCHECKED)
|
||||
goto out;
|
||||
|
||||
if (c->node_fn || c->prop_fn)
|
||||
check_nodes_props(c, dt, dt);
|
||||
|
||||
if (c->tree_fn)
|
||||
c->tree_fn(c, dt);
|
||||
if (c->status == UNCHECKED)
|
||||
c->status = PASSED;
|
||||
|
||||
TRACE(c, "\tCompleted, status %d", c->status);
|
||||
|
||||
out:
|
||||
c->inprogress = 0;
|
||||
if ((c->status != PASSED) && (c->level == ERROR))
|
||||
error = 1;
|
||||
return error;
|
||||
}
|
||||
|
||||
/*
|
||||
* Utility check functions
|
||||
*/
|
||||
|
||||
static void check_is_string(struct check *c, struct node *root,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
char *propname = c->data;
|
||||
|
||||
prop = get_property(node, propname);
|
||||
if (!prop)
|
||||
return; /* Not present, assumed ok */
|
||||
|
||||
if (!data_is_one_string(prop->val))
|
||||
FAIL(c, "\"%s\" property in %s is not a string",
|
||||
propname, node->fullpath);
|
||||
}
|
||||
#define CHECK_IS_STRING(nm, propname, lvl) \
|
||||
CHECK(nm, NULL, check_is_string, NULL, (propname), (lvl))
|
||||
|
||||
static void check_is_cell(struct check *c, struct node *root,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
char *propname = c->data;
|
||||
|
||||
prop = get_property(node, propname);
|
||||
if (!prop)
|
||||
return; /* Not present, assumed ok */
|
||||
|
||||
if (prop->val.len != sizeof(cell_t))
|
||||
FAIL(c, "\"%s\" property in %s is not a single cell",
|
||||
propname, node->fullpath);
|
||||
}
|
||||
#define CHECK_IS_CELL(nm, propname, lvl) \
|
||||
CHECK(nm, NULL, check_is_cell, NULL, (propname), (lvl))
|
||||
|
||||
/*
|
||||
* Structural check functions
|
||||
*/
|
||||
|
||||
static void check_duplicate_node_names(struct check *c, struct node *dt,
|
||||
struct node *node)
|
||||
{
|
||||
struct node *child, *child2;
|
||||
|
||||
for_each_child(node, child)
|
||||
for (child2 = child->next_sibling;
|
||||
child2;
|
||||
child2 = child2->next_sibling)
|
||||
if (streq(child->name, child2->name))
|
||||
FAIL(c, "Duplicate node name %s",
|
||||
child->fullpath);
|
||||
}
|
||||
NODE_CHECK(duplicate_node_names, NULL, ERROR);
|
||||
|
||||
static void check_duplicate_property_names(struct check *c, struct node *dt,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *prop, *prop2;
|
||||
|
||||
for_each_property(node, prop)
|
||||
for (prop2 = prop->next; prop2; prop2 = prop2->next)
|
||||
if (streq(prop->name, prop2->name))
|
||||
FAIL(c, "Duplicate property name %s in %s",
|
||||
prop->name, node->fullpath);
|
||||
}
|
||||
NODE_CHECK(duplicate_property_names, NULL, ERROR);
|
||||
|
||||
static void check_explicit_phandles(struct check *c, struct node *root,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
struct node *other;
|
||||
cell_t phandle;
|
||||
|
||||
prop = get_property(node, "linux,phandle");
|
||||
if (! prop)
|
||||
return; /* No phandle, that's fine */
|
||||
|
||||
if (prop->val.len != sizeof(cell_t)) {
|
||||
FAIL(c, "%s has bad length (%d) linux,phandle property",
|
||||
node->fullpath, prop->val.len);
|
||||
return;
|
||||
}
|
||||
|
||||
phandle = propval_cell(prop);
|
||||
if ((phandle == 0) || (phandle == -1)) {
|
||||
FAIL(c, "%s has invalid linux,phandle value 0x%x",
|
||||
node->fullpath, phandle);
|
||||
return;
|
||||
}
|
||||
|
||||
other = get_node_by_phandle(root, phandle);
|
||||
if (other) {
|
||||
FAIL(c, "%s has duplicated phandle 0x%x (seen before at %s)",
|
||||
node->fullpath, phandle, other->fullpath);
|
||||
return;
|
||||
}
|
||||
|
||||
node->phandle = phandle;
|
||||
}
|
||||
NODE_CHECK(explicit_phandles, NULL, ERROR);
|
||||
|
||||
static void check_name_properties(struct check *c, struct node *root,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
|
||||
prop = get_property(node, "name");
|
||||
if (!prop)
|
||||
return; /* No name property, that's fine */
|
||||
|
||||
if ((prop->val.len != node->basenamelen+1)
|
||||
|| (memcmp(prop->val.val, node->name, node->basenamelen) != 0))
|
||||
FAIL(c, "\"name\" property in %s is incorrect (\"%s\" instead"
|
||||
" of base node name)", node->fullpath, prop->val.val);
|
||||
}
|
||||
CHECK_IS_STRING(name_is_string, "name", ERROR);
|
||||
NODE_CHECK(name_properties, NULL, ERROR, &name_is_string);
|
||||
|
||||
/*
|
||||
* Reference fixup functions
|
||||
*/
|
||||
|
||||
static void fixup_phandle_references(struct check *c, struct node *dt,
|
||||
struct node *node, struct property *prop)
|
||||
{
|
||||
struct marker *m = prop->val.markers;
|
||||
struct node *refnode;
|
||||
cell_t phandle;
|
||||
|
||||
for_each_marker_of_type(m, REF_PHANDLE) {
|
||||
assert(m->offset + sizeof(cell_t) <= prop->val.len);
|
||||
|
||||
refnode = get_node_by_ref(dt, m->ref);
|
||||
if (! refnode) {
|
||||
FAIL(c, "Reference to non-existent node or label \"%s\"\n",
|
||||
m->ref);
|
||||
continue;
|
||||
}
|
||||
|
||||
phandle = get_node_phandle(dt, refnode);
|
||||
*((cell_t *)(prop->val.val + m->offset)) = cpu_to_be32(phandle);
|
||||
}
|
||||
}
|
||||
CHECK(phandle_references, NULL, NULL, fixup_phandle_references, NULL, ERROR,
|
||||
&duplicate_node_names, &explicit_phandles);
|
||||
|
||||
static void fixup_path_references(struct check *c, struct node *dt,
|
||||
struct node *node, struct property *prop)
|
||||
{
|
||||
struct marker *m = prop->val.markers;
|
||||
struct node *refnode;
|
||||
char *path;
|
||||
|
||||
for_each_marker_of_type(m, REF_PATH) {
|
||||
assert(m->offset <= prop->val.len);
|
||||
|
||||
refnode = get_node_by_ref(dt, m->ref);
|
||||
if (!refnode) {
|
||||
FAIL(c, "Reference to non-existent node or label \"%s\"\n",
|
||||
m->ref);
|
||||
continue;
|
||||
}
|
||||
|
||||
path = refnode->fullpath;
|
||||
prop->val = data_insert_at_marker(prop->val, m, path,
|
||||
strlen(path) + 1);
|
||||
}
|
||||
}
|
||||
CHECK(path_references, NULL, NULL, fixup_path_references, NULL, ERROR,
|
||||
&duplicate_node_names);
|
||||
|
||||
/*
|
||||
* Semantic checks
|
||||
*/
|
||||
CHECK_IS_CELL(address_cells_is_cell, "#address-cells", WARN);
|
||||
CHECK_IS_CELL(size_cells_is_cell, "#size-cells", WARN);
|
||||
CHECK_IS_CELL(interrupt_cells_is_cell, "#interrupt-cells", WARN);
|
||||
|
||||
CHECK_IS_STRING(device_type_is_string, "device_type", WARN);
|
||||
CHECK_IS_STRING(model_is_string, "model", WARN);
|
||||
CHECK_IS_STRING(status_is_string, "status", WARN);
|
||||
|
||||
static void fixup_addr_size_cells(struct check *c, struct node *dt,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
|
||||
node->addr_cells = -1;
|
||||
node->size_cells = -1;
|
||||
|
||||
prop = get_property(node, "#address-cells");
|
||||
if (prop)
|
||||
node->addr_cells = propval_cell(prop);
|
||||
|
||||
prop = get_property(node, "#size-cells");
|
||||
if (prop)
|
||||
node->size_cells = propval_cell(prop);
|
||||
}
|
||||
CHECK(addr_size_cells, NULL, fixup_addr_size_cells, NULL, NULL, WARN,
|
||||
&address_cells_is_cell, &size_cells_is_cell);
|
||||
|
||||
#define node_addr_cells(n) \
|
||||
(((n)->addr_cells == -1) ? 2 : (n)->addr_cells)
|
||||
#define node_size_cells(n) \
|
||||
(((n)->size_cells == -1) ? 1 : (n)->size_cells)
|
||||
|
||||
static void check_reg_format(struct check *c, struct node *dt,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
int addr_cells, size_cells, entrylen;
|
||||
|
||||
prop = get_property(node, "reg");
|
||||
if (!prop)
|
||||
return; /* No "reg", that's fine */
|
||||
|
||||
if (!node->parent) {
|
||||
FAIL(c, "Root node has a \"reg\" property");
|
||||
return;
|
||||
}
|
||||
|
||||
if (prop->val.len == 0)
|
||||
FAIL(c, "\"reg\" property in %s is empty", node->fullpath);
|
||||
|
||||
addr_cells = node_addr_cells(node->parent);
|
||||
size_cells = node_size_cells(node->parent);
|
||||
entrylen = (addr_cells + size_cells) * sizeof(cell_t);
|
||||
|
||||
if ((prop->val.len % entrylen) != 0)
|
||||
FAIL(c, "\"reg\" property in %s has invalid length (%d bytes) "
|
||||
"(#address-cells == %d, #size-cells == %d)",
|
||||
node->fullpath, prop->val.len, addr_cells, size_cells);
|
||||
}
|
||||
NODE_CHECK(reg_format, NULL, WARN, &addr_size_cells);
|
||||
|
||||
static void check_ranges_format(struct check *c, struct node *dt,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
int c_addr_cells, p_addr_cells, c_size_cells, p_size_cells, entrylen;
|
||||
|
||||
prop = get_property(node, "ranges");
|
||||
if (!prop)
|
||||
return;
|
||||
|
||||
if (!node->parent) {
|
||||
FAIL(c, "Root node has a \"ranges\" property");
|
||||
return;
|
||||
}
|
||||
|
||||
p_addr_cells = node_addr_cells(node->parent);
|
||||
p_size_cells = node_size_cells(node->parent);
|
||||
c_addr_cells = node_addr_cells(node);
|
||||
c_size_cells = node_size_cells(node);
|
||||
entrylen = (p_addr_cells + c_addr_cells + c_size_cells) * sizeof(cell_t);
|
||||
|
||||
if (prop->val.len == 0) {
|
||||
if (p_addr_cells != c_addr_cells)
|
||||
FAIL(c, "%s has empty \"ranges\" property but its "
|
||||
"#address-cells (%d) differs from %s (%d)",
|
||||
node->fullpath, c_addr_cells, node->parent->fullpath,
|
||||
p_addr_cells);
|
||||
if (p_size_cells != c_size_cells)
|
||||
FAIL(c, "%s has empty \"ranges\" property but its "
|
||||
"#size-cells (%d) differs from %s (%d)",
|
||||
node->fullpath, c_size_cells, node->parent->fullpath,
|
||||
p_size_cells);
|
||||
} else if ((prop->val.len % entrylen) != 0) {
|
||||
FAIL(c, "\"ranges\" property in %s has invalid length (%d bytes) "
|
||||
"(parent #address-cells == %d, child #address-cells == %d, "
|
||||
"#size-cells == %d)", node->fullpath, prop->val.len,
|
||||
p_addr_cells, c_addr_cells, c_size_cells);
|
||||
}
|
||||
}
|
||||
NODE_CHECK(ranges_format, NULL, WARN, &addr_size_cells);
|
||||
|
||||
/*
|
||||
* Style checks
|
||||
*/
|
||||
static void check_avoid_default_addr_size(struct check *c, struct node *dt,
|
||||
struct node *node)
|
||||
{
|
||||
struct property *reg, *ranges;
|
||||
|
||||
if (!node->parent)
|
||||
return; /* Ignore root node */
|
||||
|
||||
reg = get_property(node, "reg");
|
||||
ranges = get_property(node, "ranges");
|
||||
|
||||
if (!reg && !ranges)
|
||||
return;
|
||||
|
||||
if ((node->parent->addr_cells == -1))
|
||||
FAIL(c, "Relying on default #address-cells value for %s",
|
||||
node->fullpath);
|
||||
|
||||
if ((node->parent->size_cells == -1))
|
||||
FAIL(c, "Relying on default #size-cells value for %s",
|
||||
node->fullpath);
|
||||
}
|
||||
NODE_CHECK(avoid_default_addr_size, NULL, WARN, &addr_size_cells);
|
||||
|
||||
static void check_obsolete_chosen_interrupt_controller(struct check *c,
|
||||
struct node *dt)
|
||||
{
|
||||
struct node *chosen;
|
||||
struct property *prop;
|
||||
|
||||
chosen = get_node_by_path(dt, "/chosen");
|
||||
if (!chosen)
|
||||
return;
|
||||
|
||||
prop = get_property(chosen, "interrupt-controller");
|
||||
if (prop)
|
||||
FAIL(c, "/chosen has obsolete \"interrupt-controller\" "
|
||||
"property");
|
||||
}
|
||||
TREE_CHECK(obsolete_chosen_interrupt_controller, NULL, WARN);
|
||||
|
||||
static struct check *check_table[] = {
|
||||
&duplicate_node_names, &duplicate_property_names,
|
||||
&name_is_string, &name_properties,
|
||||
&explicit_phandles,
|
||||
&phandle_references, &path_references,
|
||||
|
||||
&address_cells_is_cell, &size_cells_is_cell, &interrupt_cells_is_cell,
|
||||
&device_type_is_string, &model_is_string, &status_is_string,
|
||||
|
||||
&addr_size_cells, ®_format, &ranges_format,
|
||||
|
||||
&avoid_default_addr_size,
|
||||
&obsolete_chosen_interrupt_controller,
|
||||
};
|
||||
|
||||
int check_semantics(struct node *dt, int outversion, int boot_cpuid_phys);
|
||||
|
||||
void process_checks(int force, struct boot_info *bi,
|
||||
int checkflag, int outversion, int boot_cpuid_phys)
|
||||
{
|
||||
struct node *dt = bi->dt;
|
||||
int i;
|
||||
int error = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(check_table); i++) {
|
||||
struct check *c = check_table[i];
|
||||
|
||||
if (c->level != IGNORE)
|
||||
error = error || run_check(c, dt);
|
||||
}
|
||||
|
||||
if (error) {
|
||||
if (!force) {
|
||||
fprintf(stderr, "ERROR: Input tree has errors, aborting "
|
||||
"(use -f to force output)\n");
|
||||
exit(2);
|
||||
} else if (quiet < 3) {
|
||||
fprintf(stderr, "Warning: Input tree has errors, "
|
||||
"output forced\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (checkflag) {
|
||||
if (error) {
|
||||
fprintf(stderr, "Warning: Skipping semantic checks due to structural errors\n");
|
||||
} else {
|
||||
if (!check_semantics(bi->dt, outversion,
|
||||
boot_cpuid_phys))
|
||||
fprintf(stderr, "Warning: Input tree has semantic errors\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Semantic check functions
|
||||
*/
|
||||
|
||||
#define ERRMSG(...) if (quiet < 2) fprintf(stderr, "ERROR: " __VA_ARGS__)
|
||||
#define WARNMSG(...) if (quiet < 1) fprintf(stderr, "Warning: " __VA_ARGS__)
|
||||
|
||||
#define DO_ERR(...) do {ERRMSG(__VA_ARGS__); ok = 0; } while (0)
|
||||
|
||||
#define CHECK_HAVE(node, propname) \
|
||||
do { \
|
||||
if (! (prop = get_property((node), (propname)))) \
|
||||
DO_ERR("Missing \"%s\" property in %s\n", (propname), \
|
||||
(node)->fullpath); \
|
||||
} while (0);
|
||||
|
||||
#define CHECK_HAVE_WARN(node, propname) \
|
||||
do { \
|
||||
if (! (prop = get_property((node), (propname)))) \
|
||||
WARNMSG("%s has no \"%s\" property\n", \
|
||||
(node)->fullpath, (propname)); \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_HAVE_STRING(node, propname) \
|
||||
do { \
|
||||
CHECK_HAVE((node), (propname)); \
|
||||
if (prop && !data_is_one_string(prop->val)) \
|
||||
DO_ERR("\"%s\" property in %s is not a string\n", \
|
||||
(propname), (node)->fullpath); \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_HAVE_STREQ(node, propname, value) \
|
||||
do { \
|
||||
CHECK_HAVE_STRING((node), (propname)); \
|
||||
if (prop && !streq(prop->val.val, (value))) \
|
||||
DO_ERR("%s has wrong %s, %s (should be %s\n", \
|
||||
(node)->fullpath, (propname), \
|
||||
prop->val.val, (value)); \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_HAVE_ONECELL(node, propname) \
|
||||
do { \
|
||||
CHECK_HAVE((node), (propname)); \
|
||||
if (prop && (prop->val.len != sizeof(cell_t))) \
|
||||
DO_ERR("\"%s\" property in %s has wrong size %d (should be 1 cell)\n", (propname), (node)->fullpath, prop->val.len); \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_HAVE_WARN_ONECELL(node, propname) \
|
||||
do { \
|
||||
CHECK_HAVE_WARN((node), (propname)); \
|
||||
if (prop && (prop->val.len != sizeof(cell_t))) \
|
||||
DO_ERR("\"%s\" property in %s has wrong size %d (should be 1 cell)\n", (propname), (node)->fullpath, prop->val.len); \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_HAVE_WARN_PHANDLE(xnode, propname, root) \
|
||||
do { \
|
||||
struct node *ref; \
|
||||
CHECK_HAVE_WARN_ONECELL((xnode), (propname)); \
|
||||
if (prop) {\
|
||||
cell_t phandle = propval_cell(prop); \
|
||||
if ((phandle == 0) || (phandle == -1)) { \
|
||||
DO_ERR("\"%s\" property in %s contains an invalid phandle %x\n", (propname), (xnode)->fullpath, phandle); \
|
||||
} else { \
|
||||
ref = get_node_by_phandle((root), propval_cell(prop)); \
|
||||
if (! ref) \
|
||||
DO_ERR("\"%s\" property in %s refers to non-existant phandle %x\n", (propname), (xnode)->fullpath, propval_cell(prop)); \
|
||||
} \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define CHECK_HAVE_WARN_STRING(node, propname) \
|
||||
do { \
|
||||
CHECK_HAVE_WARN((node), (propname)); \
|
||||
if (prop && !data_is_one_string(prop->val)) \
|
||||
DO_ERR("\"%s\" property in %s is not a string\n", \
|
||||
(propname), (node)->fullpath); \
|
||||
} while (0)
|
||||
|
||||
static int check_root(struct node *root)
|
||||
{
|
||||
struct property *prop;
|
||||
int ok = 1;
|
||||
|
||||
CHECK_HAVE_STRING(root, "model");
|
||||
CHECK_HAVE_WARN(root, "compatible");
|
||||
|
||||
return ok;
|
||||
}
|
||||
|
||||
static int check_cpus(struct node *root, int outversion, int boot_cpuid_phys)
|
||||
{
|
||||
struct node *cpus, *cpu;
|
||||
struct property *prop;
|
||||
struct node *bootcpu = NULL;
|
||||
int ok = 1;
|
||||
|
||||
cpus = get_subnode(root, "cpus");
|
||||
if (! cpus) {
|
||||
ERRMSG("Missing /cpus node\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (cpus->addr_cells != 1)
|
||||
DO_ERR("%s has bad #address-cells value %d (should be 1)\n",
|
||||
cpus->fullpath, cpus->addr_cells);
|
||||
if (cpus->size_cells != 0)
|
||||
DO_ERR("%s has bad #size-cells value %d (should be 0)\n",
|
||||
cpus->fullpath, cpus->size_cells);
|
||||
|
||||
for_each_child(cpus, cpu) {
|
||||
CHECK_HAVE_STREQ(cpu, "device_type", "cpu");
|
||||
|
||||
CHECK_HAVE_ONECELL(cpu, "reg");
|
||||
if (prop) {
|
||||
cell_t unitnum;
|
||||
char *eptr;
|
||||
|
||||
unitnum = strtol(get_unitname(cpu), &eptr, 16);
|
||||
if (*eptr) {
|
||||
WARNMSG("%s has bad format unit name %s (should be CPU number\n",
|
||||
cpu->fullpath, get_unitname(cpu));
|
||||
} else if (unitnum != propval_cell(prop)) {
|
||||
WARNMSG("%s unit name \"%s\" does not match \"reg\" property <%x>\n",
|
||||
cpu->fullpath, get_unitname(cpu),
|
||||
propval_cell(prop));
|
||||
}
|
||||
}
|
||||
|
||||
/* CHECK_HAVE_ONECELL(cpu, "d-cache-line-size"); */
|
||||
/* CHECK_HAVE_ONECELL(cpu, "i-cache-line-size"); */
|
||||
CHECK_HAVE_ONECELL(cpu, "d-cache-size");
|
||||
CHECK_HAVE_ONECELL(cpu, "i-cache-size");
|
||||
|
||||
CHECK_HAVE_WARN_ONECELL(cpu, "clock-frequency");
|
||||
CHECK_HAVE_WARN_ONECELL(cpu, "timebase-frequency");
|
||||
|
||||
prop = get_property(cpu, "linux,boot-cpu");
|
||||
if (prop) {
|
||||
if (prop->val.len)
|
||||
WARNMSG("\"linux,boot-cpu\" property in %s is non-empty\n",
|
||||
cpu->fullpath);
|
||||
if (bootcpu)
|
||||
DO_ERR("Multiple boot cpus (%s and %s)\n",
|
||||
bootcpu->fullpath, cpu->fullpath);
|
||||
else
|
||||
bootcpu = cpu;
|
||||
}
|
||||
}
|
||||
|
||||
if (outversion < 2) {
|
||||
if (! bootcpu)
|
||||
WARNMSG("No cpu has \"linux,boot-cpu\" property\n");
|
||||
} else {
|
||||
if (bootcpu)
|
||||
WARNMSG("\"linux,boot-cpu\" property is deprecated in blob version 2 or higher\n");
|
||||
if (boot_cpuid_phys == 0xfeedbeef)
|
||||
WARNMSG("physical boot CPU not set. Use -b option to set\n");
|
||||
}
|
||||
|
||||
return ok;
|
||||
}
|
||||
|
||||
static int check_memory(struct node *root)
|
||||
{
|
||||
struct node *mem;
|
||||
struct property *prop;
|
||||
int nnodes = 0;
|
||||
int ok = 1;
|
||||
|
||||
for_each_child(root, mem) {
|
||||
if (! strneq(mem->name, "memory", mem->basenamelen))
|
||||
continue;
|
||||
|
||||
nnodes++;
|
||||
|
||||
CHECK_HAVE_STREQ(mem, "device_type", "memory");
|
||||
CHECK_HAVE(mem, "reg");
|
||||
}
|
||||
|
||||
if (nnodes == 0) {
|
||||
ERRMSG("No memory nodes\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ok;
|
||||
}
|
||||
|
||||
int check_semantics(struct node *dt, int outversion, int boot_cpuid_phys)
|
||||
{
|
||||
int ok = 1;
|
||||
|
||||
ok = ok && check_root(dt);
|
||||
ok = ok && check_cpus(dt, outversion, boot_cpuid_phys);
|
||||
ok = ok && check_memory(dt);
|
||||
if (! ok)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
321
arch/powerpc/boot/dtc-src/data.c
Normal file
321
arch/powerpc/boot/dtc-src/data.c
Normal file
|
|
@ -0,0 +1,321 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "dtc.h"
|
||||
|
||||
void data_free(struct data d)
|
||||
{
|
||||
struct marker *m, *nm;
|
||||
|
||||
m = d.markers;
|
||||
while (m) {
|
||||
nm = m->next;
|
||||
free(m->ref);
|
||||
free(m);
|
||||
m = nm;
|
||||
}
|
||||
|
||||
assert(!d.val || d.asize);
|
||||
|
||||
if (d.val)
|
||||
free(d.val);
|
||||
}
|
||||
|
||||
struct data data_grow_for(struct data d, int xlen)
|
||||
{
|
||||
struct data nd;
|
||||
int newsize;
|
||||
|
||||
/* we must start with an allocated datum */
|
||||
assert(!d.val || d.asize);
|
||||
|
||||
if (xlen == 0)
|
||||
return d;
|
||||
|
||||
nd = d;
|
||||
|
||||
newsize = xlen;
|
||||
|
||||
while ((d.len + xlen) > newsize)
|
||||
newsize *= 2;
|
||||
|
||||
nd.asize = newsize;
|
||||
nd.val = xrealloc(d.val, newsize);
|
||||
|
||||
assert(nd.asize >= (d.len + xlen));
|
||||
|
||||
return nd;
|
||||
}
|
||||
|
||||
struct data data_copy_mem(const char *mem, int len)
|
||||
{
|
||||
struct data d;
|
||||
|
||||
d = data_grow_for(empty_data, len);
|
||||
|
||||
d.len = len;
|
||||
memcpy(d.val, mem, len);
|
||||
|
||||
return d;
|
||||
}
|
||||
|
||||
static char get_oct_char(const char *s, int *i)
|
||||
{
|
||||
char x[4];
|
||||
char *endx;
|
||||
long val;
|
||||
|
||||
x[3] = '\0';
|
||||
x[0] = s[(*i)];
|
||||
if (x[0]) {
|
||||
x[1] = s[(*i)+1];
|
||||
if (x[1])
|
||||
x[2] = s[(*i)+2];
|
||||
}
|
||||
|
||||
val = strtol(x, &endx, 8);
|
||||
if ((endx - x) == 0)
|
||||
fprintf(stderr, "Empty \\nnn escape\n");
|
||||
|
||||
(*i) += endx - x;
|
||||
return val;
|
||||
}
|
||||
|
||||
static char get_hex_char(const char *s, int *i)
|
||||
{
|
||||
char x[3];
|
||||
char *endx;
|
||||
long val;
|
||||
|
||||
x[2] = '\0';
|
||||
x[0] = s[(*i)];
|
||||
if (x[0])
|
||||
x[1] = s[(*i)+1];
|
||||
|
||||
val = strtol(x, &endx, 16);
|
||||
if ((endx - x) == 0)
|
||||
fprintf(stderr, "Empty \\x escape\n");
|
||||
|
||||
(*i) += endx - x;
|
||||
return val;
|
||||
}
|
||||
|
||||
struct data data_copy_escape_string(const char *s, int len)
|
||||
{
|
||||
int i = 0;
|
||||
struct data d;
|
||||
char *q;
|
||||
|
||||
d = data_grow_for(empty_data, strlen(s)+1);
|
||||
|
||||
q = d.val;
|
||||
while (i < len) {
|
||||
char c = s[i++];
|
||||
|
||||
if (c != '\\') {
|
||||
q[d.len++] = c;
|
||||
continue;
|
||||
}
|
||||
|
||||
c = s[i++];
|
||||
assert(c);
|
||||
switch (c) {
|
||||
case 'a':
|
||||
q[d.len++] = '\a';
|
||||
break;
|
||||
case 'b':
|
||||
q[d.len++] = '\b';
|
||||
break;
|
||||
case 't':
|
||||
q[d.len++] = '\t';
|
||||
break;
|
||||
case 'n':
|
||||
q[d.len++] = '\n';
|
||||
break;
|
||||
case 'v':
|
||||
q[d.len++] = '\v';
|
||||
break;
|
||||
case 'f':
|
||||
q[d.len++] = '\f';
|
||||
break;
|
||||
case 'r':
|
||||
q[d.len++] = '\r';
|
||||
break;
|
||||
case '0':
|
||||
case '1':
|
||||
case '2':
|
||||
case '3':
|
||||
case '4':
|
||||
case '5':
|
||||
case '6':
|
||||
case '7':
|
||||
i--; /* need to re-read the first digit as
|
||||
* part of the octal value */
|
||||
q[d.len++] = get_oct_char(s, &i);
|
||||
break;
|
||||
case 'x':
|
||||
q[d.len++] = get_hex_char(s, &i);
|
||||
break;
|
||||
default:
|
||||
q[d.len++] = c;
|
||||
}
|
||||
}
|
||||
|
||||
q[d.len++] = '\0';
|
||||
return d;
|
||||
}
|
||||
|
||||
struct data data_copy_file(FILE *f, size_t len)
|
||||
{
|
||||
struct data d;
|
||||
|
||||
d = data_grow_for(empty_data, len);
|
||||
|
||||
d.len = len;
|
||||
fread(d.val, len, 1, f);
|
||||
|
||||
return d;
|
||||
}
|
||||
|
||||
struct data data_append_data(struct data d, const void *p, int len)
|
||||
{
|
||||
d = data_grow_for(d, len);
|
||||
memcpy(d.val + d.len, p, len);
|
||||
d.len += len;
|
||||
return d;
|
||||
}
|
||||
|
||||
struct data data_insert_at_marker(struct data d, struct marker *m,
|
||||
const void *p, int len)
|
||||
{
|
||||
d = data_grow_for(d, len);
|
||||
memmove(d.val + m->offset + len, d.val + m->offset, d.len - m->offset);
|
||||
memcpy(d.val + m->offset, p, len);
|
||||
d.len += len;
|
||||
|
||||
/* Adjust all markers after the one we're inserting at */
|
||||
m = m->next;
|
||||
for_each_marker(m)
|
||||
m->offset += len;
|
||||
return d;
|
||||
}
|
||||
|
||||
struct data data_append_markers(struct data d, struct marker *m)
|
||||
{
|
||||
struct marker **mp = &d.markers;
|
||||
|
||||
/* Find the end of the markerlist */
|
||||
while (*mp)
|
||||
mp = &((*mp)->next);
|
||||
*mp = m;
|
||||
return d;
|
||||
}
|
||||
|
||||
struct data data_merge(struct data d1, struct data d2)
|
||||
{
|
||||
struct data d;
|
||||
struct marker *m2 = d2.markers;
|
||||
|
||||
d = data_append_markers(data_append_data(d1, d2.val, d2.len), m2);
|
||||
|
||||
/* Adjust for the length of d1 */
|
||||
for_each_marker(m2)
|
||||
m2->offset += d1.len;
|
||||
|
||||
d2.markers = NULL; /* So data_free() doesn't clobber them */
|
||||
data_free(d2);
|
||||
|
||||
return d;
|
||||
}
|
||||
|
||||
struct data data_append_cell(struct data d, cell_t word)
|
||||
{
|
||||
cell_t beword = cpu_to_be32(word);
|
||||
|
||||
return data_append_data(d, &beword, sizeof(beword));
|
||||
}
|
||||
|
||||
struct data data_append_re(struct data d, const struct fdt_reserve_entry *re)
|
||||
{
|
||||
struct fdt_reserve_entry bere;
|
||||
|
||||
bere.address = cpu_to_be64(re->address);
|
||||
bere.size = cpu_to_be64(re->size);
|
||||
|
||||
return data_append_data(d, &bere, sizeof(bere));
|
||||
}
|
||||
|
||||
struct data data_append_addr(struct data d, u64 addr)
|
||||
{
|
||||
u64 beaddr = cpu_to_be64(addr);
|
||||
|
||||
return data_append_data(d, &beaddr, sizeof(beaddr));
|
||||
}
|
||||
|
||||
struct data data_append_byte(struct data d, uint8_t byte)
|
||||
{
|
||||
return data_append_data(d, &byte, 1);
|
||||
}
|
||||
|
||||
struct data data_append_zeroes(struct data d, int len)
|
||||
{
|
||||
d = data_grow_for(d, len);
|
||||
|
||||
memset(d.val + d.len, 0, len);
|
||||
d.len += len;
|
||||
return d;
|
||||
}
|
||||
|
||||
struct data data_append_align(struct data d, int align)
|
||||
{
|
||||
int newlen = ALIGN(d.len, align);
|
||||
return data_append_zeroes(d, newlen - d.len);
|
||||
}
|
||||
|
||||
struct data data_add_marker(struct data d, enum markertype type, char *ref)
|
||||
{
|
||||
struct marker *m;
|
||||
|
||||
m = xmalloc(sizeof(*m));
|
||||
m->offset = d.len;
|
||||
m->type = type;
|
||||
m->ref = ref;
|
||||
m->next = NULL;
|
||||
|
||||
return data_append_markers(d, m);
|
||||
}
|
||||
|
||||
int data_is_one_string(struct data d)
|
||||
{
|
||||
int i;
|
||||
int len = d.len;
|
||||
|
||||
if (len == 0)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < len-1; i++)
|
||||
if (d.val[i] == '\0')
|
||||
return 0;
|
||||
|
||||
if (d.val[len-1] != '\0')
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
328
arch/powerpc/boot/dtc-src/dtc-lexer.l
Normal file
328
arch/powerpc/boot/dtc-src/dtc-lexer.l
Normal file
|
|
@ -0,0 +1,328 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
%option noyywrap nounput yylineno
|
||||
|
||||
%x INCLUDE
|
||||
%x BYTESTRING
|
||||
%x PROPNODENAME
|
||||
%s V1
|
||||
|
||||
PROPNODECHAR [a-zA-Z0-9,._+*#?@-]
|
||||
PATHCHAR ({PROPNODECHAR}|[/])
|
||||
LABEL [a-zA-Z_][a-zA-Z0-9_]*
|
||||
|
||||
%{
|
||||
#include "dtc.h"
|
||||
#include "srcpos.h"
|
||||
#include "dtc-parser.tab.h"
|
||||
|
||||
|
||||
/*#define LEXDEBUG 1*/
|
||||
|
||||
#ifdef LEXDEBUG
|
||||
#define DPRINT(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__)
|
||||
#else
|
||||
#define DPRINT(fmt, ...) do { } while (0)
|
||||
#endif
|
||||
|
||||
static int dts_version; /* = 0 */
|
||||
|
||||
#define BEGIN_DEFAULT() if (dts_version == 0) { \
|
||||
DPRINT("<INITIAL>\n"); \
|
||||
BEGIN(INITIAL); \
|
||||
} else { \
|
||||
DPRINT("<V1>\n"); \
|
||||
BEGIN(V1); \
|
||||
}
|
||||
%}
|
||||
|
||||
%%
|
||||
<*>"/include/" BEGIN(INCLUDE);
|
||||
|
||||
<INCLUDE>\"[^"\n]*\" {
|
||||
yytext[strlen(yytext) - 1] = 0;
|
||||
if (!push_input_file(yytext + 1)) {
|
||||
/* Some unrecoverable error.*/
|
||||
exit(1);
|
||||
}
|
||||
BEGIN_DEFAULT();
|
||||
}
|
||||
|
||||
|
||||
<*><<EOF>> {
|
||||
if (!pop_input_file()) {
|
||||
yyterminate();
|
||||
}
|
||||
}
|
||||
|
||||
<*>\"([^\\"]|\\.)*\" {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("String: %s\n", yytext);
|
||||
yylval.data = data_copy_escape_string(yytext+1,
|
||||
yyleng-2);
|
||||
yylloc.first_line = yylineno;
|
||||
return DT_STRING;
|
||||
}
|
||||
|
||||
<*>"/dts-v1/" {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("Keyword: /dts-v1/\n");
|
||||
dts_version = 1;
|
||||
BEGIN_DEFAULT();
|
||||
return DT_V1;
|
||||
}
|
||||
|
||||
<*>"/memreserve/" {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("Keyword: /memreserve/\n");
|
||||
BEGIN_DEFAULT();
|
||||
return DT_MEMRESERVE;
|
||||
}
|
||||
|
||||
<*>{LABEL}: {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("Label: %s\n", yytext);
|
||||
yylval.labelref = strdup(yytext);
|
||||
yylval.labelref[yyleng-1] = '\0';
|
||||
return DT_LABEL;
|
||||
}
|
||||
|
||||
<INITIAL>[bodh]# {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
if (*yytext == 'b')
|
||||
yylval.cbase = 2;
|
||||
else if (*yytext == 'o')
|
||||
yylval.cbase = 8;
|
||||
else if (*yytext == 'd')
|
||||
yylval.cbase = 10;
|
||||
else
|
||||
yylval.cbase = 16;
|
||||
DPRINT("Base: %d\n", yylval.cbase);
|
||||
return DT_BASE;
|
||||
}
|
||||
|
||||
<INITIAL>[0-9a-fA-F]+ {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
yylval.literal = strdup(yytext);
|
||||
DPRINT("Literal: '%s'\n", yylval.literal);
|
||||
return DT_LEGACYLITERAL;
|
||||
}
|
||||
|
||||
<V1>[0-9]+|0[xX][0-9a-fA-F]+ {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
yylval.literal = strdup(yytext);
|
||||
DPRINT("Literal: '%s'\n", yylval.literal);
|
||||
return DT_LITERAL;
|
||||
}
|
||||
|
||||
\&{LABEL} { /* label reference */
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("Ref: %s\n", yytext+1);
|
||||
yylval.labelref = strdup(yytext+1);
|
||||
return DT_REF;
|
||||
}
|
||||
|
||||
"&{/"{PATHCHAR}+\} { /* new-style path reference */
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
yytext[yyleng-1] = '\0';
|
||||
DPRINT("Ref: %s\n", yytext+2);
|
||||
yylval.labelref = strdup(yytext+2);
|
||||
return DT_REF;
|
||||
}
|
||||
|
||||
<INITIAL>"&/"{PATHCHAR}+ { /* old-style path reference */
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("Ref: %s\n", yytext+1);
|
||||
yylval.labelref = strdup(yytext+1);
|
||||
return DT_REF;
|
||||
}
|
||||
|
||||
<BYTESTRING>[0-9a-fA-F]{2} {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
yylval.byte = strtol(yytext, NULL, 16);
|
||||
DPRINT("Byte: %02x\n", (int)yylval.byte);
|
||||
return DT_BYTE;
|
||||
}
|
||||
|
||||
<BYTESTRING>"]" {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("/BYTESTRING\n");
|
||||
BEGIN_DEFAULT();
|
||||
return ']';
|
||||
}
|
||||
|
||||
<PROPNODENAME>{PROPNODECHAR}+ {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("PropNodeName: %s\n", yytext);
|
||||
yylval.propnodename = strdup(yytext);
|
||||
BEGIN_DEFAULT();
|
||||
return DT_PROPNODENAME;
|
||||
}
|
||||
|
||||
|
||||
<*>[[:space:]]+ /* eat whitespace */
|
||||
|
||||
<*>"/*"([^*]|\*+[^*/])*\*+"/" {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("Comment: %s\n", yytext);
|
||||
/* eat comments */
|
||||
}
|
||||
|
||||
<*>"//".*\n /* eat line comments */
|
||||
|
||||
<*>. {
|
||||
yylloc.filenum = srcpos_filenum;
|
||||
yylloc.first_line = yylineno;
|
||||
DPRINT("Char: %c (\\x%02x)\n", yytext[0],
|
||||
(unsigned)yytext[0]);
|
||||
if (yytext[0] == '[') {
|
||||
DPRINT("<BYTESTRING>\n");
|
||||
BEGIN(BYTESTRING);
|
||||
}
|
||||
if ((yytext[0] == '{')
|
||||
|| (yytext[0] == ';')) {
|
||||
DPRINT("<PROPNODENAME>\n");
|
||||
BEGIN(PROPNODENAME);
|
||||
}
|
||||
return yytext[0];
|
||||
}
|
||||
|
||||
%%
|
||||
|
||||
|
||||
/*
|
||||
* Stack of nested include file contexts.
|
||||
*/
|
||||
|
||||
struct incl_file {
|
||||
int filenum;
|
||||
FILE *file;
|
||||
YY_BUFFER_STATE yy_prev_buf;
|
||||
int yy_prev_lineno;
|
||||
struct incl_file *prev;
|
||||
};
|
||||
|
||||
struct incl_file *incl_file_stack;
|
||||
|
||||
|
||||
/*
|
||||
* Detect infinite include recursion.
|
||||
*/
|
||||
#define MAX_INCLUDE_DEPTH (100)
|
||||
|
||||
static int incl_depth = 0;
|
||||
|
||||
|
||||
int push_input_file(const char *filename)
|
||||
{
|
||||
FILE *f;
|
||||
struct incl_file *incl_file;
|
||||
|
||||
if (!filename) {
|
||||
yyerror("No include file name given.");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (incl_depth++ >= MAX_INCLUDE_DEPTH) {
|
||||
yyerror("Includes nested too deeply");
|
||||
return 0;
|
||||
}
|
||||
|
||||
f = dtc_open_file(filename);
|
||||
|
||||
incl_file = malloc(sizeof(struct incl_file));
|
||||
if (!incl_file) {
|
||||
yyerror("Can not allocate include file space.");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Save current context.
|
||||
*/
|
||||
incl_file->yy_prev_buf = YY_CURRENT_BUFFER;
|
||||
incl_file->yy_prev_lineno = yylineno;
|
||||
incl_file->filenum = srcpos_filenum;
|
||||
incl_file->file = yyin;
|
||||
incl_file->prev = incl_file_stack;
|
||||
|
||||
incl_file_stack = incl_file;
|
||||
|
||||
/*
|
||||
* Establish new context.
|
||||
*/
|
||||
srcpos_filenum = lookup_file_name(filename, 0);
|
||||
yylineno = 1;
|
||||
yyin = f;
|
||||
yy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int pop_input_file(void)
|
||||
{
|
||||
struct incl_file *incl_file;
|
||||
|
||||
if (incl_file_stack == 0)
|
||||
return 0;
|
||||
|
||||
fclose(yyin);
|
||||
|
||||
/*
|
||||
* Pop.
|
||||
*/
|
||||
--incl_depth;
|
||||
incl_file = incl_file_stack;
|
||||
incl_file_stack = incl_file->prev;
|
||||
|
||||
/*
|
||||
* Recover old context.
|
||||
*/
|
||||
yy_delete_buffer(YY_CURRENT_BUFFER);
|
||||
yy_switch_to_buffer(incl_file->yy_prev_buf);
|
||||
yylineno = incl_file->yy_prev_lineno;
|
||||
srcpos_filenum = incl_file->filenum;
|
||||
yyin = incl_file->file;
|
||||
|
||||
/*
|
||||
* Free old state.
|
||||
*/
|
||||
free(incl_file);
|
||||
|
||||
if (YY_CURRENT_BUFFER == 0)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
2174
arch/powerpc/boot/dtc-src/dtc-lexer.lex.c_shipped
Normal file
2174
arch/powerpc/boot/dtc-src/dtc-lexer.lex.c_shipped
Normal file
File diff suppressed because it is too large
Load diff
1983
arch/powerpc/boot/dtc-src/dtc-parser.tab.c_shipped
Normal file
1983
arch/powerpc/boot/dtc-src/dtc-parser.tab.c_shipped
Normal file
File diff suppressed because it is too large
Load diff
111
arch/powerpc/boot/dtc-src/dtc-parser.tab.h_shipped
Normal file
111
arch/powerpc/boot/dtc-src/dtc-parser.tab.h_shipped
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* A Bison parser, made by GNU Bison 2.3. */
|
||||
|
||||
/* Skeleton interface for Bison's Yacc-like parsers in C
|
||||
|
||||
Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
Boston, MA 02110-1301, USA. */
|
||||
|
||||
/* As a special exception, you may create a larger work that contains
|
||||
part or all of the Bison parser skeleton and distribute that work
|
||||
under terms of your choice, so long as that work isn't itself a
|
||||
parser generator using the skeleton or a modified version thereof
|
||||
as a parser skeleton. Alternatively, if you modify or redistribute
|
||||
the parser skeleton itself, you may (at your option) remove this
|
||||
special exception, which will cause the skeleton and the resulting
|
||||
Bison output files to be licensed under the GNU General Public
|
||||
License without this special exception.
|
||||
|
||||
This special exception was added by the Free Software Foundation in
|
||||
version 2.2 of Bison. */
|
||||
|
||||
/* Tokens. */
|
||||
#ifndef YYTOKENTYPE
|
||||
# define YYTOKENTYPE
|
||||
/* Put the tokens into the symbol table, so that GDB and other debuggers
|
||||
know about them. */
|
||||
enum yytokentype {
|
||||
DT_V1 = 258,
|
||||
DT_MEMRESERVE = 259,
|
||||
DT_PROPNODENAME = 260,
|
||||
DT_LITERAL = 261,
|
||||
DT_LEGACYLITERAL = 262,
|
||||
DT_BASE = 263,
|
||||
DT_BYTE = 264,
|
||||
DT_STRING = 265,
|
||||
DT_LABEL = 266,
|
||||
DT_REF = 267
|
||||
};
|
||||
#endif
|
||||
/* Tokens. */
|
||||
#define DT_V1 258
|
||||
#define DT_MEMRESERVE 259
|
||||
#define DT_PROPNODENAME 260
|
||||
#define DT_LITERAL 261
|
||||
#define DT_LEGACYLITERAL 262
|
||||
#define DT_BASE 263
|
||||
#define DT_BYTE 264
|
||||
#define DT_STRING 265
|
||||
#define DT_LABEL 266
|
||||
#define DT_REF 267
|
||||
|
||||
|
||||
|
||||
|
||||
#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
|
||||
typedef union YYSTYPE
|
||||
#line 34 "dtc-parser.y"
|
||||
{
|
||||
char *propnodename;
|
||||
char *literal;
|
||||
char *labelref;
|
||||
unsigned int cbase;
|
||||
u8 byte;
|
||||
struct data data;
|
||||
|
||||
u64 addr;
|
||||
cell_t cell;
|
||||
struct property *prop;
|
||||
struct property *proplist;
|
||||
struct node *node;
|
||||
struct node *nodelist;
|
||||
struct reserve_info *re;
|
||||
}
|
||||
/* Line 1489 of yacc.c. */
|
||||
#line 90 "dtc-parser.tab.h"
|
||||
YYSTYPE;
|
||||
# define yystype YYSTYPE /* obsolescent; will be withdrawn */
|
||||
# define YYSTYPE_IS_DECLARED 1
|
||||
# define YYSTYPE_IS_TRIVIAL 1
|
||||
#endif
|
||||
|
||||
extern YYSTYPE yylval;
|
||||
|
||||
#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED
|
||||
typedef struct YYLTYPE
|
||||
{
|
||||
int first_line;
|
||||
int first_column;
|
||||
int last_line;
|
||||
int last_column;
|
||||
} YYLTYPE;
|
||||
# define yyltype YYLTYPE /* obsolescent; will be withdrawn */
|
||||
# define YYLTYPE_IS_DECLARED 1
|
||||
# define YYLTYPE_IS_TRIVIAL 1
|
||||
#endif
|
||||
|
||||
extern YYLTYPE yylloc;
|
||||
336
arch/powerpc/boot/dtc-src/dtc-parser.y
Normal file
336
arch/powerpc/boot/dtc-src/dtc-parser.y
Normal file
|
|
@ -0,0 +1,336 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
%locations
|
||||
|
||||
%{
|
||||
#include "dtc.h"
|
||||
#include "srcpos.h"
|
||||
|
||||
int yylex(void);
|
||||
unsigned long long eval_literal(const char *s, int base, int bits);
|
||||
|
||||
extern struct boot_info *the_boot_info;
|
||||
|
||||
%}
|
||||
|
||||
%union {
|
||||
char *propnodename;
|
||||
char *literal;
|
||||
char *labelref;
|
||||
unsigned int cbase;
|
||||
u8 byte;
|
||||
struct data data;
|
||||
|
||||
u64 addr;
|
||||
cell_t cell;
|
||||
struct property *prop;
|
||||
struct property *proplist;
|
||||
struct node *node;
|
||||
struct node *nodelist;
|
||||
struct reserve_info *re;
|
||||
}
|
||||
|
||||
%token DT_V1
|
||||
%token DT_MEMRESERVE
|
||||
%token <propnodename> DT_PROPNODENAME
|
||||
%token <literal> DT_LITERAL
|
||||
%token <literal> DT_LEGACYLITERAL
|
||||
%token <cbase> DT_BASE
|
||||
%token <byte> DT_BYTE
|
||||
%token <data> DT_STRING
|
||||
%token <labelref> DT_LABEL
|
||||
%token <labelref> DT_REF
|
||||
|
||||
%type <data> propdata
|
||||
%type <data> propdataprefix
|
||||
%type <re> memreserve
|
||||
%type <re> memreserves
|
||||
%type <re> v0_memreserve
|
||||
%type <re> v0_memreserves
|
||||
%type <addr> addr
|
||||
%type <data> celllist
|
||||
%type <cbase> cellbase
|
||||
%type <cell> cellval
|
||||
%type <data> bytestring
|
||||
%type <prop> propdef
|
||||
%type <proplist> proplist
|
||||
|
||||
%type <node> devicetree
|
||||
%type <node> nodedef
|
||||
%type <node> subnode
|
||||
%type <nodelist> subnodes
|
||||
%type <labelref> label
|
||||
|
||||
%%
|
||||
|
||||
sourcefile:
|
||||
DT_V1 ';' memreserves devicetree
|
||||
{
|
||||
the_boot_info = build_boot_info($3, $4);
|
||||
}
|
||||
| v0_memreserves devicetree
|
||||
{
|
||||
the_boot_info = build_boot_info($1, $2);
|
||||
}
|
||||
;
|
||||
|
||||
memreserves:
|
||||
/* empty */
|
||||
{
|
||||
$$ = NULL;
|
||||
}
|
||||
| memreserve memreserves
|
||||
{
|
||||
$$ = chain_reserve_entry($1, $2);
|
||||
}
|
||||
;
|
||||
|
||||
memreserve:
|
||||
label DT_MEMRESERVE addr addr ';'
|
||||
{
|
||||
$$ = build_reserve_entry($3, $4, $1);
|
||||
}
|
||||
;
|
||||
|
||||
v0_memreserves:
|
||||
/* empty */
|
||||
{
|
||||
$$ = NULL;
|
||||
}
|
||||
| v0_memreserve v0_memreserves
|
||||
{
|
||||
$$ = chain_reserve_entry($1, $2);
|
||||
};
|
||||
;
|
||||
|
||||
v0_memreserve:
|
||||
memreserve
|
||||
{
|
||||
$$ = $1;
|
||||
}
|
||||
| label DT_MEMRESERVE addr '-' addr ';'
|
||||
{
|
||||
$$ = build_reserve_entry($3, $5 - $3 + 1, $1);
|
||||
}
|
||||
;
|
||||
|
||||
addr:
|
||||
DT_LITERAL
|
||||
{
|
||||
$$ = eval_literal($1, 0, 64);
|
||||
}
|
||||
| DT_LEGACYLITERAL
|
||||
{
|
||||
$$ = eval_literal($1, 16, 64);
|
||||
}
|
||||
;
|
||||
|
||||
devicetree:
|
||||
'/' nodedef
|
||||
{
|
||||
$$ = name_node($2, "", NULL);
|
||||
}
|
||||
;
|
||||
|
||||
nodedef:
|
||||
'{' proplist subnodes '}' ';'
|
||||
{
|
||||
$$ = build_node($2, $3);
|
||||
}
|
||||
;
|
||||
|
||||
proplist:
|
||||
/* empty */
|
||||
{
|
||||
$$ = NULL;
|
||||
}
|
||||
| proplist propdef
|
||||
{
|
||||
$$ = chain_property($2, $1);
|
||||
}
|
||||
;
|
||||
|
||||
propdef:
|
||||
label DT_PROPNODENAME '=' propdata ';'
|
||||
{
|
||||
$$ = build_property($2, $4, $1);
|
||||
}
|
||||
| label DT_PROPNODENAME ';'
|
||||
{
|
||||
$$ = build_property($2, empty_data, $1);
|
||||
}
|
||||
;
|
||||
|
||||
propdata:
|
||||
propdataprefix DT_STRING
|
||||
{
|
||||
$$ = data_merge($1, $2);
|
||||
}
|
||||
| propdataprefix '<' celllist '>'
|
||||
{
|
||||
$$ = data_merge($1, $3);
|
||||
}
|
||||
| propdataprefix '[' bytestring ']'
|
||||
{
|
||||
$$ = data_merge($1, $3);
|
||||
}
|
||||
| propdataprefix DT_REF
|
||||
{
|
||||
$$ = data_add_marker($1, REF_PATH, $2);
|
||||
}
|
||||
| propdata DT_LABEL
|
||||
{
|
||||
$$ = data_add_marker($1, LABEL, $2);
|
||||
}
|
||||
;
|
||||
|
||||
propdataprefix:
|
||||
/* empty */
|
||||
{
|
||||
$$ = empty_data;
|
||||
}
|
||||
| propdata ','
|
||||
{
|
||||
$$ = $1;
|
||||
}
|
||||
| propdataprefix DT_LABEL
|
||||
{
|
||||
$$ = data_add_marker($1, LABEL, $2);
|
||||
}
|
||||
;
|
||||
|
||||
celllist:
|
||||
/* empty */
|
||||
{
|
||||
$$ = empty_data;
|
||||
}
|
||||
| celllist cellval
|
||||
{
|
||||
$$ = data_append_cell($1, $2);
|
||||
}
|
||||
| celllist DT_REF
|
||||
{
|
||||
$$ = data_append_cell(data_add_marker($1, REF_PHANDLE,
|
||||
$2), -1);
|
||||
}
|
||||
| celllist DT_LABEL
|
||||
{
|
||||
$$ = data_add_marker($1, LABEL, $2);
|
||||
}
|
||||
;
|
||||
|
||||
cellbase:
|
||||
/* empty */
|
||||
{
|
||||
$$ = 16;
|
||||
}
|
||||
| DT_BASE
|
||||
;
|
||||
|
||||
cellval:
|
||||
DT_LITERAL
|
||||
{
|
||||
$$ = eval_literal($1, 0, 32);
|
||||
}
|
||||
| cellbase DT_LEGACYLITERAL
|
||||
{
|
||||
$$ = eval_literal($2, $1, 32);
|
||||
}
|
||||
;
|
||||
|
||||
bytestring:
|
||||
/* empty */
|
||||
{
|
||||
$$ = empty_data;
|
||||
}
|
||||
| bytestring DT_BYTE
|
||||
{
|
||||
$$ = data_append_byte($1, $2);
|
||||
}
|
||||
| bytestring DT_LABEL
|
||||
{
|
||||
$$ = data_add_marker($1, LABEL, $2);
|
||||
}
|
||||
;
|
||||
|
||||
subnodes:
|
||||
/* empty */
|
||||
{
|
||||
$$ = NULL;
|
||||
}
|
||||
| subnode subnodes
|
||||
{
|
||||
$$ = chain_node($1, $2);
|
||||
}
|
||||
| subnode propdef
|
||||
{
|
||||
yyerror("syntax error: properties must precede subnodes\n");
|
||||
YYERROR;
|
||||
}
|
||||
;
|
||||
|
||||
subnode:
|
||||
label DT_PROPNODENAME nodedef
|
||||
{
|
||||
$$ = name_node($3, $2, $1);
|
||||
}
|
||||
;
|
||||
|
||||
label:
|
||||
/* empty */
|
||||
{
|
||||
$$ = NULL;
|
||||
}
|
||||
| DT_LABEL
|
||||
{
|
||||
$$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
%%
|
||||
|
||||
void yyerror (char const *s)
|
||||
{
|
||||
const char *fname = srcpos_filename_for_num(yylloc.filenum);
|
||||
|
||||
if (strcmp(fname, "-") == 0)
|
||||
fname = "stdin";
|
||||
|
||||
fprintf(stderr, "%s:%d %s\n",
|
||||
fname, yylloc.first_line, s);
|
||||
}
|
||||
|
||||
unsigned long long eval_literal(const char *s, int base, int bits)
|
||||
{
|
||||
unsigned long long val;
|
||||
char *e;
|
||||
|
||||
errno = 0;
|
||||
val = strtoull(s, &e, base);
|
||||
if (*e)
|
||||
yyerror("bad characters in literal");
|
||||
else if ((errno == ERANGE)
|
||||
|| ((bits < 64) && (val >= (1ULL << bits))))
|
||||
yyerror("literal out of range");
|
||||
else if (errno != 0)
|
||||
yyerror("bad literal");
|
||||
return val;
|
||||
}
|
||||
231
arch/powerpc/boot/dtc-src/dtc.c
Normal file
231
arch/powerpc/boot/dtc-src/dtc.c
Normal file
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "dtc.h"
|
||||
#include "srcpos.h"
|
||||
|
||||
#include "version_gen.h"
|
||||
|
||||
/*
|
||||
* Command line options
|
||||
*/
|
||||
int quiet; /* Level of quietness */
|
||||
int reservenum; /* Number of memory reservation slots */
|
||||
int minsize; /* Minimum blob size */
|
||||
int padsize; /* Additional padding to blob */
|
||||
|
||||
char *join_path(const char *path, const char *name)
|
||||
{
|
||||
int lenp = strlen(path);
|
||||
int lenn = strlen(name);
|
||||
int len;
|
||||
int needslash = 1;
|
||||
char *str;
|
||||
|
||||
len = lenp + lenn + 2;
|
||||
if ((lenp > 0) && (path[lenp-1] == '/')) {
|
||||
needslash = 0;
|
||||
len--;
|
||||
}
|
||||
|
||||
str = xmalloc(len);
|
||||
memcpy(str, path, lenp);
|
||||
if (needslash) {
|
||||
str[lenp] = '/';
|
||||
lenp++;
|
||||
}
|
||||
memcpy(str+lenp, name, lenn+1);
|
||||
return str;
|
||||
}
|
||||
|
||||
void fill_fullpaths(struct node *tree, const char *prefix)
|
||||
{
|
||||
struct node *child;
|
||||
const char *unit;
|
||||
|
||||
tree->fullpath = join_path(prefix, tree->name);
|
||||
|
||||
unit = strchr(tree->name, '@');
|
||||
if (unit)
|
||||
tree->basenamelen = unit - tree->name;
|
||||
else
|
||||
tree->basenamelen = strlen(tree->name);
|
||||
|
||||
for_each_child(tree, child)
|
||||
fill_fullpaths(child, tree->fullpath);
|
||||
}
|
||||
|
||||
static void __attribute__ ((noreturn)) usage(void)
|
||||
{
|
||||
fprintf(stderr, "Usage:\n");
|
||||
fprintf(stderr, "\tdtc [options] <input file>\n");
|
||||
fprintf(stderr, "\nOptions:\n");
|
||||
fprintf(stderr, "\t-h\n");
|
||||
fprintf(stderr, "\t\tThis help text\n");
|
||||
fprintf(stderr, "\t-q\n");
|
||||
fprintf(stderr, "\t\tQuiet: -q suppress warnings, -qq errors, -qqq all\n");
|
||||
fprintf(stderr, "\t-I <input format>\n");
|
||||
fprintf(stderr, "\t\tInput formats are:\n");
|
||||
fprintf(stderr, "\t\t\tdts - device tree source text\n");
|
||||
fprintf(stderr, "\t\t\tdtb - device tree blob\n");
|
||||
fprintf(stderr, "\t\t\tfs - /proc/device-tree style directory\n");
|
||||
fprintf(stderr, "\t-o <output file>\n");
|
||||
fprintf(stderr, "\t-O <output format>\n");
|
||||
fprintf(stderr, "\t\tOutput formats are:\n");
|
||||
fprintf(stderr, "\t\t\tdts - device tree source text\n");
|
||||
fprintf(stderr, "\t\t\tdtb - device tree blob\n");
|
||||
fprintf(stderr, "\t\t\tasm - assembler source\n");
|
||||
fprintf(stderr, "\t-V <output version>\n");
|
||||
fprintf(stderr, "\t\tBlob version to produce, defaults to %d (relevant for dtb\n\t\tand asm output only)\n", DEFAULT_FDT_VERSION);
|
||||
fprintf(stderr, "\t-R <number>\n");
|
||||
fprintf(stderr, "\t\tMake space for <number> reserve map entries (relevant for \n\t\tdtb and asm output only)\n");
|
||||
fprintf(stderr, "\t-S <bytes>\n");
|
||||
fprintf(stderr, "\t\tMake the blob at least <bytes> long (extra space)\n");
|
||||
fprintf(stderr, "\t-p <bytes>\n");
|
||||
fprintf(stderr, "\t\tAdd padding to the blob of <bytes> long (extra space)\n");
|
||||
fprintf(stderr, "\t-b <number>\n");
|
||||
fprintf(stderr, "\t\tSet the physical boot cpu\n");
|
||||
fprintf(stderr, "\t-f\n");
|
||||
fprintf(stderr, "\t\tForce - try to produce output even if the input tree has errors\n");
|
||||
fprintf(stderr, "\t-v\n");
|
||||
fprintf(stderr, "\t\tPrint DTC version and exit\n");
|
||||
exit(2);
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
struct boot_info *bi;
|
||||
const char *inform = "dts";
|
||||
const char *outform = "dts";
|
||||
const char *outname = "-";
|
||||
int force = 0, check = 0;
|
||||
const char *arg;
|
||||
int opt;
|
||||
FILE *inf = NULL;
|
||||
FILE *outf = NULL;
|
||||
int outversion = DEFAULT_FDT_VERSION;
|
||||
int boot_cpuid_phys = 0xfeedbeef;
|
||||
|
||||
quiet = 0;
|
||||
reservenum = 0;
|
||||
minsize = 0;
|
||||
padsize = 0;
|
||||
|
||||
while ((opt = getopt(argc, argv, "hI:O:o:V:R:S:p:fcqb:v")) != EOF) {
|
||||
switch (opt) {
|
||||
case 'I':
|
||||
inform = optarg;
|
||||
break;
|
||||
case 'O':
|
||||
outform = optarg;
|
||||
break;
|
||||
case 'o':
|
||||
outname = optarg;
|
||||
break;
|
||||
case 'V':
|
||||
outversion = strtol(optarg, NULL, 0);
|
||||
break;
|
||||
case 'R':
|
||||
reservenum = strtol(optarg, NULL, 0);
|
||||
break;
|
||||
case 'S':
|
||||
minsize = strtol(optarg, NULL, 0);
|
||||
break;
|
||||
case 'p':
|
||||
padsize = strtol(optarg, NULL, 0);
|
||||
break;
|
||||
case 'f':
|
||||
force = 1;
|
||||
break;
|
||||
case 'c':
|
||||
check = 1;
|
||||
break;
|
||||
case 'q':
|
||||
quiet++;
|
||||
break;
|
||||
case 'b':
|
||||
boot_cpuid_phys = strtol(optarg, NULL, 0);
|
||||
break;
|
||||
case 'v':
|
||||
printf("Version: %s\n", DTC_VERSION);
|
||||
exit(0);
|
||||
case 'h':
|
||||
default:
|
||||
usage();
|
||||
}
|
||||
}
|
||||
|
||||
if (argc > (optind+1))
|
||||
usage();
|
||||
else if (argc < (optind+1))
|
||||
arg = "-";
|
||||
else
|
||||
arg = argv[optind];
|
||||
|
||||
/* minsize and padsize are mutually exclusive */
|
||||
if ((minsize) && (padsize)) {
|
||||
die("Can't set both -p and -S\n");
|
||||
}
|
||||
|
||||
fprintf(stderr, "DTC: %s->%s on file \"%s\"\n",
|
||||
inform, outform, arg);
|
||||
|
||||
if (streq(inform, "dts")) {
|
||||
bi = dt_from_source(arg);
|
||||
} else if (streq(inform, "fs")) {
|
||||
bi = dt_from_fs(arg);
|
||||
} else if(streq(inform, "dtb")) {
|
||||
inf = dtc_open_file(arg);
|
||||
bi = dt_from_blob(inf);
|
||||
} else {
|
||||
die("Unknown input format \"%s\"\n", inform);
|
||||
}
|
||||
|
||||
if (inf && (inf != stdin))
|
||||
fclose(inf);
|
||||
|
||||
if (! bi || ! bi->dt)
|
||||
die("Couldn't read input tree\n");
|
||||
|
||||
process_checks(force, bi, check, outversion, boot_cpuid_phys);
|
||||
|
||||
if (streq(outname, "-")) {
|
||||
outf = stdout;
|
||||
} else {
|
||||
outf = fopen(outname, "w");
|
||||
if (! outf)
|
||||
die("Couldn't open output file %s: %s\n",
|
||||
outname, strerror(errno));
|
||||
}
|
||||
|
||||
if (streq(outform, "dts")) {
|
||||
dt_to_source(outf, bi);
|
||||
} else if (streq(outform, "dtb")) {
|
||||
dt_to_blob(outf, bi, outversion, boot_cpuid_phys);
|
||||
} else if (streq(outform, "asm")) {
|
||||
dt_to_asm(outf, bi, outversion, boot_cpuid_phys);
|
||||
} else if (streq(outform, "null")) {
|
||||
/* do nothing */
|
||||
} else {
|
||||
die("Unknown output format \"%s\"\n", outform);
|
||||
}
|
||||
|
||||
exit(0);
|
||||
}
|
||||
269
arch/powerpc/boot/dtc-src/dtc.h
Normal file
269
arch/powerpc/boot/dtc-src/dtc.h
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
#ifndef _DTC_H
|
||||
#define _DTC_H
|
||||
|
||||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
#include <stdarg.h>
|
||||
#include <assert.h>
|
||||
#include <ctype.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <netinet/in.h>
|
||||
#include <endian.h>
|
||||
#include <byteswap.h>
|
||||
|
||||
#include <fdt.h>
|
||||
|
||||
#define DEFAULT_FDT_VERSION 17
|
||||
/*
|
||||
* Command line options
|
||||
*/
|
||||
extern int quiet; /* Level of quietness */
|
||||
extern int reservenum; /* Number of memory reservation slots */
|
||||
extern int minsize; /* Minimum blob size */
|
||||
extern int padsize; /* Additional padding to blob */
|
||||
|
||||
static inline void __attribute__((noreturn)) die(char * str, ...)
|
||||
{
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, str);
|
||||
fprintf(stderr, "FATAL ERROR: ");
|
||||
vfprintf(stderr, str, ap);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
static inline void *xmalloc(size_t len)
|
||||
{
|
||||
void *new = malloc(len);
|
||||
|
||||
if (! new)
|
||||
die("malloc() failed\n");
|
||||
|
||||
return new;
|
||||
}
|
||||
|
||||
static inline void *xrealloc(void *p, size_t len)
|
||||
{
|
||||
void *new = realloc(p, len);
|
||||
|
||||
if (! new)
|
||||
die("realloc() failed (len=%d)\n", len);
|
||||
|
||||
return new;
|
||||
}
|
||||
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
typedef uint64_t u64;
|
||||
typedef u32 cell_t;
|
||||
|
||||
#define cpu_to_be16(x) htons(x)
|
||||
#define be16_to_cpu(x) ntohs(x)
|
||||
|
||||
#define cpu_to_be32(x) htonl(x)
|
||||
#define be32_to_cpu(x) ntohl(x)
|
||||
|
||||
#if __BYTE_ORDER == __BIG_ENDIAN
|
||||
#define cpu_to_be64(x) (x)
|
||||
#define be64_to_cpu(x) (x)
|
||||
#else
|
||||
#define cpu_to_be64(x) bswap_64(x)
|
||||
#define be64_to_cpu(x) bswap_64(x)
|
||||
#endif
|
||||
|
||||
#define streq(a, b) (strcmp((a), (b)) == 0)
|
||||
#define strneq(a, b, n) (strncmp((a), (b), (n)) == 0)
|
||||
|
||||
#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
/* Data blobs */
|
||||
enum markertype {
|
||||
REF_PHANDLE,
|
||||
REF_PATH,
|
||||
LABEL,
|
||||
};
|
||||
|
||||
struct marker {
|
||||
enum markertype type;
|
||||
int offset;
|
||||
char *ref;
|
||||
struct marker *next;
|
||||
};
|
||||
|
||||
struct data {
|
||||
int len;
|
||||
char *val;
|
||||
int asize;
|
||||
struct marker *markers;
|
||||
};
|
||||
|
||||
|
||||
#define empty_data ((struct data){ /* all .members = 0 or NULL */ })
|
||||
|
||||
#define for_each_marker(m) \
|
||||
for (; (m); (m) = (m)->next)
|
||||
#define for_each_marker_of_type(m, t) \
|
||||
for_each_marker(m) \
|
||||
if ((m)->type == (t))
|
||||
|
||||
void data_free(struct data d);
|
||||
|
||||
struct data data_grow_for(struct data d, int xlen);
|
||||
|
||||
struct data data_copy_mem(const char *mem, int len);
|
||||
struct data data_copy_escape_string(const char *s, int len);
|
||||
struct data data_copy_file(FILE *f, size_t len);
|
||||
|
||||
struct data data_append_data(struct data d, const void *p, int len);
|
||||
struct data data_insert_at_marker(struct data d, struct marker *m,
|
||||
const void *p, int len);
|
||||
struct data data_merge(struct data d1, struct data d2);
|
||||
struct data data_append_cell(struct data d, cell_t word);
|
||||
struct data data_append_re(struct data d, const struct fdt_reserve_entry *re);
|
||||
struct data data_append_addr(struct data d, u64 addr);
|
||||
struct data data_append_byte(struct data d, uint8_t byte);
|
||||
struct data data_append_zeroes(struct data d, int len);
|
||||
struct data data_append_align(struct data d, int align);
|
||||
|
||||
struct data data_add_marker(struct data d, enum markertype type, char *ref);
|
||||
|
||||
int data_is_one_string(struct data d);
|
||||
|
||||
/* DT constraints */
|
||||
|
||||
#define MAX_PROPNAME_LEN 31
|
||||
#define MAX_NODENAME_LEN 31
|
||||
|
||||
/* Live trees */
|
||||
struct property {
|
||||
char *name;
|
||||
struct data val;
|
||||
|
||||
struct property *next;
|
||||
|
||||
char *label;
|
||||
};
|
||||
|
||||
struct node {
|
||||
char *name;
|
||||
struct property *proplist;
|
||||
struct node *children;
|
||||
|
||||
struct node *parent;
|
||||
struct node *next_sibling;
|
||||
|
||||
char *fullpath;
|
||||
int basenamelen;
|
||||
|
||||
cell_t phandle;
|
||||
int addr_cells, size_cells;
|
||||
|
||||
char *label;
|
||||
};
|
||||
|
||||
#define for_each_property(n, p) \
|
||||
for ((p) = (n)->proplist; (p); (p) = (p)->next)
|
||||
|
||||
#define for_each_child(n, c) \
|
||||
for ((c) = (n)->children; (c); (c) = (c)->next_sibling)
|
||||
|
||||
struct property *build_property(char *name, struct data val, char *label);
|
||||
struct property *chain_property(struct property *first, struct property *list);
|
||||
struct property *reverse_properties(struct property *first);
|
||||
|
||||
struct node *build_node(struct property *proplist, struct node *children);
|
||||
struct node *name_node(struct node *node, char *name, char *label);
|
||||
struct node *chain_node(struct node *first, struct node *list);
|
||||
|
||||
void add_property(struct node *node, struct property *prop);
|
||||
void add_child(struct node *parent, struct node *child);
|
||||
|
||||
const char *get_unitname(struct node *node);
|
||||
struct property *get_property(struct node *node, const char *propname);
|
||||
cell_t propval_cell(struct property *prop);
|
||||
struct node *get_subnode(struct node *node, const char *nodename);
|
||||
struct node *get_node_by_path(struct node *tree, const char *path);
|
||||
struct node *get_node_by_label(struct node *tree, const char *label);
|
||||
struct node *get_node_by_phandle(struct node *tree, cell_t phandle);
|
||||
struct node *get_node_by_ref(struct node *tree, const char *ref);
|
||||
cell_t get_node_phandle(struct node *root, struct node *node);
|
||||
|
||||
/* Boot info (tree plus memreserve information */
|
||||
|
||||
struct reserve_info {
|
||||
struct fdt_reserve_entry re;
|
||||
|
||||
struct reserve_info *next;
|
||||
|
||||
char *label;
|
||||
};
|
||||
|
||||
struct reserve_info *build_reserve_entry(u64 start, u64 len, char *label);
|
||||
struct reserve_info *chain_reserve_entry(struct reserve_info *first,
|
||||
struct reserve_info *list);
|
||||
struct reserve_info *add_reserve_entry(struct reserve_info *list,
|
||||
struct reserve_info *new);
|
||||
|
||||
|
||||
struct boot_info {
|
||||
struct reserve_info *reservelist;
|
||||
struct node *dt; /* the device tree */
|
||||
};
|
||||
|
||||
struct boot_info *build_boot_info(struct reserve_info *reservelist,
|
||||
struct node *tree);
|
||||
|
||||
/* Checks */
|
||||
|
||||
void process_checks(int force, struct boot_info *bi,
|
||||
int checkflag, int outversion, int boot_cpuid_phys);
|
||||
|
||||
/* Flattened trees */
|
||||
|
||||
void dt_to_blob(FILE *f, struct boot_info *bi, int version,
|
||||
int boot_cpuid_phys);
|
||||
void dt_to_asm(FILE *f, struct boot_info *bi, int version,
|
||||
int boot_cpuid_phys);
|
||||
|
||||
struct boot_info *dt_from_blob(FILE *f);
|
||||
|
||||
/* Tree source */
|
||||
|
||||
void dt_to_source(FILE *f, struct boot_info *bi);
|
||||
struct boot_info *dt_from_source(const char *f);
|
||||
|
||||
/* FS trees */
|
||||
|
||||
struct boot_info *dt_from_fs(const char *dirname);
|
||||
|
||||
/* misc */
|
||||
|
||||
char *join_path(const char *path, const char *name);
|
||||
void fill_fullpaths(struct node *tree, const char *prefix);
|
||||
|
||||
#endif /* _DTC_H */
|
||||
968
arch/powerpc/boot/dtc-src/flattree.c
Normal file
968
arch/powerpc/boot/dtc-src/flattree.c
Normal file
|
|
@ -0,0 +1,968 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "dtc.h"
|
||||
|
||||
#define FTF_FULLPATH 0x1
|
||||
#define FTF_VARALIGN 0x2
|
||||
#define FTF_NAMEPROPS 0x4
|
||||
#define FTF_BOOTCPUID 0x8
|
||||
#define FTF_STRTABSIZE 0x10
|
||||
#define FTF_STRUCTSIZE 0x20
|
||||
#define FTF_NOPS 0x40
|
||||
|
||||
static struct version_info {
|
||||
int version;
|
||||
int last_comp_version;
|
||||
int hdr_size;
|
||||
int flags;
|
||||
} version_table[] = {
|
||||
{1, 1, FDT_V1_SIZE,
|
||||
FTF_FULLPATH|FTF_VARALIGN|FTF_NAMEPROPS},
|
||||
{2, 1, FDT_V2_SIZE,
|
||||
FTF_FULLPATH|FTF_VARALIGN|FTF_NAMEPROPS|FTF_BOOTCPUID},
|
||||
{3, 1, FDT_V3_SIZE,
|
||||
FTF_FULLPATH|FTF_VARALIGN|FTF_NAMEPROPS|FTF_BOOTCPUID|FTF_STRTABSIZE},
|
||||
{16, 16, FDT_V3_SIZE,
|
||||
FTF_BOOTCPUID|FTF_STRTABSIZE|FTF_NOPS},
|
||||
{17, 16, FDT_V17_SIZE,
|
||||
FTF_BOOTCPUID|FTF_STRTABSIZE|FTF_STRUCTSIZE|FTF_NOPS},
|
||||
};
|
||||
|
||||
struct emitter {
|
||||
void (*cell)(void *, cell_t);
|
||||
void (*string)(void *, char *, int);
|
||||
void (*align)(void *, int);
|
||||
void (*data)(void *, struct data);
|
||||
void (*beginnode)(void *, const char *);
|
||||
void (*endnode)(void *, const char *);
|
||||
void (*property)(void *, const char *);
|
||||
};
|
||||
|
||||
static void bin_emit_cell(void *e, cell_t val)
|
||||
{
|
||||
struct data *dtbuf = e;
|
||||
|
||||
*dtbuf = data_append_cell(*dtbuf, val);
|
||||
}
|
||||
|
||||
static void bin_emit_string(void *e, char *str, int len)
|
||||
{
|
||||
struct data *dtbuf = e;
|
||||
|
||||
if (len == 0)
|
||||
len = strlen(str);
|
||||
|
||||
*dtbuf = data_append_data(*dtbuf, str, len);
|
||||
*dtbuf = data_append_byte(*dtbuf, '\0');
|
||||
}
|
||||
|
||||
static void bin_emit_align(void *e, int a)
|
||||
{
|
||||
struct data *dtbuf = e;
|
||||
|
||||
*dtbuf = data_append_align(*dtbuf, a);
|
||||
}
|
||||
|
||||
static void bin_emit_data(void *e, struct data d)
|
||||
{
|
||||
struct data *dtbuf = e;
|
||||
|
||||
*dtbuf = data_append_data(*dtbuf, d.val, d.len);
|
||||
}
|
||||
|
||||
static void bin_emit_beginnode(void *e, const char *label)
|
||||
{
|
||||
bin_emit_cell(e, FDT_BEGIN_NODE);
|
||||
}
|
||||
|
||||
static void bin_emit_endnode(void *e, const char *label)
|
||||
{
|
||||
bin_emit_cell(e, FDT_END_NODE);
|
||||
}
|
||||
|
||||
static void bin_emit_property(void *e, const char *label)
|
||||
{
|
||||
bin_emit_cell(e, FDT_PROP);
|
||||
}
|
||||
|
||||
static struct emitter bin_emitter = {
|
||||
.cell = bin_emit_cell,
|
||||
.string = bin_emit_string,
|
||||
.align = bin_emit_align,
|
||||
.data = bin_emit_data,
|
||||
.beginnode = bin_emit_beginnode,
|
||||
.endnode = bin_emit_endnode,
|
||||
.property = bin_emit_property,
|
||||
};
|
||||
|
||||
static void emit_label(FILE *f, const char *prefix, const char *label)
|
||||
{
|
||||
fprintf(f, "\t.globl\t%s_%s\n", prefix, label);
|
||||
fprintf(f, "%s_%s:\n", prefix, label);
|
||||
fprintf(f, "_%s_%s:\n", prefix, label);
|
||||
}
|
||||
|
||||
static void emit_offset_label(FILE *f, const char *label, int offset)
|
||||
{
|
||||
fprintf(f, "\t.globl\t%s\n", label);
|
||||
fprintf(f, "%s\t= . + %d\n", label, offset);
|
||||
}
|
||||
|
||||
static void asm_emit_cell(void *e, cell_t val)
|
||||
{
|
||||
FILE *f = e;
|
||||
|
||||
fprintf(f, "\t.long\t0x%x\n", val);
|
||||
}
|
||||
|
||||
static void asm_emit_string(void *e, char *str, int len)
|
||||
{
|
||||
FILE *f = e;
|
||||
char c = 0;
|
||||
|
||||
if (len != 0) {
|
||||
/* XXX: ewww */
|
||||
c = str[len];
|
||||
str[len] = '\0';
|
||||
}
|
||||
|
||||
fprintf(f, "\t.string\t\"%s\"\n", str);
|
||||
|
||||
if (len != 0) {
|
||||
str[len] = c;
|
||||
}
|
||||
}
|
||||
|
||||
static void asm_emit_align(void *e, int a)
|
||||
{
|
||||
FILE *f = e;
|
||||
|
||||
fprintf(f, "\t.balign\t%d\n", a);
|
||||
}
|
||||
|
||||
static void asm_emit_data(void *e, struct data d)
|
||||
{
|
||||
FILE *f = e;
|
||||
int off = 0;
|
||||
struct marker *m;
|
||||
|
||||
m = d.markers;
|
||||
while (m) {
|
||||
if (m->type == LABEL)
|
||||
emit_offset_label(f, m->ref, m->offset);
|
||||
m = m->next;
|
||||
}
|
||||
|
||||
while ((d.len - off) >= sizeof(u32)) {
|
||||
fprintf(f, "\t.long\t0x%x\n",
|
||||
be32_to_cpu(*((u32 *)(d.val+off))));
|
||||
off += sizeof(u32);
|
||||
}
|
||||
|
||||
if ((d.len - off) >= sizeof(u16)) {
|
||||
fprintf(f, "\t.short\t0x%hx\n",
|
||||
be16_to_cpu(*((u16 *)(d.val+off))));
|
||||
off += sizeof(u16);
|
||||
}
|
||||
|
||||
if ((d.len - off) >= 1) {
|
||||
fprintf(f, "\t.byte\t0x%hhx\n", d.val[off]);
|
||||
off += 1;
|
||||
}
|
||||
|
||||
assert(off == d.len);
|
||||
}
|
||||
|
||||
static void asm_emit_beginnode(void *e, const char *label)
|
||||
{
|
||||
FILE *f = e;
|
||||
|
||||
if (label) {
|
||||
fprintf(f, "\t.globl\t%s\n", label);
|
||||
fprintf(f, "%s:\n", label);
|
||||
}
|
||||
fprintf(f, "\t.long\tFDT_BEGIN_NODE\n");
|
||||
}
|
||||
|
||||
static void asm_emit_endnode(void *e, const char *label)
|
||||
{
|
||||
FILE *f = e;
|
||||
|
||||
fprintf(f, "\t.long\tFDT_END_NODE\n");
|
||||
if (label) {
|
||||
fprintf(f, "\t.globl\t%s_end\n", label);
|
||||
fprintf(f, "%s_end:\n", label);
|
||||
}
|
||||
}
|
||||
|
||||
static void asm_emit_property(void *e, const char *label)
|
||||
{
|
||||
FILE *f = e;
|
||||
|
||||
if (label) {
|
||||
fprintf(f, "\t.globl\t%s\n", label);
|
||||
fprintf(f, "%s:\n", label);
|
||||
}
|
||||
fprintf(f, "\t.long\tFDT_PROP\n");
|
||||
}
|
||||
|
||||
static struct emitter asm_emitter = {
|
||||
.cell = asm_emit_cell,
|
||||
.string = asm_emit_string,
|
||||
.align = asm_emit_align,
|
||||
.data = asm_emit_data,
|
||||
.beginnode = asm_emit_beginnode,
|
||||
.endnode = asm_emit_endnode,
|
||||
.property = asm_emit_property,
|
||||
};
|
||||
|
||||
static int stringtable_insert(struct data *d, const char *str)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* FIXME: do this more efficiently? */
|
||||
|
||||
for (i = 0; i < d->len; i++) {
|
||||
if (streq(str, d->val + i))
|
||||
return i;
|
||||
}
|
||||
|
||||
*d = data_append_data(*d, str, strlen(str)+1);
|
||||
return i;
|
||||
}
|
||||
|
||||
static void flatten_tree(struct node *tree, struct emitter *emit,
|
||||
void *etarget, struct data *strbuf,
|
||||
struct version_info *vi)
|
||||
{
|
||||
struct property *prop;
|
||||
struct node *child;
|
||||
int seen_name_prop = 0;
|
||||
|
||||
emit->beginnode(etarget, tree->label);
|
||||
|
||||
if (vi->flags & FTF_FULLPATH)
|
||||
emit->string(etarget, tree->fullpath, 0);
|
||||
else
|
||||
emit->string(etarget, tree->name, 0);
|
||||
|
||||
emit->align(etarget, sizeof(cell_t));
|
||||
|
||||
for_each_property(tree, prop) {
|
||||
int nameoff;
|
||||
|
||||
if (streq(prop->name, "name"))
|
||||
seen_name_prop = 1;
|
||||
|
||||
nameoff = stringtable_insert(strbuf, prop->name);
|
||||
|
||||
emit->property(etarget, prop->label);
|
||||
emit->cell(etarget, prop->val.len);
|
||||
emit->cell(etarget, nameoff);
|
||||
|
||||
if ((vi->flags & FTF_VARALIGN) && (prop->val.len >= 8))
|
||||
emit->align(etarget, 8);
|
||||
|
||||
emit->data(etarget, prop->val);
|
||||
emit->align(etarget, sizeof(cell_t));
|
||||
}
|
||||
|
||||
if ((vi->flags & FTF_NAMEPROPS) && !seen_name_prop) {
|
||||
emit->property(etarget, NULL);
|
||||
emit->cell(etarget, tree->basenamelen+1);
|
||||
emit->cell(etarget, stringtable_insert(strbuf, "name"));
|
||||
|
||||
if ((vi->flags & FTF_VARALIGN) && ((tree->basenamelen+1) >= 8))
|
||||
emit->align(etarget, 8);
|
||||
|
||||
emit->string(etarget, tree->name, tree->basenamelen);
|
||||
emit->align(etarget, sizeof(cell_t));
|
||||
}
|
||||
|
||||
for_each_child(tree, child) {
|
||||
flatten_tree(child, emit, etarget, strbuf, vi);
|
||||
}
|
||||
|
||||
emit->endnode(etarget, tree->label);
|
||||
}
|
||||
|
||||
static struct data flatten_reserve_list(struct reserve_info *reservelist,
|
||||
struct version_info *vi)
|
||||
{
|
||||
struct reserve_info *re;
|
||||
struct data d = empty_data;
|
||||
static struct fdt_reserve_entry null_re = {0,0};
|
||||
int j;
|
||||
|
||||
for (re = reservelist; re; re = re->next) {
|
||||
d = data_append_re(d, &re->re);
|
||||
}
|
||||
/*
|
||||
* Add additional reserved slots if the user asked for them.
|
||||
*/
|
||||
for (j = 0; j < reservenum; j++) {
|
||||
d = data_append_re(d, &null_re);
|
||||
}
|
||||
|
||||
return d;
|
||||
}
|
||||
|
||||
static void make_fdt_header(struct fdt_header *fdt,
|
||||
struct version_info *vi,
|
||||
int reservesize, int dtsize, int strsize,
|
||||
int boot_cpuid_phys)
|
||||
{
|
||||
int reserve_off;
|
||||
|
||||
reservesize += sizeof(struct fdt_reserve_entry);
|
||||
|
||||
memset(fdt, 0xff, sizeof(*fdt));
|
||||
|
||||
fdt->magic = cpu_to_be32(FDT_MAGIC);
|
||||
fdt->version = cpu_to_be32(vi->version);
|
||||
fdt->last_comp_version = cpu_to_be32(vi->last_comp_version);
|
||||
|
||||
/* Reserve map should be doubleword aligned */
|
||||
reserve_off = ALIGN(vi->hdr_size, 8);
|
||||
|
||||
fdt->off_mem_rsvmap = cpu_to_be32(reserve_off);
|
||||
fdt->off_dt_struct = cpu_to_be32(reserve_off + reservesize);
|
||||
fdt->off_dt_strings = cpu_to_be32(reserve_off + reservesize
|
||||
+ dtsize);
|
||||
fdt->totalsize = cpu_to_be32(reserve_off + reservesize + dtsize + strsize);
|
||||
|
||||
if (vi->flags & FTF_BOOTCPUID)
|
||||
fdt->boot_cpuid_phys = cpu_to_be32(boot_cpuid_phys);
|
||||
if (vi->flags & FTF_STRTABSIZE)
|
||||
fdt->size_dt_strings = cpu_to_be32(strsize);
|
||||
if (vi->flags & FTF_STRUCTSIZE)
|
||||
fdt->size_dt_struct = cpu_to_be32(dtsize);
|
||||
}
|
||||
|
||||
void dt_to_blob(FILE *f, struct boot_info *bi, int version,
|
||||
int boot_cpuid_phys)
|
||||
{
|
||||
struct version_info *vi = NULL;
|
||||
int i;
|
||||
struct data blob = empty_data;
|
||||
struct data reservebuf = empty_data;
|
||||
struct data dtbuf = empty_data;
|
||||
struct data strbuf = empty_data;
|
||||
struct fdt_header fdt;
|
||||
int padlen = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(version_table); i++) {
|
||||
if (version_table[i].version == version)
|
||||
vi = &version_table[i];
|
||||
}
|
||||
if (!vi)
|
||||
die("Unknown device tree blob version %d\n", version);
|
||||
|
||||
flatten_tree(bi->dt, &bin_emitter, &dtbuf, &strbuf, vi);
|
||||
bin_emit_cell(&dtbuf, FDT_END);
|
||||
|
||||
reservebuf = flatten_reserve_list(bi->reservelist, vi);
|
||||
|
||||
/* Make header */
|
||||
make_fdt_header(&fdt, vi, reservebuf.len, dtbuf.len, strbuf.len,
|
||||
boot_cpuid_phys);
|
||||
|
||||
/*
|
||||
* If the user asked for more space than is used, adjust the totalsize.
|
||||
*/
|
||||
if (minsize > 0) {
|
||||
padlen = minsize - be32_to_cpu(fdt.totalsize);
|
||||
if ((padlen < 0) && (quiet < 1))
|
||||
fprintf(stderr,
|
||||
"Warning: blob size %d >= minimum size %d\n",
|
||||
be32_to_cpu(fdt.totalsize), minsize);
|
||||
}
|
||||
|
||||
if (padsize > 0)
|
||||
padlen = padsize;
|
||||
|
||||
if (padlen > 0) {
|
||||
int tsize = be32_to_cpu(fdt.totalsize);
|
||||
tsize += padlen;
|
||||
fdt.totalsize = cpu_to_be32(tsize);
|
||||
}
|
||||
|
||||
/*
|
||||
* Assemble the blob: start with the header, add with alignment
|
||||
* the reserve buffer, add the reserve map terminating zeroes,
|
||||
* the device tree itself, and finally the strings.
|
||||
*/
|
||||
blob = data_append_data(blob, &fdt, sizeof(fdt));
|
||||
blob = data_append_align(blob, 8);
|
||||
blob = data_merge(blob, reservebuf);
|
||||
blob = data_append_zeroes(blob, sizeof(struct fdt_reserve_entry));
|
||||
blob = data_merge(blob, dtbuf);
|
||||
blob = data_merge(blob, strbuf);
|
||||
|
||||
/*
|
||||
* If the user asked for more space than is used, pad out the blob.
|
||||
*/
|
||||
if (padlen > 0)
|
||||
blob = data_append_zeroes(blob, padlen);
|
||||
|
||||
fwrite(blob.val, blob.len, 1, f);
|
||||
|
||||
if (ferror(f))
|
||||
die("Error writing device tree blob: %s\n", strerror(errno));
|
||||
|
||||
/*
|
||||
* data_merge() frees the right-hand element so only the blob
|
||||
* remains to be freed.
|
||||
*/
|
||||
data_free(blob);
|
||||
}
|
||||
|
||||
static void dump_stringtable_asm(FILE *f, struct data strbuf)
|
||||
{
|
||||
const char *p;
|
||||
int len;
|
||||
|
||||
p = strbuf.val;
|
||||
|
||||
while (p < (strbuf.val + strbuf.len)) {
|
||||
len = strlen(p);
|
||||
fprintf(f, "\t.string \"%s\"\n", p);
|
||||
p += len+1;
|
||||
}
|
||||
}
|
||||
|
||||
void dt_to_asm(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys)
|
||||
{
|
||||
struct version_info *vi = NULL;
|
||||
int i;
|
||||
struct data strbuf = empty_data;
|
||||
struct reserve_info *re;
|
||||
const char *symprefix = "dt";
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(version_table); i++) {
|
||||
if (version_table[i].version == version)
|
||||
vi = &version_table[i];
|
||||
}
|
||||
if (!vi)
|
||||
die("Unknown device tree blob version %d\n", version);
|
||||
|
||||
fprintf(f, "/* autogenerated by dtc, do not edit */\n\n");
|
||||
fprintf(f, "#define FDT_MAGIC 0x%x\n", FDT_MAGIC);
|
||||
fprintf(f, "#define FDT_BEGIN_NODE 0x%x\n", FDT_BEGIN_NODE);
|
||||
fprintf(f, "#define FDT_END_NODE 0x%x\n", FDT_END_NODE);
|
||||
fprintf(f, "#define FDT_PROP 0x%x\n", FDT_PROP);
|
||||
fprintf(f, "#define FDT_END 0x%x\n", FDT_END);
|
||||
fprintf(f, "\n");
|
||||
|
||||
emit_label(f, symprefix, "blob_start");
|
||||
emit_label(f, symprefix, "header");
|
||||
fprintf(f, "\t.long\tFDT_MAGIC\t\t\t\t/* magic */\n");
|
||||
fprintf(f, "\t.long\t_%s_blob_abs_end - _%s_blob_start\t/* totalsize */\n",
|
||||
symprefix, symprefix);
|
||||
fprintf(f, "\t.long\t_%s_struct_start - _%s_blob_start\t/* off_dt_struct */\n",
|
||||
symprefix, symprefix);
|
||||
fprintf(f, "\t.long\t_%s_strings_start - _%s_blob_start\t/* off_dt_strings */\n",
|
||||
symprefix, symprefix);
|
||||
fprintf(f, "\t.long\t_%s_reserve_map - _%s_blob_start\t/* off_dt_strings */\n",
|
||||
symprefix, symprefix);
|
||||
fprintf(f, "\t.long\t%d\t\t\t\t\t/* version */\n", vi->version);
|
||||
fprintf(f, "\t.long\t%d\t\t\t\t\t/* last_comp_version */\n",
|
||||
vi->last_comp_version);
|
||||
|
||||
if (vi->flags & FTF_BOOTCPUID)
|
||||
fprintf(f, "\t.long\t%i\t\t\t\t\t/* boot_cpuid_phys */\n",
|
||||
boot_cpuid_phys);
|
||||
|
||||
if (vi->flags & FTF_STRTABSIZE)
|
||||
fprintf(f, "\t.long\t_%s_strings_end - _%s_strings_start\t/* size_dt_strings */\n",
|
||||
symprefix, symprefix);
|
||||
|
||||
if (vi->flags & FTF_STRUCTSIZE)
|
||||
fprintf(f, "\t.long\t_%s_struct_end - _%s_struct_start\t/* size_dt_struct */\n",
|
||||
symprefix, symprefix);
|
||||
|
||||
/*
|
||||
* Reserve map entries.
|
||||
* Align the reserve map to a doubleword boundary.
|
||||
* Each entry is an (address, size) pair of u64 values.
|
||||
* Always supply a zero-sized temination entry.
|
||||
*/
|
||||
asm_emit_align(f, 8);
|
||||
emit_label(f, symprefix, "reserve_map");
|
||||
|
||||
fprintf(f, "/* Memory reserve map from source file */\n");
|
||||
|
||||
/*
|
||||
* Use .long on high and low halfs of u64s to avoid .quad
|
||||
* as it appears .quad isn't available in some assemblers.
|
||||
*/
|
||||
for (re = bi->reservelist; re; re = re->next) {
|
||||
if (re->label) {
|
||||
fprintf(f, "\t.globl\t%s\n", re->label);
|
||||
fprintf(f, "%s:\n", re->label);
|
||||
}
|
||||
fprintf(f, "\t.long\t0x%08x, 0x%08x\n",
|
||||
(unsigned int)(re->re.address >> 32),
|
||||
(unsigned int)(re->re.address & 0xffffffff));
|
||||
fprintf(f, "\t.long\t0x%08x, 0x%08x\n",
|
||||
(unsigned int)(re->re.size >> 32),
|
||||
(unsigned int)(re->re.size & 0xffffffff));
|
||||
}
|
||||
for (i = 0; i < reservenum; i++) {
|
||||
fprintf(f, "\t.long\t0, 0\n\t.long\t0, 0\n");
|
||||
}
|
||||
|
||||
fprintf(f, "\t.long\t0, 0\n\t.long\t0, 0\n");
|
||||
|
||||
emit_label(f, symprefix, "struct_start");
|
||||
flatten_tree(bi->dt, &asm_emitter, f, &strbuf, vi);
|
||||
fprintf(f, "\t.long\tFDT_END\n");
|
||||
emit_label(f, symprefix, "struct_end");
|
||||
|
||||
emit_label(f, symprefix, "strings_start");
|
||||
dump_stringtable_asm(f, strbuf);
|
||||
emit_label(f, symprefix, "strings_end");
|
||||
|
||||
emit_label(f, symprefix, "blob_end");
|
||||
|
||||
/*
|
||||
* If the user asked for more space than is used, pad it out.
|
||||
*/
|
||||
if (minsize > 0) {
|
||||
fprintf(f, "\t.space\t%d - (_%s_blob_end - _%s_blob_start), 0\n",
|
||||
minsize, symprefix, symprefix);
|
||||
}
|
||||
if (padsize > 0) {
|
||||
fprintf(f, "\t.space\t%d, 0\n", padsize);
|
||||
}
|
||||
emit_label(f, symprefix, "blob_abs_end");
|
||||
|
||||
data_free(strbuf);
|
||||
}
|
||||
|
||||
struct inbuf {
|
||||
char *base, *limit, *ptr;
|
||||
};
|
||||
|
||||
static void inbuf_init(struct inbuf *inb, void *base, void *limit)
|
||||
{
|
||||
inb->base = base;
|
||||
inb->limit = limit;
|
||||
inb->ptr = inb->base;
|
||||
}
|
||||
|
||||
static void flat_read_chunk(struct inbuf *inb, void *p, int len)
|
||||
{
|
||||
if ((inb->ptr + len) > inb->limit)
|
||||
die("Premature end of data parsing flat device tree\n");
|
||||
|
||||
memcpy(p, inb->ptr, len);
|
||||
|
||||
inb->ptr += len;
|
||||
}
|
||||
|
||||
static u32 flat_read_word(struct inbuf *inb)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
assert(((inb->ptr - inb->base) % sizeof(val)) == 0);
|
||||
|
||||
flat_read_chunk(inb, &val, sizeof(val));
|
||||
|
||||
return be32_to_cpu(val);
|
||||
}
|
||||
|
||||
static void flat_realign(struct inbuf *inb, int align)
|
||||
{
|
||||
int off = inb->ptr - inb->base;
|
||||
|
||||
inb->ptr = inb->base + ALIGN(off, align);
|
||||
if (inb->ptr > inb->limit)
|
||||
die("Premature end of data parsing flat device tree\n");
|
||||
}
|
||||
|
||||
static char *flat_read_string(struct inbuf *inb)
|
||||
{
|
||||
int len = 0;
|
||||
const char *p = inb->ptr;
|
||||
char *str;
|
||||
|
||||
do {
|
||||
if (p >= inb->limit)
|
||||
die("Premature end of data parsing flat device tree\n");
|
||||
len++;
|
||||
} while ((*p++) != '\0');
|
||||
|
||||
str = strdup(inb->ptr);
|
||||
|
||||
inb->ptr += len;
|
||||
|
||||
flat_realign(inb, sizeof(u32));
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
static struct data flat_read_data(struct inbuf *inb, int len)
|
||||
{
|
||||
struct data d = empty_data;
|
||||
|
||||
if (len == 0)
|
||||
return empty_data;
|
||||
|
||||
d = data_grow_for(d, len);
|
||||
d.len = len;
|
||||
|
||||
flat_read_chunk(inb, d.val, len);
|
||||
|
||||
flat_realign(inb, sizeof(u32));
|
||||
|
||||
return d;
|
||||
}
|
||||
|
||||
static char *flat_read_stringtable(struct inbuf *inb, int offset)
|
||||
{
|
||||
const char *p;
|
||||
|
||||
p = inb->base + offset;
|
||||
while (1) {
|
||||
if (p >= inb->limit || p < inb->base)
|
||||
die("String offset %d overruns string table\n",
|
||||
offset);
|
||||
|
||||
if (*p == '\0')
|
||||
break;
|
||||
|
||||
p++;
|
||||
}
|
||||
|
||||
return strdup(inb->base + offset);
|
||||
}
|
||||
|
||||
static struct property *flat_read_property(struct inbuf *dtbuf,
|
||||
struct inbuf *strbuf, int flags)
|
||||
{
|
||||
u32 proplen, stroff;
|
||||
char *name;
|
||||
struct data val;
|
||||
|
||||
proplen = flat_read_word(dtbuf);
|
||||
stroff = flat_read_word(dtbuf);
|
||||
|
||||
name = flat_read_stringtable(strbuf, stroff);
|
||||
|
||||
if ((flags & FTF_VARALIGN) && (proplen >= 8))
|
||||
flat_realign(dtbuf, 8);
|
||||
|
||||
val = flat_read_data(dtbuf, proplen);
|
||||
|
||||
return build_property(name, val, NULL);
|
||||
}
|
||||
|
||||
|
||||
static struct reserve_info *flat_read_mem_reserve(struct inbuf *inb)
|
||||
{
|
||||
struct reserve_info *reservelist = NULL;
|
||||
struct reserve_info *new;
|
||||
const char *p;
|
||||
struct fdt_reserve_entry re;
|
||||
|
||||
/*
|
||||
* Each entry is a pair of u64 (addr, size) values for 4 cell_t's.
|
||||
* List terminates at an entry with size equal to zero.
|
||||
*
|
||||
* First pass, count entries.
|
||||
*/
|
||||
p = inb->ptr;
|
||||
while (1) {
|
||||
flat_read_chunk(inb, &re, sizeof(re));
|
||||
re.address = be64_to_cpu(re.address);
|
||||
re.size = be64_to_cpu(re.size);
|
||||
if (re.size == 0)
|
||||
break;
|
||||
|
||||
new = build_reserve_entry(re.address, re.size, NULL);
|
||||
reservelist = add_reserve_entry(reservelist, new);
|
||||
}
|
||||
|
||||
return reservelist;
|
||||
}
|
||||
|
||||
|
||||
static char *nodename_from_path(const char *ppath, const char *cpath)
|
||||
{
|
||||
const char *lslash;
|
||||
int plen;
|
||||
|
||||
lslash = strrchr(cpath, '/');
|
||||
if (! lslash)
|
||||
return NULL;
|
||||
|
||||
plen = lslash - cpath;
|
||||
|
||||
if (streq(cpath, "/") && streq(ppath, ""))
|
||||
return "";
|
||||
|
||||
if ((plen == 0) && streq(ppath, "/"))
|
||||
return strdup(lslash+1);
|
||||
|
||||
if (! strneq(ppath, cpath, plen))
|
||||
return NULL;
|
||||
|
||||
return strdup(lslash+1);
|
||||
}
|
||||
|
||||
static const char PROPCHAR[] = "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789,._+*#?-";
|
||||
static const char UNITCHAR[] = "0123456789abcdef,";
|
||||
|
||||
static int check_node_name(const char *name)
|
||||
{
|
||||
const char *atpos;
|
||||
int basenamelen;
|
||||
|
||||
atpos = strrchr(name, '@');
|
||||
|
||||
if (atpos)
|
||||
basenamelen = atpos - name;
|
||||
else
|
||||
basenamelen = strlen(name);
|
||||
|
||||
if (strspn(name, PROPCHAR) < basenamelen)
|
||||
return -1;
|
||||
|
||||
if (atpos
|
||||
&& ((basenamelen + 1 + strspn(atpos+1, UNITCHAR)) < strlen(name)))
|
||||
return -1;
|
||||
|
||||
return basenamelen;
|
||||
}
|
||||
|
||||
static struct node *unflatten_tree(struct inbuf *dtbuf,
|
||||
struct inbuf *strbuf,
|
||||
const char *parent_path, int flags)
|
||||
{
|
||||
struct node *node;
|
||||
u32 val;
|
||||
|
||||
node = build_node(NULL, NULL);
|
||||
|
||||
if (flags & FTF_FULLPATH) {
|
||||
node->fullpath = flat_read_string(dtbuf);
|
||||
node->name = nodename_from_path(parent_path, node->fullpath);
|
||||
|
||||
if (! node->name)
|
||||
die("Path \"%s\" is not valid as a child of \"%s\"\n",
|
||||
node->fullpath, parent_path);
|
||||
} else {
|
||||
node->name = flat_read_string(dtbuf);
|
||||
node->fullpath = join_path(parent_path, node->name);
|
||||
}
|
||||
|
||||
node->basenamelen = check_node_name(node->name);
|
||||
if (node->basenamelen < 0) {
|
||||
fprintf(stderr, "Warning \"%s\" has incorrect format\n", node->name);
|
||||
}
|
||||
|
||||
do {
|
||||
struct property *prop;
|
||||
struct node *child;
|
||||
|
||||
val = flat_read_word(dtbuf);
|
||||
switch (val) {
|
||||
case FDT_PROP:
|
||||
if (node->children)
|
||||
fprintf(stderr, "Warning: Flat tree input has "
|
||||
"subnodes preceding a property.\n");
|
||||
prop = flat_read_property(dtbuf, strbuf, flags);
|
||||
add_property(node, prop);
|
||||
break;
|
||||
|
||||
case FDT_BEGIN_NODE:
|
||||
child = unflatten_tree(dtbuf,strbuf, node->fullpath,
|
||||
flags);
|
||||
add_child(node, child);
|
||||
break;
|
||||
|
||||
case FDT_END_NODE:
|
||||
break;
|
||||
|
||||
case FDT_END:
|
||||
die("Premature FDT_END in device tree blob\n");
|
||||
break;
|
||||
|
||||
case FDT_NOP:
|
||||
if (!(flags & FTF_NOPS))
|
||||
fprintf(stderr, "Warning: NOP tag found in flat tree"
|
||||
" version <16\n");
|
||||
|
||||
/* Ignore */
|
||||
break;
|
||||
|
||||
default:
|
||||
die("Invalid opcode word %08x in device tree blob\n",
|
||||
val);
|
||||
}
|
||||
} while (val != FDT_END_NODE);
|
||||
|
||||
return node;
|
||||
}
|
||||
|
||||
|
||||
struct boot_info *dt_from_blob(FILE *f)
|
||||
{
|
||||
u32 magic, totalsize, version, size_str, size_dt;
|
||||
u32 off_dt, off_str, off_mem_rsvmap;
|
||||
int rc;
|
||||
char *blob;
|
||||
struct fdt_header *fdt;
|
||||
char *p;
|
||||
struct inbuf dtbuf, strbuf;
|
||||
struct inbuf memresvbuf;
|
||||
int sizeleft;
|
||||
struct reserve_info *reservelist;
|
||||
struct node *tree;
|
||||
u32 val;
|
||||
int flags = 0;
|
||||
|
||||
rc = fread(&magic, sizeof(magic), 1, f);
|
||||
if (ferror(f))
|
||||
die("Error reading DT blob magic number: %s\n",
|
||||
strerror(errno));
|
||||
if (rc < 1) {
|
||||
if (feof(f))
|
||||
die("EOF reading DT blob magic number\n");
|
||||
else
|
||||
die("Mysterious short read reading magic number\n");
|
||||
}
|
||||
|
||||
magic = be32_to_cpu(magic);
|
||||
if (magic != FDT_MAGIC)
|
||||
die("Blob has incorrect magic number\n");
|
||||
|
||||
rc = fread(&totalsize, sizeof(totalsize), 1, f);
|
||||
if (ferror(f))
|
||||
die("Error reading DT blob size: %s\n", strerror(errno));
|
||||
if (rc < 1) {
|
||||
if (feof(f))
|
||||
die("EOF reading DT blob size\n");
|
||||
else
|
||||
die("Mysterious short read reading blob size\n");
|
||||
}
|
||||
|
||||
totalsize = be32_to_cpu(totalsize);
|
||||
if (totalsize < FDT_V1_SIZE)
|
||||
die("DT blob size (%d) is too small\n", totalsize);
|
||||
|
||||
blob = xmalloc(totalsize);
|
||||
|
||||
fdt = (struct fdt_header *)blob;
|
||||
fdt->magic = cpu_to_be32(magic);
|
||||
fdt->totalsize = cpu_to_be32(totalsize);
|
||||
|
||||
sizeleft = totalsize - sizeof(magic) - sizeof(totalsize);
|
||||
p = blob + sizeof(magic) + sizeof(totalsize);
|
||||
|
||||
while (sizeleft) {
|
||||
if (feof(f))
|
||||
die("EOF before reading %d bytes of DT blob\n",
|
||||
totalsize);
|
||||
|
||||
rc = fread(p, 1, sizeleft, f);
|
||||
if (ferror(f))
|
||||
die("Error reading DT blob: %s\n",
|
||||
strerror(errno));
|
||||
|
||||
sizeleft -= rc;
|
||||
p += rc;
|
||||
}
|
||||
|
||||
off_dt = be32_to_cpu(fdt->off_dt_struct);
|
||||
off_str = be32_to_cpu(fdt->off_dt_strings);
|
||||
off_mem_rsvmap = be32_to_cpu(fdt->off_mem_rsvmap);
|
||||
version = be32_to_cpu(fdt->version);
|
||||
|
||||
fprintf(stderr, "\tmagic:\t\t\t0x%x\n", magic);
|
||||
fprintf(stderr, "\ttotalsize:\t\t%d\n", totalsize);
|
||||
fprintf(stderr, "\toff_dt_struct:\t\t0x%x\n", off_dt);
|
||||
fprintf(stderr, "\toff_dt_strings:\t\t0x%x\n", off_str);
|
||||
fprintf(stderr, "\toff_mem_rsvmap:\t\t0x%x\n", off_mem_rsvmap);
|
||||
fprintf(stderr, "\tversion:\t\t0x%x\n", version );
|
||||
fprintf(stderr, "\tlast_comp_version:\t0x%x\n",
|
||||
be32_to_cpu(fdt->last_comp_version));
|
||||
|
||||
if (off_mem_rsvmap >= totalsize)
|
||||
die("Mem Reserve structure offset exceeds total size\n");
|
||||
|
||||
if (off_dt >= totalsize)
|
||||
die("DT structure offset exceeds total size\n");
|
||||
|
||||
if (off_str > totalsize)
|
||||
die("String table offset exceeds total size\n");
|
||||
|
||||
if (version >= 2)
|
||||
fprintf(stderr, "\tboot_cpuid_phys:\t0x%x\n",
|
||||
be32_to_cpu(fdt->boot_cpuid_phys));
|
||||
|
||||
size_str = -1;
|
||||
if (version >= 3) {
|
||||
size_str = be32_to_cpu(fdt->size_dt_strings);
|
||||
fprintf(stderr, "\tsize_dt_strings:\t%d\n", size_str);
|
||||
if (off_str+size_str > totalsize)
|
||||
die("String table extends past total size\n");
|
||||
}
|
||||
|
||||
if (version >= 17) {
|
||||
size_dt = be32_to_cpu(fdt->size_dt_struct);
|
||||
fprintf(stderr, "\tsize_dt_struct:\t\t%d\n", size_dt);
|
||||
if (off_dt+size_dt > totalsize)
|
||||
die("Structure block extends past total size\n");
|
||||
}
|
||||
|
||||
if (version < 16) {
|
||||
flags |= FTF_FULLPATH | FTF_NAMEPROPS | FTF_VARALIGN;
|
||||
} else {
|
||||
flags |= FTF_NOPS;
|
||||
}
|
||||
|
||||
inbuf_init(&memresvbuf,
|
||||
blob + off_mem_rsvmap, blob + totalsize);
|
||||
inbuf_init(&dtbuf, blob + off_dt, blob + totalsize);
|
||||
if (size_str >= 0)
|
||||
inbuf_init(&strbuf, blob + off_str, blob + off_str + size_str);
|
||||
else
|
||||
inbuf_init(&strbuf, blob + off_str, blob + totalsize);
|
||||
|
||||
reservelist = flat_read_mem_reserve(&memresvbuf);
|
||||
|
||||
val = flat_read_word(&dtbuf);
|
||||
|
||||
if (val != FDT_BEGIN_NODE)
|
||||
die("Device tree blob doesn't begin with FDT_BEGIN_NODE (begins with 0x%08x)\n", val);
|
||||
|
||||
tree = unflatten_tree(&dtbuf, &strbuf, "", flags);
|
||||
|
||||
val = flat_read_word(&dtbuf);
|
||||
if (val != FDT_END)
|
||||
die("Device tree blob doesn't end with FDT_END\n");
|
||||
|
||||
free(blob);
|
||||
|
||||
return build_boot_info(reservelist, tree);
|
||||
}
|
||||
94
arch/powerpc/boot/dtc-src/fstree.c
Normal file
94
arch/powerpc/boot/dtc-src/fstree.c
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "dtc.h"
|
||||
|
||||
#include <dirent.h>
|
||||
#include <sys/stat.h>
|
||||
|
||||
static struct node *read_fstree(const char *dirname)
|
||||
{
|
||||
DIR *d;
|
||||
struct dirent *de;
|
||||
struct stat st;
|
||||
struct node *tree;
|
||||
|
||||
d = opendir(dirname);
|
||||
if (! d)
|
||||
die("opendir(): %s\n", strerror(errno));
|
||||
|
||||
tree = build_node(NULL, NULL);
|
||||
|
||||
while ((de = readdir(d)) != NULL) {
|
||||
char *tmpnam;
|
||||
|
||||
if (streq(de->d_name, ".")
|
||||
|| streq(de->d_name, ".."))
|
||||
continue;
|
||||
|
||||
tmpnam = join_path(dirname, de->d_name);
|
||||
|
||||
if (lstat(tmpnam, &st) < 0)
|
||||
die("stat(%s): %s\n", tmpnam, strerror(errno));
|
||||
|
||||
if (S_ISREG(st.st_mode)) {
|
||||
struct property *prop;
|
||||
FILE *pfile;
|
||||
|
||||
pfile = fopen(tmpnam, "r");
|
||||
if (! pfile) {
|
||||
fprintf(stderr,
|
||||
"WARNING: Cannot open %s: %s\n",
|
||||
tmpnam, strerror(errno));
|
||||
} else {
|
||||
prop = build_property(strdup(de->d_name),
|
||||
data_copy_file(pfile,
|
||||
st.st_size),
|
||||
NULL);
|
||||
add_property(tree, prop);
|
||||
fclose(pfile);
|
||||
}
|
||||
} else if (S_ISDIR(st.st_mode)) {
|
||||
struct node *newchild;
|
||||
|
||||
newchild = read_fstree(tmpnam);
|
||||
newchild = name_node(newchild, strdup(de->d_name),
|
||||
NULL);
|
||||
add_child(tree, newchild);
|
||||
}
|
||||
|
||||
free(tmpnam);
|
||||
}
|
||||
|
||||
return tree;
|
||||
}
|
||||
|
||||
struct boot_info *dt_from_fs(const char *dirname)
|
||||
{
|
||||
struct node *tree;
|
||||
|
||||
tree = read_fstree(dirname);
|
||||
tree = name_node(tree, "", NULL);
|
||||
|
||||
fill_fullpaths(tree, "");
|
||||
|
||||
return build_boot_info(NULL, tree);
|
||||
}
|
||||
|
||||
305
arch/powerpc/boot/dtc-src/livetree.c
Normal file
305
arch/powerpc/boot/dtc-src/livetree.c
Normal file
|
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "dtc.h"
|
||||
|
||||
/*
|
||||
* Tree building functions
|
||||
*/
|
||||
|
||||
struct property *build_property(char *name, struct data val, char *label)
|
||||
{
|
||||
struct property *new = xmalloc(sizeof(*new));
|
||||
|
||||
new->name = name;
|
||||
new->val = val;
|
||||
|
||||
new->next = NULL;
|
||||
|
||||
new->label = label;
|
||||
|
||||
return new;
|
||||
}
|
||||
|
||||
struct property *chain_property(struct property *first, struct property *list)
|
||||
{
|
||||
assert(first->next == NULL);
|
||||
|
||||
first->next = list;
|
||||
return first;
|
||||
}
|
||||
|
||||
struct property *reverse_properties(struct property *first)
|
||||
{
|
||||
struct property *p = first;
|
||||
struct property *head = NULL;
|
||||
struct property *next;
|
||||
|
||||
while (p) {
|
||||
next = p->next;
|
||||
p->next = head;
|
||||
head = p;
|
||||
p = next;
|
||||
}
|
||||
return head;
|
||||
}
|
||||
|
||||
struct node *build_node(struct property *proplist, struct node *children)
|
||||
{
|
||||
struct node *new = xmalloc(sizeof(*new));
|
||||
struct node *child;
|
||||
|
||||
memset(new, 0, sizeof(*new));
|
||||
|
||||
new->proplist = reverse_properties(proplist);
|
||||
new->children = children;
|
||||
|
||||
for_each_child(new, child) {
|
||||
child->parent = new;
|
||||
}
|
||||
|
||||
return new;
|
||||
}
|
||||
|
||||
struct node *name_node(struct node *node, char *name, char * label)
|
||||
{
|
||||
assert(node->name == NULL);
|
||||
|
||||
node->name = name;
|
||||
|
||||
node->label = label;
|
||||
|
||||
return node;
|
||||
}
|
||||
|
||||
struct node *chain_node(struct node *first, struct node *list)
|
||||
{
|
||||
assert(first->next_sibling == NULL);
|
||||
|
||||
first->next_sibling = list;
|
||||
return first;
|
||||
}
|
||||
|
||||
void add_property(struct node *node, struct property *prop)
|
||||
{
|
||||
struct property **p;
|
||||
|
||||
prop->next = NULL;
|
||||
|
||||
p = &node->proplist;
|
||||
while (*p)
|
||||
p = &((*p)->next);
|
||||
|
||||
*p = prop;
|
||||
}
|
||||
|
||||
void add_child(struct node *parent, struct node *child)
|
||||
{
|
||||
struct node **p;
|
||||
|
||||
child->next_sibling = NULL;
|
||||
|
||||
p = &parent->children;
|
||||
while (*p)
|
||||
p = &((*p)->next_sibling);
|
||||
|
||||
*p = child;
|
||||
}
|
||||
|
||||
struct reserve_info *build_reserve_entry(u64 address, u64 size, char *label)
|
||||
{
|
||||
struct reserve_info *new = xmalloc(sizeof(*new));
|
||||
|
||||
new->re.address = address;
|
||||
new->re.size = size;
|
||||
|
||||
new->next = NULL;
|
||||
|
||||
new->label = label;
|
||||
|
||||
return new;
|
||||
}
|
||||
|
||||
struct reserve_info *chain_reserve_entry(struct reserve_info *first,
|
||||
struct reserve_info *list)
|
||||
{
|
||||
assert(first->next == NULL);
|
||||
|
||||
first->next = list;
|
||||
return first;
|
||||
}
|
||||
|
||||
struct reserve_info *add_reserve_entry(struct reserve_info *list,
|
||||
struct reserve_info *new)
|
||||
{
|
||||
struct reserve_info *last;
|
||||
|
||||
new->next = NULL;
|
||||
|
||||
if (! list)
|
||||
return new;
|
||||
|
||||
for (last = list; last->next; last = last->next)
|
||||
;
|
||||
|
||||
last->next = new;
|
||||
|
||||
return list;
|
||||
}
|
||||
|
||||
struct boot_info *build_boot_info(struct reserve_info *reservelist,
|
||||
struct node *tree)
|
||||
{
|
||||
struct boot_info *bi;
|
||||
|
||||
bi = xmalloc(sizeof(*bi));
|
||||
bi->reservelist = reservelist;
|
||||
bi->dt = tree;
|
||||
|
||||
return bi;
|
||||
}
|
||||
|
||||
/*
|
||||
* Tree accessor functions
|
||||
*/
|
||||
|
||||
const char *get_unitname(struct node *node)
|
||||
{
|
||||
if (node->name[node->basenamelen] == '\0')
|
||||
return "";
|
||||
else
|
||||
return node->name + node->basenamelen + 1;
|
||||
}
|
||||
|
||||
struct property *get_property(struct node *node, const char *propname)
|
||||
{
|
||||
struct property *prop;
|
||||
|
||||
for_each_property(node, prop)
|
||||
if (streq(prop->name, propname))
|
||||
return prop;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cell_t propval_cell(struct property *prop)
|
||||
{
|
||||
assert(prop->val.len == sizeof(cell_t));
|
||||
return be32_to_cpu(*((cell_t *)prop->val.val));
|
||||
}
|
||||
|
||||
struct node *get_subnode(struct node *node, const char *nodename)
|
||||
{
|
||||
struct node *child;
|
||||
|
||||
for_each_child(node, child)
|
||||
if (streq(child->name, nodename))
|
||||
return child;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct node *get_node_by_path(struct node *tree, const char *path)
|
||||
{
|
||||
const char *p;
|
||||
struct node *child;
|
||||
|
||||
if (!path || ! (*path))
|
||||
return tree;
|
||||
|
||||
while (path[0] == '/')
|
||||
path++;
|
||||
|
||||
p = strchr(path, '/');
|
||||
|
||||
for_each_child(tree, child) {
|
||||
if (p && strneq(path, child->name, p-path))
|
||||
return get_node_by_path(child, p+1);
|
||||
else if (!p && streq(path, child->name))
|
||||
return child;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct node *get_node_by_label(struct node *tree, const char *label)
|
||||
{
|
||||
struct node *child, *node;
|
||||
|
||||
assert(label && (strlen(label) > 0));
|
||||
|
||||
if (tree->label && streq(tree->label, label))
|
||||
return tree;
|
||||
|
||||
for_each_child(tree, child) {
|
||||
node = get_node_by_label(child, label);
|
||||
if (node)
|
||||
return node;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct node *get_node_by_phandle(struct node *tree, cell_t phandle)
|
||||
{
|
||||
struct node *child, *node;
|
||||
|
||||
assert((phandle != 0) && (phandle != -1));
|
||||
|
||||
if (tree->phandle == phandle)
|
||||
return tree;
|
||||
|
||||
for_each_child(tree, child) {
|
||||
node = get_node_by_phandle(child, phandle);
|
||||
if (node)
|
||||
return node;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct node *get_node_by_ref(struct node *tree, const char *ref)
|
||||
{
|
||||
if (ref[0] == '/')
|
||||
return get_node_by_path(tree, ref);
|
||||
else
|
||||
return get_node_by_label(tree, ref);
|
||||
}
|
||||
|
||||
cell_t get_node_phandle(struct node *root, struct node *node)
|
||||
{
|
||||
static cell_t phandle = 1; /* FIXME: ick, static local */
|
||||
|
||||
if ((node->phandle != 0) && (node->phandle != -1))
|
||||
return node->phandle;
|
||||
|
||||
assert(! get_property(node, "linux,phandle"));
|
||||
|
||||
while (get_node_by_phandle(root, phandle))
|
||||
phandle++;
|
||||
|
||||
node->phandle = phandle;
|
||||
add_property(node,
|
||||
build_property("linux,phandle",
|
||||
data_append_cell(empty_data, phandle),
|
||||
NULL));
|
||||
|
||||
return node->phandle;
|
||||
}
|
||||
105
arch/powerpc/boot/dtc-src/srcpos.c
Normal file
105
arch/powerpc/boot/dtc-src/srcpos.c
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Copyright 2007 Jon Loeliger, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "dtc.h"
|
||||
#include "srcpos.h"
|
||||
|
||||
|
||||
/*
|
||||
* Record the complete unique set of opened file names.
|
||||
* Primarily used to cache source position file names.
|
||||
*/
|
||||
#define MAX_N_FILE_NAMES (100)
|
||||
|
||||
const char *file_names[MAX_N_FILE_NAMES];
|
||||
static int n_file_names = 0;
|
||||
|
||||
/*
|
||||
* Like yylineno, this is the current open file pos.
|
||||
*/
|
||||
|
||||
int srcpos_filenum = -1;
|
||||
|
||||
|
||||
|
||||
FILE *dtc_open_file(const char *fname)
|
||||
{
|
||||
FILE *f;
|
||||
|
||||
if (lookup_file_name(fname, 1) < 0)
|
||||
die("Too many files opened\n");
|
||||
|
||||
if (streq(fname, "-"))
|
||||
f = stdin;
|
||||
else
|
||||
f = fopen(fname, "r");
|
||||
|
||||
if (! f)
|
||||
die("Couldn't open \"%s\": %s\n", fname, strerror(errno));
|
||||
|
||||
return f;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Locate and optionally add filename fname in the file_names[] array.
|
||||
*
|
||||
* If the filename is currently not in the array and the boolean
|
||||
* add_it is non-zero, an attempt to add the filename will be made.
|
||||
*
|
||||
* Returns;
|
||||
* Index [0..MAX_N_FILE_NAMES) where the filename is kept
|
||||
* -1 if the name can not be recorded
|
||||
*/
|
||||
|
||||
int lookup_file_name(const char *fname, int add_it)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < n_file_names; i++) {
|
||||
if (strcmp(file_names[i], fname) == 0)
|
||||
return i;
|
||||
}
|
||||
|
||||
if (add_it) {
|
||||
if (n_file_names < MAX_N_FILE_NAMES) {
|
||||
file_names[n_file_names] = strdup(fname);
|
||||
return n_file_names++;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
const char *srcpos_filename_for_num(int filenum)
|
||||
{
|
||||
if (0 <= filenum && filenum < n_file_names) {
|
||||
return file_names[filenum];
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
const char *srcpos_get_filename(void)
|
||||
{
|
||||
return srcpos_filename_for_num(srcpos_filenum);
|
||||
}
|
||||
75
arch/powerpc/boot/dtc-src/srcpos.h
Normal file
75
arch/powerpc/boot/dtc-src/srcpos.h
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* Copyright 2007 Jon Loeliger, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Augment the standard YYLTYPE with a filenum index into an
|
||||
* array of all opened filenames.
|
||||
*/
|
||||
|
||||
#if ! defined(YYLTYPE) && ! defined(YYLTYPE_IS_DECLARED)
|
||||
typedef struct YYLTYPE {
|
||||
int first_line;
|
||||
int first_column;
|
||||
int last_line;
|
||||
int last_column;
|
||||
int filenum;
|
||||
} YYLTYPE;
|
||||
|
||||
#define YYLTYPE_IS_DECLARED 1
|
||||
#define YYLTYPE_IS_TRIVIAL 1
|
||||
#endif
|
||||
|
||||
/* Cater to old parser templates. */
|
||||
#ifndef YYID
|
||||
#define YYID(n) (n)
|
||||
#endif
|
||||
|
||||
#define YYLLOC_DEFAULT(Current, Rhs, N) \
|
||||
do \
|
||||
if (YYID (N)) \
|
||||
{ \
|
||||
(Current).first_line = YYRHSLOC (Rhs, 1).first_line; \
|
||||
(Current).first_column = YYRHSLOC (Rhs, 1).first_column; \
|
||||
(Current).last_line = YYRHSLOC (Rhs, N).last_line; \
|
||||
(Current).last_column = YYRHSLOC (Rhs, N).last_column; \
|
||||
(Current).filenum = YYRHSLOC (Rhs, N).filenum; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(Current).first_line = (Current).last_line = \
|
||||
YYRHSLOC (Rhs, 0).last_line; \
|
||||
(Current).first_column = (Current).last_column = \
|
||||
YYRHSLOC (Rhs, 0).last_column; \
|
||||
(Current).filenum = YYRHSLOC (Rhs, 0).filenum; \
|
||||
} \
|
||||
while (YYID (0))
|
||||
|
||||
|
||||
|
||||
extern void yyerror(char const *);
|
||||
|
||||
extern int srcpos_filenum;
|
||||
|
||||
extern int push_input_file(const char *filename);
|
||||
extern int pop_input_file(void);
|
||||
|
||||
extern FILE *dtc_open_file(const char *fname);
|
||||
extern int lookup_file_name(const char *fname, int add_it);
|
||||
extern const char *srcpos_filename_for_num(int filenum);
|
||||
const char *srcpos_get_filename(void);
|
||||
275
arch/powerpc/boot/dtc-src/treesource.c
Normal file
275
arch/powerpc/boot/dtc-src/treesource.c
Normal file
|
|
@ -0,0 +1,275 @@
|
|||
/*
|
||||
* (C) Copyright David Gibson <dwg@au1.ibm.com>, IBM Corporation. 2005.
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include "dtc.h"
|
||||
#include "srcpos.h"
|
||||
|
||||
extern FILE *yyin;
|
||||
extern int yyparse(void);
|
||||
extern void yyerror(char const *);
|
||||
|
||||
struct boot_info *the_boot_info;
|
||||
|
||||
struct boot_info *dt_from_source(const char *fname)
|
||||
{
|
||||
the_boot_info = NULL;
|
||||
|
||||
push_input_file(fname);
|
||||
|
||||
if (yyparse() != 0)
|
||||
return NULL;
|
||||
|
||||
fill_fullpaths(the_boot_info->dt, "");
|
||||
|
||||
return the_boot_info;
|
||||
}
|
||||
|
||||
static void write_prefix(FILE *f, int level)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < level; i++)
|
||||
fputc('\t', f);
|
||||
}
|
||||
|
||||
int isstring(char c)
|
||||
{
|
||||
return (isprint(c)
|
||||
|| (c == '\0')
|
||||
|| strchr("\a\b\t\n\v\f\r", c));
|
||||
}
|
||||
|
||||
static void write_propval_string(FILE *f, struct data val)
|
||||
{
|
||||
const char *str = val.val;
|
||||
int i;
|
||||
int newchunk = 1;
|
||||
struct marker *m = val.markers;
|
||||
|
||||
assert(str[val.len-1] == '\0');
|
||||
|
||||
for (i = 0; i < (val.len-1); i++) {
|
||||
char c = str[i];
|
||||
|
||||
if (newchunk) {
|
||||
while (m && (m->offset <= i)) {
|
||||
if (m->type == LABEL) {
|
||||
assert(m->offset == i);
|
||||
fprintf(f, "%s: ", m->ref);
|
||||
}
|
||||
m = m->next;
|
||||
}
|
||||
fprintf(f, "\"");
|
||||
newchunk = 0;
|
||||
}
|
||||
|
||||
switch (c) {
|
||||
case '\a':
|
||||
fprintf(f, "\\a");
|
||||
break;
|
||||
case '\b':
|
||||
fprintf(f, "\\b");
|
||||
break;
|
||||
case '\t':
|
||||
fprintf(f, "\\t");
|
||||
break;
|
||||
case '\n':
|
||||
fprintf(f, "\\n");
|
||||
break;
|
||||
case '\v':
|
||||
fprintf(f, "\\v");
|
||||
break;
|
||||
case '\f':
|
||||
fprintf(f, "\\f");
|
||||
break;
|
||||
case '\r':
|
||||
fprintf(f, "\\r");
|
||||
break;
|
||||
case '\\':
|
||||
fprintf(f, "\\\\");
|
||||
break;
|
||||
case '\"':
|
||||
fprintf(f, "\\\"");
|
||||
break;
|
||||
case '\0':
|
||||
fprintf(f, "\", ");
|
||||
newchunk = 1;
|
||||
break;
|
||||
default:
|
||||
if (isprint(c))
|
||||
fprintf(f, "%c", c);
|
||||
else
|
||||
fprintf(f, "\\x%02hhx", c);
|
||||
}
|
||||
}
|
||||
fprintf(f, "\"");
|
||||
|
||||
/* Wrap up any labels at the end of the value */
|
||||
for_each_marker_of_type(m, LABEL) {
|
||||
assert (m->offset == val.len);
|
||||
fprintf(f, " %s:", m->ref);
|
||||
}
|
||||
}
|
||||
|
||||
static void write_propval_cells(FILE *f, struct data val)
|
||||
{
|
||||
void *propend = val.val + val.len;
|
||||
cell_t *cp = (cell_t *)val.val;
|
||||
struct marker *m = val.markers;
|
||||
|
||||
fprintf(f, "<");
|
||||
for (;;) {
|
||||
while (m && (m->offset <= ((char *)cp - val.val))) {
|
||||
if (m->type == LABEL) {
|
||||
assert(m->offset == ((char *)cp - val.val));
|
||||
fprintf(f, "%s: ", m->ref);
|
||||
}
|
||||
m = m->next;
|
||||
}
|
||||
|
||||
fprintf(f, "0x%x", be32_to_cpu(*cp++));
|
||||
if ((void *)cp >= propend)
|
||||
break;
|
||||
fprintf(f, " ");
|
||||
}
|
||||
|
||||
/* Wrap up any labels at the end of the value */
|
||||
for_each_marker_of_type(m, LABEL) {
|
||||
assert (m->offset == val.len);
|
||||
fprintf(f, " %s:", m->ref);
|
||||
}
|
||||
fprintf(f, ">");
|
||||
}
|
||||
|
||||
static void write_propval_bytes(FILE *f, struct data val)
|
||||
{
|
||||
void *propend = val.val + val.len;
|
||||
const char *bp = val.val;
|
||||
struct marker *m = val.markers;
|
||||
|
||||
fprintf(f, "[");
|
||||
for (;;) {
|
||||
while (m && (m->offset == (bp-val.val))) {
|
||||
if (m->type == LABEL)
|
||||
fprintf(f, "%s: ", m->ref);
|
||||
m = m->next;
|
||||
}
|
||||
|
||||
fprintf(f, "%02hhx", *bp++);
|
||||
if ((void *)bp >= propend)
|
||||
break;
|
||||
fprintf(f, " ");
|
||||
}
|
||||
|
||||
/* Wrap up any labels at the end of the value */
|
||||
for_each_marker_of_type(m, LABEL) {
|
||||
assert (m->offset == val.len);
|
||||
fprintf(f, " %s:", m->ref);
|
||||
}
|
||||
fprintf(f, "]");
|
||||
}
|
||||
|
||||
static void write_propval(FILE *f, struct property *prop)
|
||||
{
|
||||
int len = prop->val.len;
|
||||
const char *p = prop->val.val;
|
||||
struct marker *m = prop->val.markers;
|
||||
int nnotstring = 0, nnul = 0;
|
||||
int nnotstringlbl = 0, nnotcelllbl = 0;
|
||||
int i;
|
||||
|
||||
if (len == 0) {
|
||||
fprintf(f, ";\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (! isstring(p[i]))
|
||||
nnotstring++;
|
||||
if (p[i] == '\0')
|
||||
nnul++;
|
||||
}
|
||||
|
||||
for_each_marker_of_type(m, LABEL) {
|
||||
if ((m->offset > 0) && (prop->val.val[m->offset - 1] != '\0'))
|
||||
nnotstringlbl++;
|
||||
if ((m->offset % sizeof(cell_t)) != 0)
|
||||
nnotcelllbl++;
|
||||
}
|
||||
|
||||
fprintf(f, " = ");
|
||||
if ((p[len-1] == '\0') && (nnotstring == 0) && (nnul < (len-nnul))
|
||||
&& (nnotstringlbl == 0)) {
|
||||
write_propval_string(f, prop->val);
|
||||
} else if (((len % sizeof(cell_t)) == 0) && (nnotcelllbl == 0)) {
|
||||
write_propval_cells(f, prop->val);
|
||||
} else {
|
||||
write_propval_bytes(f, prop->val);
|
||||
}
|
||||
|
||||
fprintf(f, ";\n");
|
||||
}
|
||||
|
||||
static void write_tree_source_node(FILE *f, struct node *tree, int level)
|
||||
{
|
||||
struct property *prop;
|
||||
struct node *child;
|
||||
|
||||
write_prefix(f, level);
|
||||
if (tree->label)
|
||||
fprintf(f, "%s: ", tree->label);
|
||||
if (tree->name && (*tree->name))
|
||||
fprintf(f, "%s {\n", tree->name);
|
||||
else
|
||||
fprintf(f, "/ {\n");
|
||||
|
||||
for_each_property(tree, prop) {
|
||||
write_prefix(f, level+1);
|
||||
if (prop->label)
|
||||
fprintf(f, "%s: ", prop->label);
|
||||
fprintf(f, "%s", prop->name);
|
||||
write_propval(f, prop);
|
||||
}
|
||||
for_each_child(tree, child) {
|
||||
fprintf(f, "\n");
|
||||
write_tree_source_node(f, child, level+1);
|
||||
}
|
||||
write_prefix(f, level);
|
||||
fprintf(f, "};\n");
|
||||
}
|
||||
|
||||
|
||||
void dt_to_source(FILE *f, struct boot_info *bi)
|
||||
{
|
||||
struct reserve_info *re;
|
||||
|
||||
fprintf(f, "/dts-v1/;\n\n");
|
||||
|
||||
for (re = bi->reservelist; re; re = re->next) {
|
||||
if (re->label)
|
||||
fprintf(f, "%s: ", re->label);
|
||||
fprintf(f, "/memreserve/\t0x%016llx 0x%016llx;\n",
|
||||
(unsigned long long)re->re.address,
|
||||
(unsigned long long)re->re.size);
|
||||
}
|
||||
|
||||
write_tree_source_node(f, bi->dt, 0);
|
||||
}
|
||||
|
||||
1
arch/powerpc/boot/dtc-src/version_gen.h
Normal file
1
arch/powerpc/boot/dtc-src/version_gen.h
Normal file
|
|
@ -0,0 +1 @@
|
|||
#define DTC_VERSION "DTC 1.0.0-gd6f9b62f"
|
||||
184
arch/powerpc/boot/dts/adder875-redboot.dts
Normal file
184
arch/powerpc/boot/dts/adder875-redboot.dts
Normal file
|
|
@ -0,0 +1,184 @@
|
|||
/*
|
||||
* Device Tree Source for MPC885 ADS running RedBoot
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "Analogue & Micro Adder MPC875";
|
||||
compatible = "analogue-and-micro,adder875";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
console = &console;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,875@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <16>;
|
||||
i-cache-line-size = <16>;
|
||||
d-cache-size = <8192>;
|
||||
i-cache-size = <8192>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <15 2>; // decrementer interrupt
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus@fa200100 {
|
||||
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xfa200100 0x40>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xfe000000 0x00800000
|
||||
2 0 0xfa100000 0x00008000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@fa200000 {
|
||||
compatible = "fsl,mpc875-immr", "fsl,pq1-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xfa200000 0x00004000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary until get_immrbase() is fixed.
|
||||
reg = <0xfa200000 0x4000>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <0xe00 0x188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0xe00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
eth1: ethernet@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0x1e00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x24>;
|
||||
compatible = "fsl,mpc875-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc875-cpm", "fsl,cpm1", "simple-bus";
|
||||
interrupts = <0>; // cpm error interrupt
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
reg = <0x9c0 0x40>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc875-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x9f0 0x10>;
|
||||
};
|
||||
|
||||
CPM_PIC: interrupt-controller@930 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0x930 0x20>;
|
||||
compatible = "fsl,mpc875-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
console: serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc875-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <0xa80 0x10 0x3e80 0x40>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x0090>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &console;
|
||||
};
|
||||
};
|
||||
183
arch/powerpc/boot/dts/adder875-uboot.dts
Normal file
183
arch/powerpc/boot/dts/adder875-uboot.dts
Normal file
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* Device Tree Source for MPC885 ADS running U-Boot
|
||||
*
|
||||
* Copyright 2006 MontaVista Software, Inc.
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "Analogue & Micro Adder MPC875";
|
||||
compatible = "analogue-and-micro,adder875";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
console = &console;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,875@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <16>;
|
||||
i-cache-line-size = <16>;
|
||||
d-cache-size = <8192>;
|
||||
i-cache-size = <8192>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <15 2>; // decrementer interrupt
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus@ff000100 {
|
||||
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xff000100 0x40>;
|
||||
|
||||
ranges = <
|
||||
0 0 0xfe000000 0x01000000
|
||||
>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@ff000000 {
|
||||
compatible = "fsl,mpc875-immr", "fsl,pq1-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff000000 0x00004000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary until get_immrbase() is fixed.
|
||||
reg = <0xff000000 0x4000>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc875-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <0xe00 0x188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0xe00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
eth1: ethernet@1e00 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc875-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <0x1e00 0x188>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <7 1>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x24>;
|
||||
compatible = "fsl,mpc875-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc875-cpm", "fsl,cpm1", "simple-bus";
|
||||
interrupts = <0>; // cpm error interrupt
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
reg = <0x9c0 0x40>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc875-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x9f0 0x10>;
|
||||
};
|
||||
|
||||
CPM_PIC: interrupt-controller@930 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0x930 0x20>;
|
||||
compatible = "fsl,mpc875-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
console: serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc875-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <0xa80 0x10 0x3e80 0x40>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x0090>;
|
||||
current-speed = <115200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &console;
|
||||
};
|
||||
};
|
||||
|
|
@ -16,14 +16,24 @@ / {
|
|||
#size-cells = <1>;
|
||||
model = "amcc,bamboo";
|
||||
compatible = "amcc,bamboo";
|
||||
dcr-parent = <&/cpus/PowerPC,440EP@0>;
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
serial2 = &UART2;
|
||||
serial3 = &UART3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,440EP@0 {
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440EP";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
|
|
@ -126,7 +136,6 @@ EBC0: ebc {
|
|||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
ranges;
|
||||
interrupts = <5 1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
};
|
||||
|
|
@ -238,11 +247,56 @@ EMAC1: ethernet@ef600f00 {
|
|||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
||||
usb@ef601000 {
|
||||
compatible = "ohci-be";
|
||||
reg = <ef601000 80>;
|
||||
interrupts = <8 1 9 1>;
|
||||
interrupt-parent = < &UIC1 >;
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <0 eec00000 8 /* Config space access */
|
||||
0 eed00000 4 /* IACK */
|
||||
0 eed00000 4 /* Special cycle */
|
||||
0 ef400000 40>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <02000000 0 a0000000 0 a0000000 0 20000000
|
||||
01000000 0 00000000 0 e8000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
/* Bamboo has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <f800 0 0 0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 0 &UIC0 1c 8
|
||||
|
||||
/* IDSEL 2 */
|
||||
1000 0 0 0 &UIC0 1b 8
|
||||
|
||||
/* IDSEL 3 */
|
||||
1800 0 0 0 &UIC0 1a 8
|
||||
|
||||
/* IDSEL 4 */
|
||||
2000 0 0 0 &UIC0 19 8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
234
arch/powerpc/boot/dts/cm5200.dts
Normal file
234
arch/powerpc/boot/dts/cm5200.dts
Normal file
|
|
@ -0,0 +1,234 @@
|
|||
/*
|
||||
* CM5200 board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: Do not depend on this tree layout remaining static just yet.
|
||||
* The MPC5200 device tree conventions are still in flux
|
||||
* Keep an eye on the linuxppc-dev mailing list for more details
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "schindler,cm5200";
|
||||
compatible = "schindler,cm5200";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 04000000>; // 64MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
||||
reg = <f0000000 00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||
reg = <200 38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: pic@500 {
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <500 80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <600 10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <610 10>;
|
||||
interrupts = <1 a 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <620 10>;
|
||||
interrupts = <1 b 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <630 10>;
|
||||
interrupts = <1 c 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <640 10>;
|
||||
interrupts = <1 d 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <650 10>;
|
||||
interrupts = <1 e 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <660 10>;
|
||||
interrupts = <1 f 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <670 10>;
|
||||
interrupts = <1 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
reg = <800 100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <c00 40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <f00 20>;
|
||||
interrupts = <2 d 0 2 e 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 a 0 3 b 0
|
||||
3 c 0 3 d 0 3 e 0 3 f 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
reg = <2000 100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
serial@2200 { // PSC2
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <1>; // Logical port assignment
|
||||
reg = <2200 100>;
|
||||
interrupts = <2 2 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
serial@2400 { // PSC3
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <2>; // Logical port assignment
|
||||
reg = <2400 100>;
|
||||
interrupts = <2 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
serial@2c00 { // PSC6
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <5>; // Logical port assignment
|
||||
reg = <2c00 100>;
|
||||
interrupts = <2 4 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <3000 800>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <8000 4000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -16,14 +16,22 @@ / {
|
|||
#size-cells = <1>;
|
||||
model = "ibm,ebony";
|
||||
compatible = "ibm,ebony";
|
||||
dcr-parent = <&/cpus/PowerPC,440GP@0>;
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,440GP@0 {
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440GP";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; // Filled in by zImage
|
||||
timebase-frequency = <0>; // Filled in by zImage
|
||||
|
|
@ -150,9 +158,10 @@ partition@0 {
|
|||
};
|
||||
};
|
||||
|
||||
ds1743@1,0 {
|
||||
nvram@1,0 {
|
||||
/* NVRAM & RTC */
|
||||
compatible = "ds1743";
|
||||
compatible = "ds1743-nvram";
|
||||
#bytes = <2000>;
|
||||
reg = <1 0 2000>;
|
||||
};
|
||||
|
||||
|
|
@ -284,12 +293,43 @@ GPT0: gpt@40000a00 {
|
|||
|
||||
};
|
||||
|
||||
PCIX0: pci@1234 {
|
||||
PCIX0: pci@20ec00000 {
|
||||
device_type = "pci";
|
||||
/* FIXME */
|
||||
reg = <2 0ec00000 8
|
||||
2 0ec80000 f0
|
||||
2 0ec80100 fc>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
|
||||
primary;
|
||||
reg = <2 0ec00000 8 /* Config space access */
|
||||
0 0 0 /* no IACK cycles */
|
||||
2 0ed00000 4 /* Special cycles */
|
||||
2 0ec80000 f0 /* Internal registers */
|
||||
2 0ec80100 fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 00000003 80000000 0 80000000
|
||||
01000000 0 00000000 00000002 08000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
/* Ebony has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <f800 0 0 0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 0 &UIC0 17 8
|
||||
|
||||
/* IDSEL 2 */
|
||||
1000 0 0 0 &UIC0 18 8
|
||||
|
||||
/* IDSEL 3 */
|
||||
1800 0 0 0 &UIC0 19 8
|
||||
|
||||
/* IDSEL 4 */
|
||||
2000 0 0 0 &UIC0 1a 8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
228
arch/powerpc/boot/dts/ep405.dts
Normal file
228
arch/powerpc/boot/dts/ep405.dts
Normal file
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
* Device Tree Source for EP405
|
||||
*
|
||||
* Copyright 2007 IBM Corp.
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "ep405";
|
||||
compatible = "ep405";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405GP";
|
||||
reg = <0>;
|
||||
clock-frequency = <bebc200>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <4000>;
|
||||
d-cache-size = <4000>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 9>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405gp";
|
||||
dcr-reg = <010 2>;
|
||||
};
|
||||
|
||||
MAL: mcmal {
|
||||
compatible = "ibm,mcmal-405gp", "ibm,mcmal";
|
||||
dcr-reg = <180 62>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
b 4 /* TXEOB */
|
||||
c 4 /* RXEOB */
|
||||
a 4 /* SERR */
|
||||
d 4 /* TXDE */
|
||||
e 4 /* RXDE */>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <ef600000 ef600000 a00000>;
|
||||
dcr-reg = <0a0 5>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <2580>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600400 8>;
|
||||
virtual-reg = <ef600400>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <2580>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
};
|
||||
|
||||
IIC: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405gp", "ibm,iic";
|
||||
reg = <ef600500 11>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
};
|
||||
|
||||
GPIO: gpio@ef600700 {
|
||||
compatible = "ibm,gpio-405gp";
|
||||
reg = <ef600700 20>;
|
||||
};
|
||||
|
||||
EMAC: ethernet@ef600800 {
|
||||
linux,network-index = <0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405gp", "ibm,emac";
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <
|
||||
f 4 /* Ethernet */
|
||||
9 4 /* Ethernet Wake Up */>;
|
||||
local-mac-address = [000000000000]; /* Filled in by zImage */
|
||||
reg = <ef600800 70>;
|
||||
mal-device = <&MAL>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405gp", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
||||
/* The ranges property is supplied by the bootwrapper
|
||||
* and is based on the firmware's configuration of the
|
||||
* EBC bridge
|
||||
*/
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
/* NVRAM and RTC */
|
||||
nvrtc@4,200000 {
|
||||
compatible = "ds1742";
|
||||
reg = <4 200000 0>; /* size fixed up by zImage */
|
||||
};
|
||||
|
||||
/* "BCSR" CPLD contains a PCI irq controller */
|
||||
bcsr@4,0 {
|
||||
compatible = "ep405-bcsr";
|
||||
reg = <4 0 10>;
|
||||
interrupt-controller;
|
||||
/* Routing table */
|
||||
irq-routing = [ 00 /* SYSERR */
|
||||
01 /* STTM */
|
||||
01 /* RTC */
|
||||
01 /* FENET */
|
||||
02 /* NB PCIIRQ mux ? */
|
||||
03 /* SB Winbond 8259 ? */
|
||||
04 /* Serial Ring */
|
||||
05 /* USB (ep405pc) */
|
||||
06 /* XIRQ 0 */
|
||||
06 /* XIRQ 1 */
|
||||
06 /* XIRQ 2 */
|
||||
06 /* XIRQ 3 */
|
||||
06 /* XIRQ 4 */
|
||||
06 /* XIRQ 5 */
|
||||
06 /* XIRQ 6 */
|
||||
07]; /* Reserved */
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <eec00000 8 /* Config space access */
|
||||
eed80000 4 /* IACK */
|
||||
eed80000 4 /* Special cycle */
|
||||
ef480000 40>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e8000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
|
||||
/* That's all I know about IRQs on that thing ... */
|
||||
interrupt-map-mask = <f800 0 0 0>;
|
||||
interrupt-map = <
|
||||
/* USB */
|
||||
7000 0 0 0 &UIC0 1e 8 /* IRQ5 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
};
|
||||
};
|
||||
207
arch/powerpc/boot/dts/ep8248e.dts
Normal file
207
arch/powerpc/boot/dts/ep8248e.dts
Normal file
|
|
@ -0,0 +1,207 @@
|
|||
/*
|
||||
* Device Tree for the Embedded Planet EP8248E board running PlanetCore.
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "EP8248E";
|
||||
compatible = "fsl,ep8248e";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
planetcore-SMC1 = &smc1;
|
||||
planetcore-SCC1 = &scc1;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
serial0 = &smc1;
|
||||
serial1 = &scc1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8248@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <16384>;
|
||||
i-cache-size = <16384>;
|
||||
timebase-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
localbus@f0010100 {
|
||||
compatible = "fsl,mpc8248-localbus",
|
||||
"fsl,pq2-localbus",
|
||||
"simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xf0010100 0x40>;
|
||||
|
||||
ranges = <0 0 0xfc000000 0x04000000
|
||||
1 0 0xfa000000 0x00008000>;
|
||||
|
||||
flash@0,3800000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x3800000 0x800000>;
|
||||
bank-width = <4>;
|
||||
device-width = <2>;
|
||||
};
|
||||
|
||||
bcsr@1,0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <1 0 0x10>;
|
||||
compatible = "fsl,ep8248e-bcsr";
|
||||
ranges;
|
||||
|
||||
mdio {
|
||||
device_type = "mdio";
|
||||
compatible = "fsl,ep8248e-mdio-bitbang";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1 8 1>;
|
||||
|
||||
PHY0: ethernet-phy@0 {
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
||||
PHY1: ethernet-phy@1 {
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>;
|
||||
};
|
||||
|
||||
soc@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8248-immr", "fsl,pq2-soc", "simple-bus";
|
||||
ranges = <0x00000000 0xf0000000 0x00053000>;
|
||||
|
||||
// Temporary until code stops depending on it.
|
||||
device_type = "soc";
|
||||
|
||||
// Temporary -- will go away once kernel uses ranges for get_immrbase().
|
||||
reg = <0xf0000000 0x00053000>;
|
||||
|
||||
cpm@119c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,mpc8248-cpm", "fsl,cpm2",
|
||||
"simple-bus";
|
||||
reg = <0x119c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x1100 0x1140
|
||||
0xec0 0x9800 0x800>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@119f0 {
|
||||
compatible = "fsl,mpc8248-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x119f0 0x10 0x115f0 0x10>;
|
||||
};
|
||||
|
||||
/* Monitor port/SMC1 */
|
||||
smc1: serial@11a80 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8248-smc-uart",
|
||||
"fsl,cpm2-smc-uart";
|
||||
reg = <0x11a80 0x20 0x1100 0x40>;
|
||||
interrupts = <4 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-brg = <7>;
|
||||
fsl,cpm-command = <0x1d000000>;
|
||||
linux,planetcore-label = "SMC1";
|
||||
};
|
||||
|
||||
/* "Serial" port/SCC1 */
|
||||
scc1: serial@11a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8248-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <0x11a00 0x20 0x8000 0x100>;
|
||||
interrupts = <40 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x00800000>;
|
||||
linux,planetcore-label = "SCC1";
|
||||
};
|
||||
|
||||
eth0: ethernet@11300 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8248-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x11300 0x20 0x8400 0x100 0x11390 1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY0>;
|
||||
linux,network-index = <0>;
|
||||
fsl,cpm-command = <0x12000300>;
|
||||
};
|
||||
|
||||
eth1: ethernet@11320 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8248-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x11320 0x20 0x8500 0x100 0x113b0 1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <33 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY1>;
|
||||
linux,network-index = <1>;
|
||||
fsl,cpm-command = <0x16200300>;
|
||||
};
|
||||
|
||||
usb@11b60 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc8248-usb",
|
||||
"fsl,cpm2-usb";
|
||||
reg = <0x11b60 0x18 0x8b00 0x100>;
|
||||
interrupt-parent = <&PIC>;
|
||||
interrupts = <11 8>;
|
||||
fsl,cpm-command = <0x2e600000>;
|
||||
};
|
||||
};
|
||||
|
||||
PIC: interrupt-controller@10c00 {
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0x10c00 0x80>;
|
||||
compatible = "fsl,mpc8248-pic", "fsl,pq2-pic";
|
||||
};
|
||||
};
|
||||
};
|
||||
274
arch/powerpc/boot/dts/haleakala.dts
Normal file
274
arch/powerpc/boot/dts/haleakala.dts
Normal file
|
|
@ -0,0 +1,274 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Haleakala (405EXr)
|
||||
*
|
||||
* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,haleakala";
|
||||
compatible = "amcc,kilauea";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EXr";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <4000>; /* 16 kB */
|
||||
d-cache-size = <4000>; /* 16 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405exr", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-405exr","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-405exr","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1c 4 1d 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-405exr", "ibm,plb4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405exr";
|
||||
dcr-reg = <010 2>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405exr", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405exr", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <80000000 80000000 10000000
|
||||
ef600000 ef600000 a00000
|
||||
f0000000 f0000000 10000000>;
|
||||
dcr-reg = <0a0 5>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405exr", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <5 1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0 200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <200000 200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <400000 3b60000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600200 8>;
|
||||
virtual-reg = <ef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1a 4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
compatible = "ibm,iic-405exr", "ibm,iic";
|
||||
reg = <ef600400 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
compatible = "ibm,iic-405exr", "ibm,iic";
|
||||
reg = <ef600500 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
};
|
||||
|
||||
|
||||
RGMII0: emac-rgmii@ef600b00 {
|
||||
compatible = "ibm,rgmii-405exr", "ibm,rgmii";
|
||||
reg = <ef600b00 104>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
linux,network-index = <0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405exr", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 18 4
|
||||
/*Wake*/ 1 &UIC1 1d 4>;
|
||||
reg = <ef600900 70>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@0a0000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405exr", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <a0000000 20000000 /* Config space access */
|
||||
ef000000 00001000>; /* Registers */
|
||||
dcr-reg = <040 020>;
|
||||
sdr-base = <400>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 90000000 0 08000000
|
||||
01000000 0 00000000 e0000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 0x00 to 0x3f */
|
||||
bus-range = <00 3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 0 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 1 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 2 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
400
arch/powerpc/boot/dts/katmai.dts
Normal file
400
arch/powerpc/boot/dts/katmai.dts
Normal file
|
|
@ -0,0 +1,400 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Katmai eval board
|
||||
*
|
||||
* Copyright (c) 2006, 2007 IBM Corp.
|
||||
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
||||
*
|
||||
* Copyright (c) 2006, 2007 IBM Corp.
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,katmai";
|
||||
compatible = "amcc,katmai";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
serial2 = &UART2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440SPe";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <20000>;
|
||||
d-cache-size = <20000>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <a 4 b 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic-440spe","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0f0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <10 4 11 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440spe";
|
||||
dcr-reg = <00e 002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440spe";
|
||||
dcr-reg = <00c 002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
|
||||
dcr-reg = <010 2>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <1>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC1 6 4
|
||||
/*RXEOB*/ 1 &UIC1 7 4
|
||||
/*SERR*/ 2 &UIC1 1 4
|
||||
/*TXDE*/ 3 &UIC1 2 4
|
||||
/*RXDE*/ 4 &UIC1 3 4>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <00000000 4 e0000000 20000000>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <5 1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
};
|
||||
|
||||
UART0: serial@10000200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <10000200 8>;
|
||||
virtual-reg = <a0000200>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <1c200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
};
|
||||
|
||||
UART1: serial@10000300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <10000300 8>;
|
||||
virtual-reg = <a0000300>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
};
|
||||
|
||||
|
||||
UART2: serial@10000600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <10000600 8>;
|
||||
virtual-reg = <a0000600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <5 4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@10000400 {
|
||||
device_type = "i2c";
|
||||
compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <10000400 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@10000500 {
|
||||
device_type = "i2c";
|
||||
compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <10000500 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@10000800 {
|
||||
linux,network-index = <0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440spe", "ibm,emac4";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1c 4 1d 4>;
|
||||
reg = <10000800 70>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "gmii";
|
||||
phy-map = <00000000>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIX0: pci@c0ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
|
||||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <c 0ec00000 8 /* Config space access */
|
||||
0 0 0 /* no IACK cycles */
|
||||
c 0ed00000 4 /* Special cycles */
|
||||
c 0ec80000 100 /* Internal registers */
|
||||
c 0ec80100 fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
|
||||
01000000 0 00000000 0000000c 08000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 0 to 0xf */
|
||||
bus-range = <0 f>;
|
||||
|
||||
/*
|
||||
* On Katmai, the following PCI-X interrupts signals
|
||||
* have to be enabled via jumpers (only INTA is
|
||||
* enabled per default):
|
||||
*
|
||||
* INTB: J3: 1-2
|
||||
* INTC: J2: 1-2
|
||||
* INTD: J1: 1-2
|
||||
*/
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 1 &UIC1 14 8
|
||||
0800 0 0 2 &UIC1 13 8
|
||||
0800 0 0 3 &UIC1 12 8
|
||||
0800 0 0 4 &UIC1 11 8
|
||||
>;
|
||||
};
|
||||
|
||||
PCIE0: pciex@d00000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <d 00000000 20000000 /* Config space access */
|
||||
c 10000000 00001000>; /* Registers */
|
||||
dcr-reg = <100 020>;
|
||||
sdr-base = <300>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <10 1f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 0 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 1 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 2 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 3 4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@d20000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <1>; /* port number */
|
||||
reg = <d 20000000 20000000 /* Config space access */
|
||||
c 10001000 00001000>; /* Registers */
|
||||
dcr-reg = <120 020>;
|
||||
sdr-base = <340>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80010000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <20 2f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 4 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 5 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 6 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 7 4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE2: pciex@d40000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <2>; /* port number */
|
||||
reg = <d 40000000 20000000 /* Config space access */
|
||||
c 10002000 00001000>; /* Registers */
|
||||
dcr-reg = <140 020>;
|
||||
sdr-base = <370>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 0000000f 00000000 0 80000000
|
||||
01000000 0 00000000 0000000f 80020000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 10 to 0x1f */
|
||||
bus-range = <30 3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC3 8 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC3 9 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC3 a 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC3 b 4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@10000200";
|
||||
};
|
||||
};
|
||||
|
|
@ -13,14 +13,22 @@ / {
|
|||
#size-cells = <1>;
|
||||
model = "amcc,kilauea";
|
||||
compatible = "amcc,kilauea";
|
||||
dcr-parent = <&/cpus/PowerPC,405EX@0>;
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,405EX@0 {
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EX";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
|
@ -194,6 +202,7 @@ RGMII0: emac-rgmii@ef600b00 {
|
|||
device_type = "rgmii-interface";
|
||||
compatible = "ibm,rgmii-405ex", "ibm,rgmii";
|
||||
reg = <ef600b00 104>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
|
|
@ -220,6 +229,8 @@ EMAC0: ethernet@ef600900 {
|
|||
phy-map = <00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600a00 {
|
||||
|
|
@ -246,7 +257,91 @@ EMAC1: ethernet@ef600a00 {
|
|||
phy-map = <00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@0a0000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <a0000000 20000000 /* Config space access */
|
||||
ef000000 00001000>; /* Registers */
|
||||
dcr-reg = <040 020>;
|
||||
sdr-base = <400>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 90000000 0 08000000
|
||||
01000000 0 00000000 e0000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 0x00 to 0x3f */
|
||||
bus-range = <00 3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 0 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 1 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 2 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@0c0000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <1>; /* port number */
|
||||
reg = <c0000000 20000000 /* Config space access */
|
||||
ef001000 00001000>; /* Registers */
|
||||
dcr-reg = <060 020>;
|
||||
sdr-base = <440>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 98000000 0 08000000
|
||||
01000000 0 00000000 e0010000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 0x40 to 0x7f */
|
||||
bus-range = <40 7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 b 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 c 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 d 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,6 +23,12 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -60,7 +66,7 @@ fec00000 fec00000 00300000 /* pci cfg regs */
|
|||
i2c@80003000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <80003000 1000>;
|
||||
interrupts = <5 2>;
|
||||
|
|
@ -73,7 +79,8 @@ rtc@32 {
|
|||
};
|
||||
};
|
||||
|
||||
serial@80004500 {
|
||||
serial0: serial@80004500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <80004500 8>;
|
||||
|
|
@ -83,7 +90,8 @@ serial@80004500 {
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@80004600 {
|
||||
serial1: serial@80004600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <80004600 8>;
|
||||
|
|
@ -102,7 +110,7 @@ mpic: interrupt-controller@80040000 {
|
|||
reg = <80040000 40000>;
|
||||
};
|
||||
|
||||
pci@fec00000 {
|
||||
pci0: pci@fec00000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -23,6 +23,12 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -60,7 +66,7 @@ fec00000 fec00000 00300000 /* pci cfg regs */
|
|||
i2c@80003000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <80003000 1000>;
|
||||
interrupts = <5 2>;
|
||||
|
|
@ -73,7 +79,8 @@ rtc@32 {
|
|||
};
|
||||
};
|
||||
|
||||
serial@80004500 {
|
||||
serial0: serial@80004500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <80004500 8>;
|
||||
|
|
@ -83,7 +90,8 @@ serial@80004500 {
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@80004600 {
|
||||
serial1: serial@80004600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <80004600 8>;
|
||||
|
|
@ -102,7 +110,7 @@ mpic: interrupt-controller@80040000 {
|
|||
reg = <80040000 40000>;
|
||||
};
|
||||
|
||||
pci@fec00000 {
|
||||
pci0: pci@fec00000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -10,16 +10,9 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING: Do not depend on this tree layout remaining static just yet.
|
||||
* The MPC5200 device tree conventions are still in flux
|
||||
* Keep an eye on the linuxppc-dev mailing list for more details
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "fsl,lite5200";
|
||||
// revision = "1.0";
|
||||
compatible = "fsl,lite5200","generic-mpc5200";
|
||||
compatible = "fsl,lite5200";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -46,30 +39,29 @@ memory {
|
|||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
model = "fsl,mpc5200";
|
||||
compatible = "mpc5200";
|
||||
revision = ""; // from bootloader
|
||||
device_type = "soc";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
||||
reg = <f0000000 00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "mpc5200-cdm";
|
||||
compatible = "fsl,mpc5200-cdm";
|
||||
reg = <200 38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: pic@500 {
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "mpc5200-pic";
|
||||
compatible = "fsl,mpc5200-pic";
|
||||
reg = <500 80>;
|
||||
};
|
||||
|
||||
gpt@600 { // General Purpose Timer
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <0>;
|
||||
reg = <600 10>;
|
||||
|
|
@ -78,7 +70,7 @@ gpt@600 { // General Purpose Timer
|
|||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
gpt@610 { // General Purpose Timer
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <1>;
|
||||
reg = <610 10>;
|
||||
|
|
@ -86,7 +78,7 @@ gpt@610 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@620 { // General Purpose Timer
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <2>;
|
||||
reg = <620 10>;
|
||||
|
|
@ -94,7 +86,7 @@ gpt@620 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@630 { // General Purpose Timer
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <3>;
|
||||
reg = <630 10>;
|
||||
|
|
@ -102,7 +94,7 @@ gpt@630 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@640 { // General Purpose Timer
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <4>;
|
||||
reg = <640 10>;
|
||||
|
|
@ -110,7 +102,7 @@ gpt@640 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@650 { // General Purpose Timer
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <5>;
|
||||
reg = <650 10>;
|
||||
|
|
@ -118,7 +110,7 @@ gpt@650 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@660 { // General Purpose Timer
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <6>;
|
||||
reg = <660 10>;
|
||||
|
|
@ -126,7 +118,7 @@ gpt@660 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@670 { // General Purpose Timer
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <7>;
|
||||
reg = <670 10>;
|
||||
|
|
@ -135,25 +127,23 @@ gpt@670 { // General Purpose Timer
|
|||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "mpc5200-rtc";
|
||||
compatible = "fsl,mpc5200-rtc";
|
||||
device_type = "rtc";
|
||||
reg = <800 100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
mscan@900 {
|
||||
device_type = "mscan";
|
||||
compatible = "mpc5200-mscan";
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <2 11 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <900 80>;
|
||||
};
|
||||
|
||||
mscan@980 {
|
||||
device_type = "mscan";
|
||||
compatible = "mpc5200-mscan";
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <2 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
|
@ -161,38 +151,36 @@ mscan@980 {
|
|||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "mpc5200-gpio";
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio-wkup@c00 {
|
||||
compatible = "mpc5200-gpio-wkup";
|
||||
gpio@c00 {
|
||||
compatible = "fsl,mpc5200-gpio-wkup";
|
||||
reg = <c00 40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
device_type = "spi";
|
||||
compatible = "mpc5200-spi";
|
||||
compatible = "fsl,mpc5200-spi";
|
||||
reg = <f00 20>;
|
||||
interrupts = <2 d 0 2 e 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
device_type = "usb-ohci-be";
|
||||
compatible = "mpc5200-ohci","ohci-be";
|
||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
bestcomm@1200 {
|
||||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "mpc5200-bestcomm";
|
||||
compatible = "fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
|
|
@ -202,13 +190,13 @@ bestcomm@1200 {
|
|||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "mpc5200-xlb";
|
||||
compatible = "fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "mpc5200-psc-uart";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
cell-index = <0>;
|
||||
reg = <2000 100>;
|
||||
|
|
@ -218,8 +206,7 @@ serial@2000 { // PSC1
|
|||
|
||||
// PSC2 in ac97 mode example
|
||||
//ac97@2200 { // PSC2
|
||||
// device_type = "sound";
|
||||
// compatible = "mpc5200-psc-ac97";
|
||||
// compatible = "fsl,mpc5200-psc-ac97";
|
||||
// cell-index = <1>;
|
||||
// reg = <2200 100>;
|
||||
// interrupts = <2 2 0>;
|
||||
|
|
@ -228,8 +215,7 @@ serial@2000 { // PSC1
|
|||
|
||||
// PSC3 in CODEC mode example
|
||||
//i2s@2400 { // PSC3
|
||||
// device_type = "sound";
|
||||
// compatible = "mpc5200-psc-i2s";
|
||||
// compatible = "fsl,mpc5200-psc-i2s";
|
||||
// cell-index = <2>;
|
||||
// reg = <2400 100>;
|
||||
// interrupts = <2 3 0>;
|
||||
|
|
@ -239,7 +225,7 @@ serial@2000 { // PSC1
|
|||
// PSC4 in uart mode example
|
||||
//serial@2600 { // PSC4
|
||||
// device_type = "serial";
|
||||
// compatible = "mpc5200-psc-uart";
|
||||
// compatible = "fsl,mpc5200-psc-uart";
|
||||
// cell-index = <3>;
|
||||
// reg = <2600 100>;
|
||||
// interrupts = <2 b 0>;
|
||||
|
|
@ -249,7 +235,7 @@ serial@2000 { // PSC1
|
|||
// PSC5 in uart mode example
|
||||
//serial@2800 { // PSC5
|
||||
// device_type = "serial";
|
||||
// compatible = "mpc5200-psc-uart";
|
||||
// compatible = "fsl,mpc5200-psc-uart";
|
||||
// cell-index = <4>;
|
||||
// reg = <2800 100>;
|
||||
// interrupts = <2 c 0>;
|
||||
|
|
@ -258,8 +244,7 @@ serial@2000 { // PSC1
|
|||
|
||||
// PSC6 in spi mode example
|
||||
//spi@2c00 { // PSC6
|
||||
// device_type = "spi";
|
||||
// compatible = "mpc5200-psc-spi";
|
||||
// compatible = "fsl,mpc5200-psc-spi";
|
||||
// cell-index = <5>;
|
||||
// reg = <2c00 100>;
|
||||
// interrupts = <2 4 0>;
|
||||
|
|
@ -268,24 +253,25 @@ serial@2000 { // PSC1
|
|||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "mpc5200-fec";
|
||||
compatible = "fsl,mpc5200-fec";
|
||||
reg = <3000 800>;
|
||||
mac-address = [ 02 03 04 05 06 07 ]; // Bad!
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
device_type = "ata";
|
||||
compatible = "mpc5200-ata";
|
||||
compatible = "fsl,mpc5200-ata";
|
||||
reg = <3a00 100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
device_type = "i2c";
|
||||
compatible = "mpc5200-i2c","fsl-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <3d00 40>;
|
||||
interrupts = <2 f 0>;
|
||||
|
|
@ -294,8 +280,9 @@ i2c@3d00 {
|
|||
};
|
||||
|
||||
i2c@3d40 {
|
||||
device_type = "i2c";
|
||||
compatible = "mpc5200-i2c","fsl-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
|
|
@ -303,8 +290,7 @@ i2c@3d40 {
|
|||
fsl5200-clocking;
|
||||
};
|
||||
sram@8000 {
|
||||
device_type = "sram";
|
||||
compatible = "mpc5200-sram","sram";
|
||||
compatible = "fsl,mpc5200-sram","sram";
|
||||
reg = <8000 4000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -314,7 +300,7 @@ pci@f0000d00 {
|
|||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "mpc5200-pci";
|
||||
compatible = "fsl,mpc5200-pci";
|
||||
reg = <f0000d00 100>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
|
||||
|
|
|
|||
|
|
@ -18,8 +18,7 @@
|
|||
|
||||
/ {
|
||||
model = "fsl,lite5200b";
|
||||
// revision = "1.0";
|
||||
compatible = "fsl,lite5200b","generic-mpc5200";
|
||||
compatible = "fsl,lite5200b";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -46,30 +45,29 @@ memory {
|
|||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
model = "fsl,mpc5200b";
|
||||
compatible = "mpc5200";
|
||||
revision = ""; // from bootloader
|
||||
device_type = "soc";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
||||
reg = <f0000000 00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "mpc5200b-cdm","mpc5200-cdm";
|
||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||
reg = <200 38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: pic@500 {
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "mpc5200b-pic","mpc5200-pic";
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <500 80>;
|
||||
};
|
||||
|
||||
gpt@600 { // General Purpose Timer
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <0>;
|
||||
reg = <600 10>;
|
||||
|
|
@ -78,7 +76,7 @@ gpt@600 { // General Purpose Timer
|
|||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
gpt@610 { // General Purpose Timer
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <1>;
|
||||
reg = <610 10>;
|
||||
|
|
@ -86,7 +84,7 @@ gpt@610 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@620 { // General Purpose Timer
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <2>;
|
||||
reg = <620 10>;
|
||||
|
|
@ -94,7 +92,7 @@ gpt@620 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@630 { // General Purpose Timer
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <3>;
|
||||
reg = <630 10>;
|
||||
|
|
@ -102,7 +100,7 @@ gpt@630 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@640 { // General Purpose Timer
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <4>;
|
||||
reg = <640 10>;
|
||||
|
|
@ -110,7 +108,7 @@ gpt@640 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@650 { // General Purpose Timer
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <5>;
|
||||
reg = <650 10>;
|
||||
|
|
@ -118,7 +116,7 @@ gpt@650 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@660 { // General Purpose Timer
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <6>;
|
||||
reg = <660 10>;
|
||||
|
|
@ -126,7 +124,7 @@ gpt@660 { // General Purpose Timer
|
|||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpt@670 { // General Purpose Timer
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <7>;
|
||||
reg = <670 10>;
|
||||
|
|
@ -135,25 +133,23 @@ gpt@670 { // General Purpose Timer
|
|||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "mpc5200b-rtc","mpc5200-rtc";
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
device_type = "rtc";
|
||||
reg = <800 100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
mscan@900 {
|
||||
device_type = "mscan";
|
||||
compatible = "mpc5200b-mscan","mpc5200-mscan";
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <2 11 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <900 80>;
|
||||
};
|
||||
|
||||
mscan@980 {
|
||||
device_type = "mscan";
|
||||
compatible = "mpc5200b-mscan","mpc5200-mscan";
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <2 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
|
@ -161,38 +157,36 @@ mscan@980 {
|
|||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "mpc5200b-gpio","mpc5200-gpio";
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio-wkup@c00 {
|
||||
compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup";
|
||||
gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <c00 40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
device_type = "spi";
|
||||
compatible = "mpc5200b-spi","mpc5200-spi";
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <f00 20>;
|
||||
interrupts = <2 d 0 2 e 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
device_type = "usb-ohci-be";
|
||||
compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
bestcomm@1200 {
|
||||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "mpc5200b-bestcomm","mpc5200-bestcomm";
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
|
|
@ -202,13 +196,13 @@ bestcomm@1200 {
|
|||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "mpc5200b-xlb","mpc5200-xlb";
|
||||
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
cell-index = <0>;
|
||||
reg = <2000 100>;
|
||||
|
|
@ -218,8 +212,7 @@ serial@2000 { // PSC1
|
|||
|
||||
// PSC2 in ac97 mode example
|
||||
//ac97@2200 { // PSC2
|
||||
// device_type = "sound";
|
||||
// compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97";
|
||||
// compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
|
||||
// cell-index = <1>;
|
||||
// reg = <2200 100>;
|
||||
// interrupts = <2 2 0>;
|
||||
|
|
@ -228,8 +221,7 @@ serial@2000 { // PSC1
|
|||
|
||||
// PSC3 in CODEC mode example
|
||||
//i2s@2400 { // PSC3
|
||||
// device_type = "sound";
|
||||
// compatible = "mpc5200b-psc-i2s"; //not 5200 compatible
|
||||
// compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
|
||||
// cell-index = <2>;
|
||||
// reg = <2400 100>;
|
||||
// interrupts = <2 3 0>;
|
||||
|
|
@ -239,7 +231,7 @@ serial@2000 { // PSC1
|
|||
// PSC4 in uart mode example
|
||||
//serial@2600 { // PSC4
|
||||
// device_type = "serial";
|
||||
// compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
|
||||
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
// cell-index = <3>;
|
||||
// reg = <2600 100>;
|
||||
// interrupts = <2 b 0>;
|
||||
|
|
@ -249,7 +241,7 @@ serial@2000 { // PSC1
|
|||
// PSC5 in uart mode example
|
||||
//serial@2800 { // PSC5
|
||||
// device_type = "serial";
|
||||
// compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
|
||||
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
// cell-index = <4>;
|
||||
// reg = <2800 100>;
|
||||
// interrupts = <2 c 0>;
|
||||
|
|
@ -258,8 +250,7 @@ serial@2000 { // PSC1
|
|||
|
||||
// PSC6 in spi mode example
|
||||
//spi@2c00 { // PSC6
|
||||
// device_type = "spi";
|
||||
// compatible = "mpc5200b-psc-spi","mpc5200-psc-spi";
|
||||
// compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
|
||||
// cell-index = <5>;
|
||||
// reg = <2c00 100>;
|
||||
// interrupts = <2 4 0>;
|
||||
|
|
@ -268,9 +259,9 @@ serial@2000 { // PSC1
|
|||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "mpc5200b-fec","mpc5200-fec";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <3000 400>;
|
||||
mac-address = [ 02 03 04 05 06 07 ]; // Bad!
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
phy-handle = <&phy0>;
|
||||
|
|
@ -279,8 +270,7 @@ ethernet@3000 {
|
|||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "mpc5200b-fec-phy";
|
||||
compatible = "fsl,mpc5200b-mdio";
|
||||
reg = <3000 400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
|
@ -293,15 +283,16 @@ phy0:ethernet-phy@0 {
|
|||
|
||||
ata@3a00 {
|
||||
device_type = "ata";
|
||||
compatible = "mpc5200b-ata","mpc5200-ata";
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <3a00 100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
device_type = "i2c";
|
||||
compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <3d00 40>;
|
||||
interrupts = <2 f 0>;
|
||||
|
|
@ -310,8 +301,9 @@ i2c@3d00 {
|
|||
};
|
||||
|
||||
i2c@3d40 {
|
||||
device_type = "i2c";
|
||||
compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
|
|
@ -319,8 +311,7 @@ i2c@3d40 {
|
|||
fsl5200-clocking;
|
||||
};
|
||||
sram@8000 {
|
||||
device_type = "sram";
|
||||
compatible = "mpc5200b-sram","mpc5200-sram","sram";
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
|
||||
reg = <8000 4000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -330,7 +321,7 @@ pci@f0000d00 {
|
|||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "mpc5200b-pci","mpc5200-pci";
|
||||
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||
reg = <f0000d00 100>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
|
||||
|
|
|
|||
347
arch/powerpc/boot/dts/makalu.dts
Normal file
347
arch/powerpc/boot/dts/makalu.dts
Normal file
|
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Makalu (405EX)
|
||||
*
|
||||
* Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,makalu";
|
||||
compatible = "amcc,makalu";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405EX";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <4000>; /* 16 kB */
|
||||
d-cache-size = <4000>; /* 16 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller {
|
||||
compatible = "ibm,uic-405ex", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-405ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-405ex","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1c 4 1d 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-405ex", "ibm,plb4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-405ex";
|
||||
dcr-reg = <010 2>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-405ex", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <80000000 80000000 10000000
|
||||
ef600000 ef600000 a00000
|
||||
f0000000 f0000000 10000000>;
|
||||
dcr-reg = <0a0 5>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-405ex", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
|
||||
interrupts = <5 1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0 200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <200000 200000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "user";
|
||||
reg = <400000 3b60000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
UART0: serial@ef600200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600200 8>;
|
||||
virtual-reg = <ef600200>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1a 4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600400 {
|
||||
device_type = "i2c";
|
||||
compatible = "ibm,iic-405ex", "ibm,iic";
|
||||
reg = <ef600400 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600500 {
|
||||
device_type = "i2c";
|
||||
compatible = "ibm,iic-405ex", "ibm,iic";
|
||||
reg = <ef600500 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
};
|
||||
|
||||
|
||||
RGMII0: emac-rgmii@ef600b00 {
|
||||
device_type = "rgmii-interface";
|
||||
compatible = "ibm,rgmii-405ex", "ibm,rgmii";
|
||||
reg = <ef600b00 104>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600900 {
|
||||
linux,network-index = <0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 18 4
|
||||
/*Wake*/ 1 &UIC1 1d 4>;
|
||||
reg = <ef600900 70>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0000003f>; /* Start at 6 */
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600a00 {
|
||||
linux,network-index = <1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-405ex", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 19 4
|
||||
/*Wake*/ 1 &UIC1 1f 4>;
|
||||
reg = <ef600a00 70>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCIE0: pciex@0a0000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <0>; /* port number */
|
||||
reg = <a0000000 20000000 /* Config space access */
|
||||
ef000000 00001000>; /* Registers */
|
||||
dcr-reg = <040 020>;
|
||||
sdr-base = <400>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 90000000 0 08000000
|
||||
01000000 0 00000000 e0000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 0x00 to 0x3f */
|
||||
bus-range = <00 3f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 0 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 1 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 2 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
|
||||
};
|
||||
|
||||
PCIE1: pciex@0c0000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||||
primary;
|
||||
port = <1>; /* port number */
|
||||
reg = <c0000000 20000000 /* Config space access */
|
||||
ef001000 00001000>; /* Registers */
|
||||
dcr-reg = <060 020>;
|
||||
sdr-base = <440>;
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 98000000 0 08000000
|
||||
01000000 0 00000000 e0010000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
|
||||
/* This drives busses 0x40 to 0x7f */
|
||||
bus-range = <40 7f>;
|
||||
|
||||
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||||
* to invert PCIe legacy interrupts).
|
||||
* We are de-swizzling here because the numbers are actually for
|
||||
* port of the root complex virtual P2P bridge. But I want
|
||||
* to avoid putting a node for it in the tree, so the numbers
|
||||
* below are basically de-swizzled numbers.
|
||||
* The real slot is on idsel 0, so the swizzling is 1:1
|
||||
*/
|
||||
interrupt-map-mask = <0000 0 0 7>;
|
||||
interrupt-map = <
|
||||
0000 0 0 1 &UIC2 b 4 /* swizzled int A */
|
||||
0000 0 0 2 &UIC2 c 4 /* swizzled int B */
|
||||
0000 0 0 3 &UIC2 d 4 /* swizzled int C */
|
||||
0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
|
||||
};
|
||||
};
|
||||
};
|
||||
301
arch/powerpc/boot/dts/motionpro.dts
Normal file
301
arch/powerpc/boot/dts/motionpro.dts
Normal file
|
|
@ -0,0 +1,301 @@
|
|||
/*
|
||||
* Motion-PRO board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "promess,motionpro";
|
||||
compatible = "promess,motionpro";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 04000000>; // 64MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
||||
reg = <f0000000 00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||
reg = <200 38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <500 80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <600 10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <610 10>;
|
||||
interrupts = <1 a 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <620 10>;
|
||||
interrupts = <1 b 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <630 10>;
|
||||
interrupts = <1 c 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <640 10>;
|
||||
interrupts = <1 d 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <650 10>;
|
||||
interrupts = <1 e 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
motionpro-led@660 { // Motion-PRO status LED
|
||||
compatible = "promess,motionpro-led";
|
||||
label = "motionpro-statusled";
|
||||
reg = <660 10>;
|
||||
interrupts = <1 f 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
blink-delay = <64>; // 100 msec
|
||||
};
|
||||
|
||||
motionpro-led@670 { // Motion-PRO ready LED
|
||||
compatible = "promess,motionpro-led";
|
||||
label = "motionpro-readyled";
|
||||
reg = <670 10>;
|
||||
interrupts = <1 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
reg = <800 100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
mscan@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
interrupts = <2 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <980 80>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <c00 40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <f00 20>;
|
||||
interrupts = <2 d 0 2 e 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 a 0 3 b 0
|
||||
3 c 0 3 d 0 3 e 0 3 f 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
reg = <2000 100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
// PSC2 in spi master mode
|
||||
spi@2200 { // PSC2
|
||||
compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
|
||||
cell-index = <1>;
|
||||
reg = <2200 100>;
|
||||
interrupts = <2 2 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
// PSC5 in uart mode
|
||||
serial@2800 { // PSC5
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <4>; // Logical port assignment
|
||||
reg = <2800 100>;
|
||||
interrupts = <2 c 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <3000 800>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <3a00 100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <8000 4000>;
|
||||
};
|
||||
};
|
||||
|
||||
lpb {
|
||||
compatible = "fsl,lpb";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0 50000000 00010000
|
||||
2 0 50010000 00010000
|
||||
3 0 50020000 00010000>;
|
||||
|
||||
// 8-bit DualPort SRAM on LocalPlus Bus CS1
|
||||
kollmorgen@1,0 {
|
||||
compatible = "promess,motionpro-kollmorgen";
|
||||
reg = <1 0 10000>;
|
||||
interrupts = <1 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
// 8-bit board CPLD on LocalPlus Bus CS2
|
||||
cpld@2,0 {
|
||||
compatible = "promess,motionpro-cpld";
|
||||
reg = <2 0 10000>;
|
||||
};
|
||||
|
||||
// 8-bit custom Anybus Module on LocalPlus Bus CS3
|
||||
anybus@3,0 {
|
||||
compatible = "promess,motionpro-anybus";
|
||||
reg = <3 0 10000>;
|
||||
};
|
||||
pro_module_general@3,0 {
|
||||
compatible = "promess,pro_module_general";
|
||||
reg = <3 0 3>;
|
||||
};
|
||||
pro_module_dio@3,800 {
|
||||
compatible = "promess,pro_module_dio";
|
||||
reg = <3 800 2>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||
reg = <f0000d00 100>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
|
||||
c000 0 0 2 &mpc5200_pic 1 1 3
|
||||
c000 0 0 3 &mpc5200_pic 1 2 3
|
||||
c000 0 0 4 &mpc5200_pic 1 3 3
|
||||
|
||||
c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
|
||||
c800 0 0 2 &mpc5200_pic 1 2 3
|
||||
c800 0 0 3 &mpc5200_pic 1 3 3
|
||||
c800 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 a 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 20000000
|
||||
02000000 0 a0000000 a0000000 0 10000000
|
||||
01000000 0 00000000 b0000000 0 01000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -9,23 +9,33 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8313ERDB";
|
||||
compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8313@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <16384>;
|
||||
i-cache-size = <16384>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
|
|
@ -34,134 +44,188 @@ PowerPC,8313@0 {
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 08000000>; // 128MB at 0
|
||||
reg = <0x00000000 0x08000000>; // 128MB at 0
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
// CS0 and CS1 are swapped when
|
||||
// booting from nand, but the
|
||||
// addresses are the same.
|
||||
ranges = <0x0 0x0 0xfe000000 0x00800000
|
||||
0x1 0x0 0xe2800000 0x00008000
|
||||
0x2 0x0 0xf0000000 0x00020000
|
||||
0x3 0x0 0xfa000000 0x00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8313-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <0x1 0x0 0x2000>;
|
||||
|
||||
u-boot@0 {
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@100000 {
|
||||
reg = <0x100000 0x300000>;
|
||||
};
|
||||
|
||||
fs@400000 {
|
||||
reg = <0x400000 0x1c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc8313@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00000200>;
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <200 100>;
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <e 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <f 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <7000 1000>;
|
||||
interrupts = <10 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <23000 1000>;
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <26 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
phy_type = "utmi_wide";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
reg = <24520 20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <13 8>;
|
||||
reg = <1>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <19 0x8>;
|
||||
reg = <0x1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <14 8>;
|
||||
reg = <4>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <20 0x8>;
|
||||
reg = <0x4>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <25 8 24 8 23 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <37 0x8 36 0x8 35 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = < &phy1 >;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <25000 1000>;
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <22 8 21 8 20 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <34 0x8 33 0x8 32 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = < &phy4 >;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <a 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 7000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x30000 0x7000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 2.2 */
|
||||
num-channels = <1>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000004c>;
|
||||
descriptor-types-mask = <0122003f>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000004c>;
|
||||
descriptor-types-mask = <0x0122003f>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
|
|
@ -174,37 +238,38 @@ ipic: pic@700 {
|
|||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x0E -mini PCI */
|
||||
7000 0 0 1 &ipic 12 8
|
||||
7000 0 0 2 &ipic 12 8
|
||||
7000 0 0 3 &ipic 12 8
|
||||
7000 0 0 4 &ipic 12 8
|
||||
0x7000 0x0 0x0 0x1 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x2 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x3 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x4 &ipic 18 0x8
|
||||
|
||||
/* IDSEL 0x0F - PCI slot */
|
||||
7800 0 0 1 &ipic 11 8
|
||||
7800 0 0 2 &ipic 12 8
|
||||
7800 0 0 3 &ipic 11 8
|
||||
7800 0 0 4 &ipic 12 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 90000000 90000000 0 10000000
|
||||
42000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 00100000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
0x7800 0x0 0x0 0x1 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x2 &ipic 18 0x8
|
||||
0x7800 0x0 0x0 0x3 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
|
|
|||
287
arch/powerpc/boot/dts/mpc8315erdb.dts
Normal file
287
arch/powerpc/boot/dts/mpc8315erdb.dts
Normal file
|
|
@ -0,0 +1,287 @@
|
|||
/*
|
||||
* MPC8315E RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,mpc8315erdb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8315@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <16384>;
|
||||
i-cache-size = <16384>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>; // 128MB at 0
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
// CS0 and CS1 are swapped when
|
||||
// booting from nand, but the
|
||||
// addresses are the same.
|
||||
ranges = <0x0 0x0 0xfe000000 0x00800000
|
||||
0x1 0x0 0xe0600000 0x00002000
|
||||
0x2 0x0 0xf0000000 0x00020000
|
||||
0x3 0x0 0xfa000000 0x00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8315-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <0x1 0x0 0x2000>;
|
||||
|
||||
u-boot@0 {
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@100000 {
|
||||
reg = <0x100000 0x300000>;
|
||||
};
|
||||
fs@400000 {
|
||||
reg = <0x400000 0x1c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
immr@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
device_type = "rtc";
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <20 0x8>;
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <19 0x8>;
|
||||
reg = <0x1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = < &phy0 >;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = < &phy1 >;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
device_type = "crypto";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
cell-index = <1>;
|
||||
interrupts = <44 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
cell-index = <2>;
|
||||
interrupts = <45 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: interrupt-controller@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0E -mini PCI */
|
||||
0x7000 0x0 0x0 0x1 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x2 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x3 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x4 &ipic 18 0x8
|
||||
|
||||
/* IDSEL 0x0F -mini PCI */
|
||||
0x7800 0x0 0x0 0x1 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x2 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x3 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x4 &ipic 17 0x8
|
||||
|
||||
/* IDSEL 0x10 - PCI slot */
|
||||
0x8000 0x0 0x0 0x1 &ipic 48 0x8
|
||||
0x8000 0x0 0x0 0x2 &ipic 17 0x8
|
||||
0x8000 0x0 0x0 0x3 &ipic 48 0x8
|
||||
0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
|
|
@ -7,25 +7,47 @@
|
|||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
|
||||
* To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
|
||||
* this:
|
||||
*
|
||||
* 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
|
||||
* 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
|
||||
* next to the serial ports.
|
||||
* 3) Solder a wire from U61-22 to P19K-22.
|
||||
*
|
||||
* Note that there's a typo in the schematic. The board labels the last column
|
||||
* of pins "P19K", but in the schematic, that column is called "P19J". So if
|
||||
* you're going by the schematic, the pin is called "P19J-K22".
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8323EMDS";
|
||||
compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8323@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <16384>; // L1, 16K
|
||||
i-cache-size = <16384>; // L1, 16K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
|
|
@ -34,86 +56,88 @@ PowerPC,8323@0 {
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 08000000>;
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
bcsr@f8000000 {
|
||||
device_type = "board-control";
|
||||
reg = <f8000000 8000>;
|
||||
reg = <0xf8000000 0x8000>;
|
||||
};
|
||||
|
||||
soc8323@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00000200>;
|
||||
bus-frequency = <7DE2900>;
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <132000000>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <200 100>;
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <e 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <68>;
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <a 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 7000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x30000 0x7000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 2.2 */
|
||||
num-channels = <1>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000004c>;
|
||||
descriptor-types-mask = <0122003f>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000004c>;
|
||||
descriptor-types-mask = <0x0122003f>;
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
par_io@1400 {
|
||||
reg = <1400 100>;
|
||||
reg = <0x1400 0x100>;
|
||||
device_type = "par_io";
|
||||
num-ports = <7>;
|
||||
|
||||
|
|
@ -122,8 +146,8 @@ pio3: ucc_pin@03 {
|
|||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
0 d 2 0 1 0 /* RX_CLK (CLK9) */
|
||||
3 18 2 0 1 0 /* TX_CLK (CLK10) */
|
||||
0 13 2 0 1 0 /* RX_CLK (CLK9) */
|
||||
3 24 2 0 1 0 /* TX_CLK (CLK10) */
|
||||
1 0 1 0 1 0 /* TxD0 */
|
||||
1 1 1 0 1 0 /* TxD1 */
|
||||
1 2 1 0 1 0 /* TxD2 */
|
||||
|
|
@ -134,31 +158,48 @@ pio3: ucc_pin@03 {
|
|||
1 7 2 0 1 0 /* RxD3 */
|
||||
1 8 2 0 1 0 /* RX_ER */
|
||||
1 9 1 0 1 0 /* TX_ER */
|
||||
1 a 2 0 1 0 /* RX_DV */
|
||||
1 b 2 0 1 0 /* COL */
|
||||
1 c 1 0 1 0 /* TX_EN */
|
||||
1 d 2 0 1 0>;/* CRS */
|
||||
1 10 2 0 1 0 /* RX_DV */
|
||||
1 11 2 0 1 0 /* COL */
|
||||
1 12 1 0 1 0 /* TX_EN */
|
||||
1 13 2 0 1 0>; /* CRS */
|
||||
};
|
||||
pio4: ucc_pin@04 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
3 1f 2 0 1 0 /* RX_CLK (CLK7) */
|
||||
3 31 2 0 1 0 /* RX_CLK (CLK7) */
|
||||
3 6 2 0 1 0 /* TX_CLK (CLK8) */
|
||||
1 12 1 0 1 0 /* TxD0 */
|
||||
1 13 1 0 1 0 /* TxD1 */
|
||||
1 14 1 0 1 0 /* TxD2 */
|
||||
1 15 1 0 1 0 /* TxD3 */
|
||||
1 16 2 0 1 0 /* RxD0 */
|
||||
1 17 2 0 1 0 /* RxD1 */
|
||||
1 18 2 0 1 0 /* RxD2 */
|
||||
1 19 2 0 1 0 /* RxD3 */
|
||||
1 1a 2 0 1 0 /* RX_ER */
|
||||
1 1b 1 0 1 0 /* TX_ER */
|
||||
1 1c 2 0 1 0 /* RX_DV */
|
||||
1 1d 2 0 1 0 /* COL */
|
||||
1 1e 1 0 1 0 /* TX_EN */
|
||||
1 1f 2 0 1 0>;/* CRS */
|
||||
1 18 1 0 1 0 /* TxD0 */
|
||||
1 19 1 0 1 0 /* TxD1 */
|
||||
1 20 1 0 1 0 /* TxD2 */
|
||||
1 21 1 0 1 0 /* TxD3 */
|
||||
1 22 2 0 1 0 /* RxD0 */
|
||||
1 23 2 0 1 0 /* RxD1 */
|
||||
1 24 2 0 1 0 /* RxD2 */
|
||||
1 25 2 0 1 0 /* RxD3 */
|
||||
1 26 2 0 1 0 /* RX_ER */
|
||||
1 27 1 0 1 0 /* TX_ER */
|
||||
1 28 2 0 1 0 /* RX_DV */
|
||||
1 29 2 0 1 0 /* COL */
|
||||
1 30 1 0 1 0 /* TX_EN */
|
||||
1 31 2 0 1 0>; /* CRS */
|
||||
};
|
||||
pio5: ucc_pin@05 {
|
||||
pio-map = <
|
||||
/*
|
||||
* open has
|
||||
* port pin dir drain sel irq
|
||||
*/
|
||||
2 0 1 0 2 0 /* TxD5 */
|
||||
2 8 2 0 2 0 /* RxD5 */
|
||||
|
||||
2 29 2 0 0 0 /* CTS5 */
|
||||
2 31 1 0 2 0 /* RTS5 */
|
||||
|
||||
2 24 2 0 0 0 /* CD */
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -166,178 +207,191 @@ qe@e0100000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
model = "QE";
|
||||
ranges = <0 e0100000 00100000>;
|
||||
reg = <e0100000 480>;
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0xe0100000 0x00100000>;
|
||||
reg = <0xe0100000 0x480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <BCD3D80>;
|
||||
bus-frequency = <198000000>;
|
||||
|
||||
muram@10000 {
|
||||
device_type = "muram";
|
||||
ranges = <0 00010000 00004000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x00010000 0x00004000>;
|
||||
|
||||
data-only@0 {
|
||||
reg = <0 4000>;
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <4c0 40>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = < &qeic >;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <500 40>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = < &qeic >;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
usb@6c0 {
|
||||
device_type = "usb";
|
||||
compatible = "qe_udc";
|
||||
reg = <6c0 40 8B00 100>;
|
||||
interrupts = <b>;
|
||||
interrupt-parent = < &qeic >;
|
||||
reg = <0x6c0 0x40 0x8b00 0x100>;
|
||||
interrupts = <11>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "slave";
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
enet0: ucc@2200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
cell-index = <3>;
|
||||
device-id = <3>;
|
||||
reg = <2200 200>;
|
||||
interrupts = <22>;
|
||||
interrupt-parent = < &qeic >;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock = <19>;
|
||||
tx-clock = <1a>;
|
||||
phy-handle = < &phy3 >;
|
||||
pio-handle = < &pio3 >;
|
||||
rx-clock-name = "clk9";
|
||||
tx-clock-name = "clk10";
|
||||
phy-handle = <&phy3>;
|
||||
pio-handle = <&pio3>;
|
||||
};
|
||||
|
||||
ucc@3200 {
|
||||
enet1: ucc@3200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
cell-index = <4>;
|
||||
device-id = <4>;
|
||||
reg = <3200 200>;
|
||||
interrupts = <23>;
|
||||
reg = <0x3200 0x200>;
|
||||
interrupts = <35>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock-name = "clk7";
|
||||
tx-clock-name = "clk8";
|
||||
phy-handle = <&phy4>;
|
||||
pio-handle = <&pio4>;
|
||||
};
|
||||
|
||||
ucc@2400 {
|
||||
device_type = "serial";
|
||||
compatible = "ucc_uart";
|
||||
model = "UCC";
|
||||
device-id = <5>; /* The UCC number, 1-7*/
|
||||
port-number = <0>; /* Which ttyQEx device */
|
||||
soft-uart; /* We need Soft-UART */
|
||||
reg = <0x2400 0x200>;
|
||||
interrupts = <40>; /* From Table 18-12 */
|
||||
interrupt-parent = < &qeic >;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
* For Soft-UART, we need to set TX to 1X, which
|
||||
* means specifying separate clock sources.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock = <17>;
|
||||
tx-clock = <18>;
|
||||
phy-handle = < &phy4 >;
|
||||
pio-handle = < &pio4 >;
|
||||
rx-clock-name = "brg5";
|
||||
tx-clock-name = "brg6";
|
||||
pio-handle = < &pio5 >;
|
||||
};
|
||||
|
||||
|
||||
mdio@2320 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2320 18>;
|
||||
device_type = "mdio";
|
||||
compatible = "ucc_geth_phy";
|
||||
reg = <0x2320 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
phy3: ethernet-phy@03 {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <11 8>;
|
||||
reg = <3>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy4: ethernet-phy@04 {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <12 8>;
|
||||
reg = <4>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x4>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
qeic: qeic@80 {
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
device_type = "qeic";
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <80 80>;
|
||||
reg = <0x80 0x80>;
|
||||
big-endian;
|
||||
interrupts = <20 8 21 8>; //high:32 low:33
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <32 0x8 33 0x8>; //high:32 low:33
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x11 AD17 */
|
||||
8800 0 0 1 &ipic 14 8
|
||||
8800 0 0 2 &ipic 15 8
|
||||
8800 0 0 3 &ipic 16 8
|
||||
8800 0 0 4 &ipic 17 8
|
||||
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x12 AD18 */
|
||||
9000 0 0 1 &ipic 16 8
|
||||
9000 0 0 2 &ipic 17 8
|
||||
9000 0 0 3 &ipic 14 8
|
||||
9000 0 0 4 &ipic 15 8
|
||||
0x9000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0x9000 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0x9000 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0x9000 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x13 AD19 */
|
||||
9800 0 0 1 &ipic 17 8
|
||||
9800 0 0 2 &ipic 14 8
|
||||
9800 0 0 3 &ipic 15 8
|
||||
9800 0 0 4 &ipic 16 8
|
||||
0x9800 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0x9800 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0x9800 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0x9800 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x15 AD21*/
|
||||
a800 0 0 1 &ipic 14 8
|
||||
a800 0 0 2 &ipic 15 8
|
||||
a800 0 0 3 &ipic 16 8
|
||||
a800 0 0 4 &ipic 17 8
|
||||
0xa800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0xa800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xa800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0xa800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x16 AD22*/
|
||||
b000 0 0 1 &ipic 17 8
|
||||
b000 0 0 2 &ipic 14 8
|
||||
b000 0 0 3 &ipic 15 8
|
||||
b000 0 0 4 &ipic 16 8
|
||||
0xb000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xb000 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0xb000 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0xb000 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x17 AD23*/
|
||||
b800 0 0 1 &ipic 16 8
|
||||
b800 0 0 2 &ipic 17 8
|
||||
b800 0 0 3 &ipic 14 8
|
||||
b800 0 0 4 &ipic 15 8
|
||||
0xb800 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0xb800 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0xb800 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0xb800 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x18 AD24*/
|
||||
c000 0 0 1 &ipic 15 8
|
||||
c000 0 0 2 &ipic 16 8
|
||||
c000 0 0 3 &ipic 17 8
|
||||
c000 0 0 4 &ipic 14 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 90000000 90000000 0 10000000
|
||||
42000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 d0000000 0 00100000>;
|
||||
0xc000 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0xc000 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0xc000 0x0 0x0 0x3 &ipic 23 0x8
|
||||
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
|
||||
clock-frequency = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,23 +9,33 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8323ERDB";
|
||||
compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8323@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <0x20>; // 32 bytes
|
||||
i-cache-line-size = <0x20>; // 32 bytes
|
||||
d-cache-size = <16384>; // L1, 16K
|
||||
i-cache-size = <16384>; // L1, 16K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
|
|
@ -34,47 +44,51 @@ PowerPC,8323@0 {
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 04000000>;
|
||||
reg = <0x00000000 0x04000000>;
|
||||
};
|
||||
|
||||
soc8323@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00000200>;
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <200 100>;
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <e 8>;
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&pic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 8>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <a 8>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
|
|
@ -82,26 +96,26 @@ crypto@30000 {
|
|||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 7000>;
|
||||
interrupts = <b 8>;
|
||||
reg = <0x30000 0x7000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&pic>;
|
||||
/* Rev. 2.2 */
|
||||
num-channels = <1>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000004c>;
|
||||
descriptor-types-mask = <0122003f>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000004c>;
|
||||
descriptor-types-mask = <0x0122003f>;
|
||||
};
|
||||
|
||||
pic:pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
par_io@1400 {
|
||||
reg = <1400 100>;
|
||||
reg = <0x1400 0x100>;
|
||||
device_type = "par_io";
|
||||
num-ports = <7>;
|
||||
|
||||
|
|
@ -110,28 +124,28 @@ ucc2pio:ucc_pin@02 {
|
|||
/* port pin dir open_drain assignment has_irq */
|
||||
3 4 3 0 2 0 /* MDIO */
|
||||
3 5 1 0 2 0 /* MDC */
|
||||
3 15 2 0 1 0 /* RX_CLK (CLK16) */
|
||||
3 17 2 0 1 0 /* TX_CLK (CLK3) */
|
||||
0 12 1 0 1 0 /* TxD0 */
|
||||
0 13 1 0 1 0 /* TxD1 */
|
||||
0 14 1 0 1 0 /* TxD2 */
|
||||
0 15 1 0 1 0 /* TxD3 */
|
||||
0 16 2 0 1 0 /* RxD0 */
|
||||
0 17 2 0 1 0 /* RxD1 */
|
||||
0 18 2 0 1 0 /* RxD2 */
|
||||
0 19 2 0 1 0 /* RxD3 */
|
||||
0 1a 2 0 1 0 /* RX_ER */
|
||||
0 1b 1 0 1 0 /* TX_ER */
|
||||
0 1c 2 0 1 0 /* RX_DV */
|
||||
0 1d 2 0 1 0 /* COL */
|
||||
0 1e 1 0 1 0 /* TX_EN */
|
||||
0 1f 2 0 1 0>; /* CRS */
|
||||
3 21 2 0 1 0 /* RX_CLK (CLK16) */
|
||||
3 23 2 0 1 0 /* TX_CLK (CLK3) */
|
||||
0 18 1 0 1 0 /* TxD0 */
|
||||
0 19 1 0 1 0 /* TxD1 */
|
||||
0 20 1 0 1 0 /* TxD2 */
|
||||
0 21 1 0 1 0 /* TxD3 */
|
||||
0 22 2 0 1 0 /* RxD0 */
|
||||
0 23 2 0 1 0 /* RxD1 */
|
||||
0 24 2 0 1 0 /* RxD2 */
|
||||
0 25 2 0 1 0 /* RxD3 */
|
||||
0 26 2 0 1 0 /* RX_ER */
|
||||
0 27 1 0 1 0 /* TX_ER */
|
||||
0 28 2 0 1 0 /* RX_DV */
|
||||
0 29 2 0 1 0 /* COL */
|
||||
0 30 1 0 1 0 /* TX_EN */
|
||||
0 31 2 0 1 0>; /* CRS */
|
||||
};
|
||||
ucc3pio:ucc_pin@03 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 d 2 0 1 0 /* RX_CLK (CLK9) */
|
||||
3 18 2 0 1 0 /* TX_CLK (CLK10) */
|
||||
0 13 2 0 1 0 /* RX_CLK (CLK9) */
|
||||
3 24 2 0 1 0 /* TX_CLK (CLK10) */
|
||||
1 0 1 0 1 0 /* TxD0 */
|
||||
1 1 1 0 1 0 /* TxD1 */
|
||||
1 2 1 0 1 0 /* TxD2 */
|
||||
|
|
@ -142,10 +156,10 @@ ucc3pio:ucc_pin@03 {
|
|||
1 7 2 0 1 0 /* RxD3 */
|
||||
1 8 2 0 1 0 /* RX_ER */
|
||||
1 9 1 0 1 0 /* TX_ER */
|
||||
1 a 2 0 1 0 /* RX_DV */
|
||||
1 b 2 0 1 0 /* COL */
|
||||
1 c 1 0 1 0 /* TX_EN */
|
||||
1 d 2 0 1 0>; /* CRS */
|
||||
1 10 2 0 1 0 /* RX_DV */
|
||||
1 11 2 0 1 0 /* COL */
|
||||
1 12 1 0 1 0 /* TX_EN */
|
||||
1 13 2 0 1 0>; /* CRS */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -154,77 +168,71 @@ qe@e0100000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
model = "QE";
|
||||
ranges = <0 e0100000 00100000>;
|
||||
reg = <e0100000 480>;
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0xe0100000 0x00100000>;
|
||||
reg = <0xe0100000 0x480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <BCD3D80>;
|
||||
bus-frequency = <198000000>;
|
||||
|
||||
muram@10000 {
|
||||
device_type = "muram";
|
||||
ranges = <0 00010000 00004000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x00010000 0x00004000>;
|
||||
|
||||
data-only@0 {
|
||||
reg = <0 4000>;
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <4c0 40>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu-qe";
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <500 40>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
ucc@3000 {
|
||||
enet0: ucc@3000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
cell-index = <2>;
|
||||
device-id = <2>;
|
||||
reg = <3000 200>;
|
||||
interrupts = <21>;
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock = <20>;
|
||||
tx-clock = <13>;
|
||||
rx-clock-name = "clk16";
|
||||
tx-clock-name = "clk3";
|
||||
phy-handle = <&phy00>;
|
||||
pio-handle = <&ucc2pio>;
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
enet1: ucc@2200 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
cell-index = <3>;
|
||||
device-id = <3>;
|
||||
reg = <2200 200>;
|
||||
interrupts = <22>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock = <19>;
|
||||
tx-clock = <1a>;
|
||||
rx-clock-name = "clk9";
|
||||
tx-clock-name = "clk10";
|
||||
phy-handle = <&phy04>;
|
||||
pio-handle = <&ucc3pio>;
|
||||
};
|
||||
|
|
@ -232,65 +240,65 @@ ucc@2200 {
|
|||
mdio@3120 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3120 18>;
|
||||
device_type = "mdio";
|
||||
compatible = "ucc_geth_phy";
|
||||
reg = <0x3120 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
phy00:ethernet-phy@00 {
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <0>;
|
||||
reg = <0>;
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy04:ethernet-phy@04 {
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <0>;
|
||||
reg = <4>;
|
||||
reg = <0x4>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
qeic:qeic@80 {
|
||||
qeic:interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
device_type = "qeic";
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <80 80>;
|
||||
reg = <0x80 0x80>;
|
||||
big-endian;
|
||||
interrupts = <20 8 21 8>; //high:32 low:33
|
||||
interrupts = <32 0x8 33 0x8>; //high:32 low:33
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x10 AD16 (USB) */
|
||||
8000 0 0 1 &pic 11 8
|
||||
0x8000 0x0 0x0 0x1 &pic 17 0x8
|
||||
|
||||
/* IDSEL 0x11 AD17 (Mini1)*/
|
||||
8800 0 0 1 &pic 12 8
|
||||
8800 0 0 2 &pic 13 8
|
||||
8800 0 0 3 &pic 14 8
|
||||
8800 0 0 4 &pic 30 8
|
||||
0x8800 0x0 0x0 0x1 &pic 18 0x8
|
||||
0x8800 0x0 0x0 0x2 &pic 19 0x8
|
||||
0x8800 0x0 0x0 0x3 &pic 20 0x8
|
||||
0x8800 0x0 0x0 0x4 &pic 48 0x8
|
||||
|
||||
/* IDSEL 0x12 AD18 (PCI/Mini2) */
|
||||
9000 0 0 1 &pic 13 8
|
||||
9000 0 0 2 &pic 14 8
|
||||
9000 0 0 3 &pic 30 8
|
||||
9000 0 0 4 &pic 11 8>;
|
||||
0x9000 0x0 0x0 0x1 &pic 19 0x8
|
||||
0x9000 0x0 0x0 0x2 &pic 20 0x8
|
||||
0x9000 0x0 0x0 0x3 &pic 48 0x8
|
||||
0x9000 0x0 0x0 0x4 &pic 17 0x8>;
|
||||
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 10000000
|
||||
02000000 0 90000000 90000000 0 10000000
|
||||
01000000 0 d0000000 d0000000 0 04000000>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
|
||||
clock-frequency = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,23 +8,35 @@
|
|||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8349EMITX";
|
||||
compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8349@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-size = <8000>;
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
|
|
@ -33,222 +45,223 @@ PowerPC,8349@0 {
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 10000000>;
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc8349@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00000200>;
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <200 100>;
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <e 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <f 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <7000 1000>;
|
||||
interrupts = <10 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
usb@22000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <22000 1000>;
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <27 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <23000 1000>;
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <26 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
dr_mode = "peripheral";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
reg = <24520 20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
/* Vitesse 8201 */
|
||||
phy1c: ethernet-phy@1c {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <12 8>;
|
||||
reg = <1c>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
|
||||
/* Vitesse 7385 */
|
||||
phy1f: ethernet-phy@1f {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <12 8>;
|
||||
reg = <1f>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x1c>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <20 8 21 8 22 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
phy-handle = < &phy1c >;
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy1c>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <25000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <23 8 24 8 25 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
phy-handle = < &phy1f >;
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Vitesse 7385 isn't on the MDIO bus */
|
||||
fixed-link = <1 1 1000 0 0>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>; // from bootloader
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>; // from bootloader
|
||||
interrupts = <a 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 10000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000007e>;
|
||||
descriptor-types-mask = <01010ebf>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x10 - SATA */
|
||||
8000 0 0 1 &ipic 16 8 /* SATA_INTA */
|
||||
0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 10000000
|
||||
02000000 0 90000000 90000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pci@e0008600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci1: pci@e0008600 {
|
||||
cell-index = <2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0E - MiniPCI Slot */
|
||||
7000 0 0 1 &ipic 15 8 /* PCI_INTA */
|
||||
0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
|
||||
|
||||
/* IDSEL 0x0F - PCI Slot */
|
||||
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
|
||||
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <43 8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 a0000000 a0000000 0 10000000
|
||||
02000000 0 b0000000 b0000000 0 10000000
|
||||
01000000 0 00000000 e3000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
|
||||
0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
|
||||
>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <67 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008600 100>;
|
||||
reg = <0xe0008600 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8349e-localbus",
|
||||
"fsl,pq2pro-localbus";
|
||||
reg = <0xe0005000 0xd8>;
|
||||
ranges = <0x3 0x0 0xf0000000 0x210>;
|
||||
|
||||
|
||||
pata@3,0 {
|
||||
compatible = "fsl,mpc8349emitx-pata", "ata-generic";
|
||||
reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
|
||||
reg-shift = <1>;
|
||||
pio-mode = <6>;
|
||||
interrupts = <23 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,23 +8,33 @@
|
|||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8349EMITXGP";
|
||||
compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8349@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <8000>;
|
||||
i-cache-size = <8000>;
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
|
|
@ -33,148 +43,154 @@ PowerPC,8349@0 {
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 10000000>;
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc8349@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00000200>;
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <200 100>;
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <e 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <f 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <7000 1000>;
|
||||
interrupts = <10 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <23000 1000>;
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <26 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
dr_mode = "otg";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
reg = <24520 20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
/* Vitesse 8201 */
|
||||
phy1c: ethernet-phy@1c {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <12 8>;
|
||||
reg = <1c>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x1c>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <20 8 21 8 22 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
phy-handle = < &phy1c >;
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy1c>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>; // from bootloader
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>; // from bootloader
|
||||
interrupts = <a 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 10000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000007e>;
|
||||
descriptor-types-mask = <01010ebf>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci0: pci@e0008600 {
|
||||
cell-index = <2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0F - PCI Slot */
|
||||
7800 0 0 1 &ipic 14 8 /* PCI_INTA */
|
||||
7800 0 0 2 &ipic 15 8 /* PCI_INTB */
|
||||
0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
|
||||
0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
|
||||
>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <43 8>;
|
||||
bus-range = <1 1>;
|
||||
ranges = <42000000 0 a0000000 a0000000 0 10000000
|
||||
02000000 0 b0000000 b0000000 0 10000000
|
||||
01000000 0 00000000 e3000000 0 01000000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <67 0x8>;
|
||||
bus-range = <0x1 0x1>;
|
||||
ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008600 100>;
|
||||
reg = <0xe0008600 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,23 +9,34 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8349EMDS";
|
||||
compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8349@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <8000>; // L1, 32K
|
||||
i-cache-size = <8000>; // L1, 32K
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
|
|
@ -34,164 +45,152 @@ PowerPC,8349@0 {
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 10000000>; // 256MB at 0
|
||||
reg = <0x00000000 0x10000000>; // 256MB at 0
|
||||
};
|
||||
|
||||
bcsr@e2400000 {
|
||||
device_type = "board-control";
|
||||
reg = <e2400000 8000>;
|
||||
reg = <0xe2400000 0x8000>;
|
||||
};
|
||||
|
||||
soc8349@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00000200>;
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <200 100>;
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <e 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <68>;
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <f 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <7000 1000>;
|
||||
interrupts = <10 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI or SERIAL) are only types supportted for MPH */
|
||||
/* phy type (ULPI or SERIAL) are only types supported for MPH */
|
||||
/* port = 0 or 1 */
|
||||
usb@22000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <22000 1000>;
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <27 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <23000 1000>;
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <26 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
dr_mode = "otg";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
reg = <24520 20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <11 8>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <12 8>;
|
||||
reg = <1>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <20 8 21 8 22 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
phy-handle = < &phy0 >;
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <25000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <23 8 24 8 25 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
phy-handle = < &phy1 >;
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <a 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
|
|
@ -199,15 +198,15 @@ crypto@30000 {
|
|||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 10000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000007e>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <01010ebf>;
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
|
|
@ -220,127 +219,129 @@ ipic: pic@700 {
|
|||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
8800 0 0 1 &ipic 14 8
|
||||
8800 0 0 2 &ipic 15 8
|
||||
8800 0 0 3 &ipic 16 8
|
||||
8800 0 0 4 &ipic 17 8
|
||||
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x12 */
|
||||
9000 0 0 1 &ipic 16 8
|
||||
9000 0 0 2 &ipic 17 8
|
||||
9000 0 0 3 &ipic 14 8
|
||||
9000 0 0 4 &ipic 15 8
|
||||
0x9000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0x9000 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0x9000 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0x9000 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x13 */
|
||||
9800 0 0 1 &ipic 17 8
|
||||
9800 0 0 2 &ipic 14 8
|
||||
9800 0 0 3 &ipic 15 8
|
||||
9800 0 0 4 &ipic 16 8
|
||||
0x9800 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0x9800 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0x9800 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0x9800 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x15 */
|
||||
a800 0 0 1 &ipic 14 8
|
||||
a800 0 0 2 &ipic 15 8
|
||||
a800 0 0 3 &ipic 16 8
|
||||
a800 0 0 4 &ipic 17 8
|
||||
0xa800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0xa800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xa800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0xa800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x16 */
|
||||
b000 0 0 1 &ipic 17 8
|
||||
b000 0 0 2 &ipic 14 8
|
||||
b000 0 0 3 &ipic 15 8
|
||||
b000 0 0 4 &ipic 16 8
|
||||
0xb000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xb000 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0xb000 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0xb000 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x17 */
|
||||
b800 0 0 1 &ipic 16 8
|
||||
b800 0 0 2 &ipic 17 8
|
||||
b800 0 0 3 &ipic 14 8
|
||||
b800 0 0 4 &ipic 15 8
|
||||
0xb800 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0xb800 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0xb800 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0xb800 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x18 */
|
||||
c000 0 0 1 &ipic 15 8
|
||||
c000 0 0 2 &ipic 16 8
|
||||
c000 0 0 3 &ipic 17 8
|
||||
c000 0 0 4 &ipic 14 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
0xc000 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0xc000 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0xc000 0x0 0x0 0x3 &ipic 23 0x8
|
||||
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 90000000 90000000 0 10000000
|
||||
42000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 00100000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pci@e0008600 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci1: pci@e0008600 {
|
||||
cell-index = <2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
8800 0 0 1 &ipic 14 8
|
||||
8800 0 0 2 &ipic 15 8
|
||||
8800 0 0 3 &ipic 16 8
|
||||
8800 0 0 4 &ipic 17 8
|
||||
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x12 */
|
||||
9000 0 0 1 &ipic 16 8
|
||||
9000 0 0 2 &ipic 17 8
|
||||
9000 0 0 3 &ipic 14 8
|
||||
9000 0 0 4 &ipic 15 8
|
||||
0x9000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0x9000 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0x9000 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0x9000 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x13 */
|
||||
9800 0 0 1 &ipic 17 8
|
||||
9800 0 0 2 &ipic 14 8
|
||||
9800 0 0 3 &ipic 15 8
|
||||
9800 0 0 4 &ipic 16 8
|
||||
0x9800 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0x9800 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0x9800 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0x9800 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x15 */
|
||||
a800 0 0 1 &ipic 14 8
|
||||
a800 0 0 2 &ipic 15 8
|
||||
a800 0 0 3 &ipic 16 8
|
||||
a800 0 0 4 &ipic 17 8
|
||||
0xa800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0xa800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xa800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0xa800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x16 */
|
||||
b000 0 0 1 &ipic 17 8
|
||||
b000 0 0 2 &ipic 14 8
|
||||
b000 0 0 3 &ipic 15 8
|
||||
b000 0 0 4 &ipic 16 8
|
||||
0xb000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xb000 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0xb000 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0xb000 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x17 */
|
||||
b800 0 0 1 &ipic 16 8
|
||||
b800 0 0 2 &ipic 17 8
|
||||
b800 0 0 3 &ipic 14 8
|
||||
b800 0 0 4 &ipic 15 8
|
||||
0xb800 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0xb800 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0xb800 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0xb800 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x18 */
|
||||
c000 0 0 1 &ipic 15 8
|
||||
c000 0 0 2 &ipic 16 8
|
||||
c000 0 0 3 &ipic 17 8
|
||||
c000 0 0 4 &ipic 14 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
0xc000 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0xc000 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0xc000 0x0 0x0 0x3 &ipic 23 0x8
|
||||
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 b0000000 b0000000 0 10000000
|
||||
42000000 0 a0000000 a0000000 0 10000000
|
||||
01000000 0 00000000 e2100000 0 00100000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
|
||||
0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008600 100>;
|
||||
reg = <0xe0008600 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,122 +14,134 @@
|
|||
/memreserve/ 00000000 1000000;
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8360MDS";
|
||||
compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8360@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <8000>; // L1, 32K
|
||||
i-cache-size = <8000>; // L1, 32K
|
||||
timebase-frequency = <3EF1480>;
|
||||
bus-frequency = <FBC5200>;
|
||||
clock-frequency = <1F78A400>;
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>; // 32 bytes
|
||||
i-cache-line-size = <32>; // 32 bytes
|
||||
d-cache-size = <32768>; // L1, 32K
|
||||
i-cache-size = <32768>; // L1, 32K
|
||||
timebase-frequency = <66000000>;
|
||||
bus-frequency = <264000000>;
|
||||
clock-frequency = <528000000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 10000000>;
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
bcsr@f8000000 {
|
||||
device_type = "board-control";
|
||||
reg = <f8000000 8000>;
|
||||
reg = <0xf8000000 0x8000>;
|
||||
};
|
||||
|
||||
soc8360@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 00000200>;
|
||||
bus-frequency = <FBC5200>;
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <264000000>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <200 100>;
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <e 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <68>;
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <f 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
clock-frequency = <FBC5200>;
|
||||
interrupts = <9 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <264000000>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
clock-frequency = <FBC5200>;
|
||||
interrupts = <a 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <264000000>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
device_type = "crypto";
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <30000 10000>;
|
||||
interrupts = <b 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <18>;
|
||||
exec-units-mask = <0000007e>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
|
||||
descriptor-types-mask = <01010ebf>;
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <700 100>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
par_io@1400 {
|
||||
reg = <1400 100>;
|
||||
reg = <0x1400 0x100>;
|
||||
device_type = "par_io";
|
||||
num-ports = <7>;
|
||||
|
||||
|
|
@ -143,19 +155,19 @@ pio1: ucc_pin@01 {
|
|||
1 6 1 0 3 0 /* TxD4 */
|
||||
1 7 1 0 1 0 /* TxD5 */
|
||||
1 9 1 0 2 0 /* TxD6 */
|
||||
1 a 1 0 2 0 /* TxD7 */
|
||||
1 10 1 0 2 0 /* TxD7 */
|
||||
0 9 2 0 1 0 /* RxD0 */
|
||||
0 a 2 0 1 0 /* RxD1 */
|
||||
0 b 2 0 1 0 /* RxD2 */
|
||||
0 c 2 0 1 0 /* RxD3 */
|
||||
0 d 2 0 1 0 /* RxD4 */
|
||||
0 10 2 0 1 0 /* RxD1 */
|
||||
0 11 2 0 1 0 /* RxD2 */
|
||||
0 12 2 0 1 0 /* RxD3 */
|
||||
0 13 2 0 1 0 /* RxD4 */
|
||||
1 1 2 0 2 0 /* RxD5 */
|
||||
1 0 2 0 2 0 /* RxD6 */
|
||||
1 4 2 0 2 0 /* RxD7 */
|
||||
0 7 1 0 1 0 /* TX_EN */
|
||||
0 8 1 0 1 0 /* TX_ER */
|
||||
0 f 2 0 1 0 /* RX_DV */
|
||||
0 10 2 0 1 0 /* RX_ER */
|
||||
0 15 2 0 1 0 /* RX_DV */
|
||||
0 16 2 0 1 0 /* RX_ER */
|
||||
0 0 2 0 1 0 /* RX_CLK */
|
||||
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
|
||||
2 8 2 0 1 0>; /* GTX125 - CLK9 */
|
||||
|
|
@ -163,27 +175,27 @@ pio1: ucc_pin@01 {
|
|||
pio2: ucc_pin@02 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 11 1 0 1 0 /* TxD0 */
|
||||
0 12 1 0 1 0 /* TxD1 */
|
||||
0 13 1 0 1 0 /* TxD2 */
|
||||
0 14 1 0 1 0 /* TxD3 */
|
||||
0 17 1 0 1 0 /* TxD0 */
|
||||
0 18 1 0 1 0 /* TxD1 */
|
||||
0 19 1 0 1 0 /* TxD2 */
|
||||
0 20 1 0 1 0 /* TxD3 */
|
||||
1 2 1 0 1 0 /* TxD4 */
|
||||
1 3 1 0 2 0 /* TxD5 */
|
||||
1 5 1 0 3 0 /* TxD6 */
|
||||
1 8 1 0 3 0 /* TxD7 */
|
||||
0 17 2 0 1 0 /* RxD0 */
|
||||
0 18 2 0 1 0 /* RxD1 */
|
||||
0 19 2 0 1 0 /* RxD2 */
|
||||
0 1a 2 0 1 0 /* RxD3 */
|
||||
0 1b 2 0 1 0 /* RxD4 */
|
||||
1 c 2 0 2 0 /* RxD5 */
|
||||
1 d 2 0 3 0 /* RxD6 */
|
||||
1 b 2 0 2 0 /* RxD7 */
|
||||
0 15 1 0 1 0 /* TX_EN */
|
||||
0 16 1 0 1 0 /* TX_ER */
|
||||
0 1d 2 0 1 0 /* RX_DV */
|
||||
0 1e 2 0 1 0 /* RX_ER */
|
||||
0 1f 2 0 1 0 /* RX_CLK */
|
||||
0 23 2 0 1 0 /* RxD0 */
|
||||
0 24 2 0 1 0 /* RxD1 */
|
||||
0 25 2 0 1 0 /* RxD2 */
|
||||
0 26 2 0 1 0 /* RxD3 */
|
||||
0 27 2 0 1 0 /* RxD4 */
|
||||
1 12 2 0 2 0 /* RxD5 */
|
||||
1 13 2 0 3 0 /* RxD6 */
|
||||
1 11 2 0 2 0 /* RxD7 */
|
||||
0 21 1 0 1 0 /* TX_EN */
|
||||
0 22 1 0 1 0 /* TX_ER */
|
||||
0 29 2 0 1 0 /* RX_DV */
|
||||
0 30 2 0 1 0 /* RX_ER */
|
||||
0 31 2 0 1 0 /* RX_CLK */
|
||||
2 2 1 0 2 0 /* GTX_CLK - CLK10 */
|
||||
2 3 2 0 1 0 /* GTX125 - CLK4 */
|
||||
0 1 3 0 2 0 /* MDIO */
|
||||
|
|
@ -197,181 +209,174 @@ qe@e0100000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
model = "QE";
|
||||
ranges = <0 e0100000 00100000>;
|
||||
reg = <e0100000 480>;
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0x0 0xe0100000 0x00100000>;
|
||||
reg = <0xe0100000 0x480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <179A7B00>;
|
||||
bus-frequency = <396000000>;
|
||||
|
||||
muram@10000 {
|
||||
device_type = "muram";
|
||||
ranges = <0 00010000 0000c000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x00010000 0x0000c000>;
|
||||
|
||||
data-only@0{
|
||||
reg = <0 c000>;
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0xc000>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <4c0 40>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x4c0 0x40>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = < &qeic >;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
spi@500 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
reg = <500 40>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x500 0x40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = < &qeic >;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
usb@6c0 {
|
||||
device_type = "usb";
|
||||
compatible = "qe_udc";
|
||||
reg = <6c0 40 8B00 100>;
|
||||
interrupts = <b>;
|
||||
interrupt-parent = < &qeic >;
|
||||
reg = <0x6c0 0x40 0x8b00 0x100>;
|
||||
interrupts = <11>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "slave";
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
enet0: ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
cell-index = <1>;
|
||||
device-id = <1>;
|
||||
reg = <2000 200>;
|
||||
interrupts = <20>;
|
||||
interrupt-parent = < &qeic >;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock = <0>;
|
||||
tx-clock = <19>;
|
||||
phy-handle = < &phy0 >;
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk9";
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = < &pio1 >;
|
||||
pio-handle = <&pio1>;
|
||||
};
|
||||
|
||||
ucc@3000 {
|
||||
enet1: ucc@3000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
cell-index = <2>;
|
||||
device-id = <2>;
|
||||
reg = <3000 200>;
|
||||
interrupts = <21>;
|
||||
interrupt-parent = < &qeic >;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x3000 0x200>;
|
||||
interrupts = <33>;
|
||||
interrupt-parent = <&qeic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock = <0>;
|
||||
tx-clock = <14>;
|
||||
phy-handle = < &phy1 >;
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk4";
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
pio-handle = < &pio2 >;
|
||||
pio-handle = <&pio2>;
|
||||
};
|
||||
|
||||
mdio@2120 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2120 18>;
|
||||
device_type = "mdio";
|
||||
compatible = "ucc_geth_phy";
|
||||
reg = <0x2120 0x18>;
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
phy0: ethernet-phy@00 {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <11 8>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@01 {
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <12 8>;
|
||||
reg = <1>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
qeic: qeic@80 {
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
device_type = "qeic";
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <80 80>;
|
||||
reg = <0x80 0x80>;
|
||||
big-endian;
|
||||
interrupts = <20 8 21 8>; //high:32 low:33
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <32 0x8 33 0x8>; // high:32 low:33
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0008500 {
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 AD17 */
|
||||
8800 0 0 1 &ipic 14 8
|
||||
8800 0 0 2 &ipic 15 8
|
||||
8800 0 0 3 &ipic 16 8
|
||||
8800 0 0 4 &ipic 17 8
|
||||
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x12 AD18 */
|
||||
9000 0 0 1 &ipic 16 8
|
||||
9000 0 0 2 &ipic 17 8
|
||||
9000 0 0 3 &ipic 14 8
|
||||
9000 0 0 4 &ipic 15 8
|
||||
0x9000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0x9000 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0x9000 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0x9000 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x13 AD19 */
|
||||
9800 0 0 1 &ipic 17 8
|
||||
9800 0 0 2 &ipic 14 8
|
||||
9800 0 0 3 &ipic 15 8
|
||||
9800 0 0 4 &ipic 16 8
|
||||
0x9800 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0x9800 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0x9800 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0x9800 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x15 AD21*/
|
||||
a800 0 0 1 &ipic 14 8
|
||||
a800 0 0 2 &ipic 15 8
|
||||
a800 0 0 3 &ipic 16 8
|
||||
a800 0 0 4 &ipic 17 8
|
||||
0xa800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0xa800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xa800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0xa800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x16 AD22*/
|
||||
b000 0 0 1 &ipic 17 8
|
||||
b000 0 0 2 &ipic 14 8
|
||||
b000 0 0 3 &ipic 15 8
|
||||
b000 0 0 4 &ipic 16 8
|
||||
0xb000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xb000 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0xb000 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0xb000 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x17 AD23*/
|
||||
b800 0 0 1 &ipic 16 8
|
||||
b800 0 0 2 &ipic 17 8
|
||||
b800 0 0 3 &ipic 14 8
|
||||
b800 0 0 4 &ipic 15 8
|
||||
0xb800 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0xb800 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0xb800 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0xb800 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x18 AD24*/
|
||||
c000 0 0 1 &ipic 15 8
|
||||
c000 0 0 2 &ipic 16 8
|
||||
c000 0 0 3 &ipic 17 8
|
||||
c000 0 0 4 &ipic 14 8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
interrupts = <42 8>;
|
||||
0xc000 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0xc000 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0xc000 0x0 0x0 0x3 &ipic 23 0x8
|
||||
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 a0000000 a0000000 0 10000000
|
||||
42000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 e2000000 0 00100000>;
|
||||
clock-frequency = <3f940aa>;
|
||||
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008500 100>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
|
|
|||
280
arch/powerpc/boot/dts/mpc8377_mds.dts
Normal file
280
arch/powerpc/boot/dts/mpc8377_mds.dts
Normal file
|
|
@ -0,0 +1,280 @@
|
|||
/*
|
||||
* MPC8377E MDS Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "fsl,mpc8377emds";
|
||||
compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8377@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; // 512MB at 0
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
phy_type = "utmi_wide";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
model = "eSDHC";
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8379-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <44 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8379-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
interrupts = <45 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x12 */
|
||||
0x9000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0x9000 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0x9000 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0x9000 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x13 */
|
||||
0x9800 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0x9800 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0x9800 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0x9800 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x15 */
|
||||
0xa800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0xa800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xa800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0xa800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x16 */
|
||||
0xb000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xb000 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0xb000 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0xb000 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x17 */
|
||||
0xb800 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0xb800 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0xb800 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0xb800 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x18 */
|
||||
0xc000 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0xc000 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0xc000 0x0 0x0 0x3 &ipic 23 0x8
|
||||
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
||||
clock-frequency = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
296
arch/powerpc/boot/dts/mpc8377_rdb.dts
Normal file
296
arch/powerpc/boot/dts/mpc8377_rdb.dts
Normal file
|
|
@ -0,0 +1,296 @@
|
|||
/*
|
||||
* MPC8377E RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2007, 2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,mpc8377rdb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8377@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>; // 256MB at 0
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
// CS0 and CS1 are swapped when
|
||||
// booting from nand, but the
|
||||
// addresses are the same.
|
||||
ranges = <0x0 0x0 0xfe000000 0x00800000
|
||||
0x1 0x0 0xe0600000 0x00008000
|
||||
0x2 0x0 0xf0000000 0x00020000
|
||||
0x3 0x0 0xfa000000 0x00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8377-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <0x1 0x0 0x8000>;
|
||||
|
||||
u-boot@0 {
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@100000 {
|
||||
reg = <0x100000 0x300000>;
|
||||
};
|
||||
fs@400000 {
|
||||
reg = <0x400000 0x1c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
immr@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
device_type = "rtc";
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
device_type = "crypto";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <44 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
interrupts = <45 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: interrupt-controller@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
|
||||
|
||||
/* IDSEL AD14 IRQ6 inta */
|
||||
0x7000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
|
||||
/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
|
||||
0x7800 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0x7800 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0x7800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
|
||||
0xE000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xE000 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
266
arch/powerpc/boot/dts/mpc8378_mds.dts
Normal file
266
arch/powerpc/boot/dts/mpc8378_mds.dts
Normal file
|
|
@ -0,0 +1,266 @@
|
|||
/*
|
||||
* MPC8378E MDS Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "fsl,mpc8378emds";
|
||||
compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8378@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; // 512MB at 0
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
phy_type = "utmi_wide";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
model = "eSDHC";
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x12 */
|
||||
0x9000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0x9000 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0x9000 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0x9000 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x13 */
|
||||
0x9800 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0x9800 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0x9800 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0x9800 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x15 */
|
||||
0xa800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0xa800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xa800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0xa800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x16 */
|
||||
0xb000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xb000 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0xb000 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0xb000 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x17 */
|
||||
0xb800 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0xb800 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0xb800 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0xb800 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x18 */
|
||||
0xc000 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0xc000 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0xc000 0x0 0x0 0x3 &ipic 23 0x8
|
||||
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
||||
clock-frequency = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
282
arch/powerpc/boot/dts/mpc8378_rdb.dts
Normal file
282
arch/powerpc/boot/dts/mpc8378_rdb.dts
Normal file
|
|
@ -0,0 +1,282 @@
|
|||
/*
|
||||
* MPC8378E RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2007, 2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,mpc8378rdb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8378@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>; // 256MB at 0
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
// CS0 and CS1 are swapped when
|
||||
// booting from nand, but the
|
||||
// addresses are the same.
|
||||
ranges = <0x0 0x0 0xfe000000 0x00800000
|
||||
0x1 0x0 0xe0600000 0x00008000
|
||||
0x2 0x0 0xf0000000 0x00020000
|
||||
0x3 0x0 0xfa000000 0x00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8378-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <0x1 0x0 0x8000>;
|
||||
|
||||
u-boot@0 {
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@100000 {
|
||||
reg = <0x100000 0x300000>;
|
||||
};
|
||||
fs@400000 {
|
||||
reg = <0x400000 0x1c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
immr@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
device_type = "rtc";
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
device_type = "crypto";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: interrupt-controller@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
|
||||
|
||||
/* IDSEL AD14 IRQ6 inta */
|
||||
0x7000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
|
||||
/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
|
||||
0x7800 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0x7800 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0x7800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
|
||||
0xE000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xE000 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
294
arch/powerpc/boot/dts/mpc8379_mds.dts
Normal file
294
arch/powerpc/boot/dts/mpc8379_mds.dts
Normal file
|
|
@ -0,0 +1,294 @@
|
|||
/*
|
||||
* MPC8379E MDS Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "fsl,mpc8379emds";
|
||||
compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8379@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; // 512MB at 0
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
phy_type = "utmi_wide";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
};
|
||||
|
||||
sdhc@2e000 {
|
||||
model = "eSDHC";
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x2e000 0x1000>;
|
||||
interrupts = <42 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8379-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <44 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8379-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
interrupts = <45 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@1a000 {
|
||||
compatible = "fsl,mpc8379-sata";
|
||||
reg = <0x1a000 0x1000>;
|
||||
interrupts = <46 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@1b000 {
|
||||
compatible = "fsl,mpc8379-sata";
|
||||
reg = <0x1b000 0x1000>;
|
||||
interrupts = <47 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x12 */
|
||||
0x9000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0x9000 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0x9000 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0x9000 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x13 */
|
||||
0x9800 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0x9800 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0x9800 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0x9800 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x15 */
|
||||
0xa800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0xa800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xa800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0xa800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL 0x16 */
|
||||
0xb000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xb000 0x0 0x0 0x2 &ipic 20 0x8
|
||||
0xb000 0x0 0x0 0x3 &ipic 21 0x8
|
||||
0xb000 0x0 0x0 0x4 &ipic 22 0x8
|
||||
|
||||
/* IDSEL 0x17 */
|
||||
0xb800 0x0 0x0 0x1 &ipic 22 0x8
|
||||
0xb800 0x0 0x0 0x2 &ipic 23 0x8
|
||||
0xb800 0x0 0x0 0x3 &ipic 20 0x8
|
||||
0xb800 0x0 0x0 0x4 &ipic 21 0x8
|
||||
|
||||
/* IDSEL 0x18 */
|
||||
0xc000 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0xc000 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0xc000 0x0 0x0 0x3 &ipic 23 0x8
|
||||
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
|
||||
clock-frequency = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
310
arch/powerpc/boot/dts/mpc8379_rdb.dts
Normal file
310
arch/powerpc/boot/dts/mpc8379_rdb.dts
Normal file
|
|
@ -0,0 +1,310 @@
|
|||
/*
|
||||
* MPC8379E RDB Device Tree Source
|
||||
*
|
||||
* Copyright 2007, 2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,mpc8379rdb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8379@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>; // 256MB at 0
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
// CS0 and CS1 are swapped when
|
||||
// booting from nand, but the
|
||||
// addresses are the same.
|
||||
ranges = <0x0 0x0 0xfe000000 0x00800000
|
||||
0x1 0x0 0xe0600000 0x00008000
|
||||
0x2 0x0 0xf0000000 0x00020000
|
||||
0x3 0x0 0xfa000000 0x00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8379-fcm-nand",
|
||||
"fsl,elbc-fcm-nand";
|
||||
reg = <0x1 0x0 0x8000>;
|
||||
|
||||
u-boot@0 {
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
kernel@100000 {
|
||||
reg = <0x100000 0x300000>;
|
||||
};
|
||||
fs@400000 {
|
||||
reg = <0x400000 0x1c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
immr@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
device_type = "watchdog";
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
rtc@68 {
|
||||
device_type = "rtc";
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
phy_type = "utmi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <18 0x8>;
|
||||
reg = <0x3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
phy-connection-type = "mii";
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
model = "SEC3";
|
||||
device_type = "crypto";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
/* Rev. 3.0 geometry */
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x000001fe>;
|
||||
descriptor-types-mask = <0x03ab0ebf>;
|
||||
};
|
||||
|
||||
sata@18000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <44 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@19000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x19000 0x1000>;
|
||||
interrupts = <45 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@1a000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x1a000 0x1000>;
|
||||
interrupts = <46 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
sata@1b000 {
|
||||
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
|
||||
reg = <0x1b000 0x1000>;
|
||||
interrupts = <47 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: interrupt-controller@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
|
||||
|
||||
/* IDSEL AD14 IRQ6 inta */
|
||||
0x7000 0x0 0x0 0x1 &ipic 22 0x8
|
||||
|
||||
/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
|
||||
0x7800 0x0 0x0 0x1 &ipic 21 0x8
|
||||
0x7800 0x0 0x0 0x2 &ipic 22 0x8
|
||||
0x7800 0x0 0x0 0x4 &ipic 23 0x8
|
||||
|
||||
/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
|
||||
0xE000 0x0 0x0 0x1 &ipic 23 0x8
|
||||
0xE000 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
|
|
@ -16,6 +16,15 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -63,7 +72,9 @@ l2-cache-controller@20000 {
|
|||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -74,9 +85,9 @@ i2c@3000 {
|
|||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <24520 20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
|
|
@ -97,64 +108,44 @@ phy3: ethernet-phy@3 {
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <1d 2 1e 2 22 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <25000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <23 2 24 2 28 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet2: ethernet@26000 {
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "FEC";
|
||||
compatible = "gianfar";
|
||||
reg = <26000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>; // reg base, size
|
||||
|
|
@ -163,7 +154,8 @@ serial@4500 {
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>; // reg base, size
|
||||
|
|
@ -183,7 +175,8 @@ mpic: pic@40000 {
|
|||
};
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,15 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -63,7 +72,9 @@ l2-cache-controller@20000 {
|
|||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -74,9 +85,9 @@ i2c@3000 {
|
|||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <24520 20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
|
|
@ -91,9 +102,8 @@ phy1: ethernet-phy@1 {
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -104,9 +114,8 @@ ethernet@24000 {
|
|||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -117,7 +126,8 @@ ethernet@25000 {
|
|||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>; // reg base, size
|
||||
|
|
@ -126,7 +136,8 @@ serial@4500 {
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>; // reg base, size
|
||||
|
|
@ -183,7 +194,8 @@ cpmpic: pic@90c00 {
|
|||
};
|
||||
};
|
||||
|
||||
pci1: pci@e0008000 {
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <1f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -250,11 +262,12 @@ i8259@19000 {
|
|||
#interrupt-cells = <2>;
|
||||
compatible = "chrp,iic";
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&pci1>;
|
||||
interrupt-parent = <&pci0>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0009000 {
|
||||
pci1: pci@e0009000 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,17 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#cpus = <1>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -64,7 +75,9 @@ l2-cache-controller@20000 {
|
|||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -72,12 +85,23 @@ i2c@3000 {
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <2b 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <24520 20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <a 1>;
|
||||
|
|
@ -92,9 +116,8 @@ phy1: ethernet-phy@1 {
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -106,9 +129,8 @@ ethernet@24000 {
|
|||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@26000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -120,7 +142,8 @@ ethernet@26000 {
|
|||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
|
|
@ -129,7 +152,8 @@ serial@4500 {
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
|
|
@ -156,7 +180,8 @@ mpic: pic@40000 {
|
|||
};
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
|
|
@ -187,7 +212,8 @@ pci@e0008000 {
|
|||
reg = <e0008000 1000>;
|
||||
};
|
||||
|
||||
pcie@e0009000 {
|
||||
pci1: pcie@e0009000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
|
|
@ -223,7 +249,8 @@ pcie@0 {
|
|||
};
|
||||
};
|
||||
|
||||
pcie@e000a000 {
|
||||
pci2: pcie@e000a000 {
|
||||
cell-index = <2>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
|
|
@ -259,7 +286,8 @@ pcie@0 {
|
|||
};
|
||||
};
|
||||
|
||||
pcie@e000b000 {
|
||||
pci3: pcie@e000b000 {
|
||||
cell-index = <3>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
|
|
@ -276,9 +304,9 @@ pcie@e000b000 {
|
|||
interrupt-map = <
|
||||
// IDSEL 0x1c USB
|
||||
e000 0 0 1 &i8259 c 2
|
||||
e100 0 0 1 &i8259 9 2
|
||||
e200 0 0 1 &i8259 a 2
|
||||
e300 0 0 1 &i8259 b 2
|
||||
e100 0 0 2 &i8259 9 2
|
||||
e200 0 0 3 &i8259 a 2
|
||||
e300 0 0 4 &i8259 b 2
|
||||
|
||||
// IDSEL 0x1d Audio
|
||||
e800 0 0 1 &i8259 6 2
|
||||
|
|
@ -369,6 +397,5 @@ gpio@400 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,6 +16,20 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
/*
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
*/
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -63,7 +77,9 @@ l2-cache-controller@20000 {
|
|||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -71,12 +87,23 @@ i2c@3000 {
|
|||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <2b 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <24520 20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
|
|
@ -103,9 +130,8 @@ phy3: ethernet-phy@3 {
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -116,9 +142,8 @@ ethernet@24000 {
|
|||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -130,9 +155,8 @@ ethernet@25000 {
|
|||
};
|
||||
|
||||
/* eTSEC 3/4 are currently broken
|
||||
ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet2: ethernet@26000 {
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -143,9 +167,8 @@ ethernet@26000 {
|
|||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet3: ethernet@27000 {
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -157,7 +180,8 @@ ethernet@27000 {
|
|||
};
|
||||
*/
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>; // reg base, size
|
||||
|
|
@ -166,7 +190,8 @@ serial@4500 {
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>; // reg base, size
|
||||
|
|
@ -193,7 +218,8 @@ mpic: pic@40000 {
|
|||
};
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x4 (PCIX Slot 2) */
|
||||
|
|
@ -342,7 +368,8 @@ rtc@70 {
|
|||
};
|
||||
};
|
||||
|
||||
pci@e0009000 {
|
||||
pci1: pci@e0009000 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -366,7 +393,8 @@ a800 0 0 3 &mpic 2 1
|
|||
device_type = "pci";
|
||||
};
|
||||
|
||||
pcie@e000a000 {
|
||||
pci2: pcie@e000a000 {
|
||||
cell-index = <2>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,15 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -63,7 +72,9 @@ l2-cache-controller@20000 {
|
|||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -74,9 +85,9 @@ i2c@3000 {
|
|||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <24520 20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
|
|
@ -91,9 +102,8 @@ phy1: ethernet-phy@1 {
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -104,9 +114,8 @@ ethernet@24000 {
|
|||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -117,7 +126,8 @@ ethernet@25000 {
|
|||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>; // reg base, size
|
||||
|
|
@ -126,7 +136,8 @@ serial@4500 {
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>; // reg base, size
|
||||
|
|
@ -183,7 +194,8 @@ cpmpic: pic@90c00 {
|
|||
};
|
||||
};
|
||||
|
||||
pci1: pci@e0008000 {
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <1f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
@ -250,11 +262,12 @@ i8259@19000 {
|
|||
#interrupt-cells = <2>;
|
||||
compatible = "chrp,iic";
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&pci1>;
|
||||
interrupt-parent = <&pci0>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@e0009000 {
|
||||
pci1: pci@e0009000 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,16 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -63,11 +73,11 @@ l2-cache-controller@20000 {
|
|||
};
|
||||
|
||||
mdio@24520 {
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
reg = <24520 20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <24520 20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 1>;
|
||||
|
|
@ -94,36 +104,24 @@ phy3: ethernet-phy@3 {
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <1d 2 1e 2 22 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <25000 1000>;
|
||||
/*
|
||||
* address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <23 2 24 2 28 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
|
@ -174,7 +172,7 @@ cpmpic: pic@90c00 {
|
|||
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
|
||||
serial@91a00 {
|
||||
serial0: serial@91a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8560-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
|
|
@ -186,7 +184,7 @@ serial@91a00 {
|
|||
interrupt-parent = <&cpmpic>;
|
||||
};
|
||||
|
||||
serial@91a20 {
|
||||
serial1: serial@91a20 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8560-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
|
|
@ -198,17 +196,11 @@ serial@91a20 {
|
|||
interrupt-parent = <&cpmpic>;
|
||||
};
|
||||
|
||||
ethernet@91320 {
|
||||
enet2: ethernet@91320 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8560-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <91320 20 88500 100 913b0 1>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fsl,cpm-command = <16200300>;
|
||||
interrupts = <21 8>;
|
||||
|
|
@ -216,17 +208,11 @@ ethernet@91320 {
|
|||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
ethernet@91340 {
|
||||
enet3: ethernet@91340 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8560-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <91340 20 88600 100 913d0 1>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fsl,cpm-command = <1a400300>;
|
||||
interrupts = <22 8>;
|
||||
|
|
@ -236,7 +222,8 @@ ethernet@91340 {
|
|||
};
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
|
|
|
|||
|
|
@ -20,6 +20,17 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -74,7 +85,7 @@ l2-cache-controller@20000 {
|
|||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -90,7 +101,7 @@ rtc@68 {
|
|||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "i2c";
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -101,9 +112,9 @@ i2c@3100 {
|
|||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <24520 20>;
|
||||
|
||||
phy0: ethernet-phy@7 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <1 1>;
|
||||
|
|
@ -130,45 +141,32 @@ phy3: ethernet-phy@3 {
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <1d 2 1e 2 22 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <25000 1000>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <23 2 24 2 28 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
|
|
@ -183,7 +181,8 @@ global-utilities@e0000 { //global utilities block
|
|||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
|
|
@ -285,24 +284,28 @@ qe@e0080000 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
model = "QE";
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0 e0080000 00040000>;
|
||||
reg = <e0080000 480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <179A7B00>;
|
||||
|
||||
muram@10000 {
|
||||
device_type = "muram";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0 00010000 0000c000>;
|
||||
|
||||
data-only@0{
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0 c000>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@4c0 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <4c0 40>;
|
||||
interrupts = <2>;
|
||||
interrupt-parent = <&qeic>;
|
||||
|
|
@ -310,53 +313,43 @@ spi@4c0 {
|
|||
};
|
||||
|
||||
spi@500 {
|
||||
device_type = "spi";
|
||||
compatible = "fsl_spi";
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <500 40>;
|
||||
interrupts = <1>;
|
||||
interrupt-parent = <&qeic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
enet2: ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
cell-index = <1>;
|
||||
device-id = <1>;
|
||||
reg = <2000 200>;
|
||||
interrupts = <20>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock = <0>;
|
||||
tx-clock = <20>;
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
pio-handle = <&pio1>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ucc@3000 {
|
||||
enet3: ucc@3000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
model = "UCC";
|
||||
cell-index = <2>;
|
||||
device-id = <2>;
|
||||
reg = <3000 200>;
|
||||
interrupts = <21>;
|
||||
interrupt-parent = <&qeic>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
rx-clock = <0>;
|
||||
tx-clock = <20>;
|
||||
rx-clock-name = "none";
|
||||
tx-clock-name = "clk16";
|
||||
pio-handle = <&pio2>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
|
|
@ -366,8 +359,7 @@ mdio@2120 {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2120 18>;
|
||||
device_type = "mdio";
|
||||
compatible = "ucc_geth_phy";
|
||||
compatible = "fsl,ucc-mdio";
|
||||
|
||||
/* These are the same PHYs as on
|
||||
* gianfar's MDIO bus */
|
||||
|
|
@ -397,9 +389,9 @@ qe_phy3: ethernet-phy@03 {
|
|||
};
|
||||
};
|
||||
|
||||
qeic: qeic@80 {
|
||||
qeic: interrupt-controller@80 {
|
||||
interrupt-controller;
|
||||
device_type = "qeic";
|
||||
compatible = "fsl,qe-ic";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <80 80>;
|
||||
|
|
@ -410,7 +402,8 @@ qeic: qeic@80 {
|
|||
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x12 AD18 */
|
||||
|
|
@ -440,7 +433,8 @@ pci@e0008000 {
|
|||
};
|
||||
|
||||
/* PCI Express */
|
||||
pcie@e000a000 {
|
||||
pci1: pcie@e000a000 {
|
||||
cell-index = <2>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,18 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -69,7 +81,9 @@ l2-cache-controller@20000 {
|
|||
};
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -78,7 +92,9 @@ i2c@3000 {
|
|||
};
|
||||
|
||||
i2c@3100 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <2b 2>;
|
||||
|
|
@ -89,9 +105,9 @@ i2c@3100 {
|
|||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <24520 20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <a 1>;
|
||||
|
|
@ -114,9 +130,8 @@ phy3: ethernet-phy@3 {
|
|||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -128,9 +143,8 @@ ethernet@24000 {
|
|||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -142,9 +156,8 @@ ethernet@25000 {
|
|||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet2: ethernet@26000 {
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -156,9 +169,8 @@ ethernet@26000 {
|
|||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet3: ethernet@27000 {
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
|
|
@ -170,7 +182,8 @@ ethernet@27000 {
|
|||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
|
|
@ -179,7 +192,8 @@ serial@4500 {
|
|||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
|
|
@ -206,7 +220,8 @@ mpic: pic@40000 {
|
|||
};
|
||||
};
|
||||
|
||||
pcie@ffe08000 {
|
||||
pci0: pcie@ffe08000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
|
|
@ -319,9 +334,9 @@ pcie@ffe08000 {
|
|||
|
||||
// IDSEL 0x1c USB
|
||||
e000 0 0 1 &i8259 c 2
|
||||
e100 0 0 1 &i8259 9 2
|
||||
e200 0 0 1 &i8259 a 2
|
||||
e300 0 0 1 &i8259 b 2
|
||||
e100 0 0 2 &i8259 9 2
|
||||
e200 0 0 3 &i8259 a 2
|
||||
e300 0 0 4 &i8259 b 2
|
||||
|
||||
// IDSEL 0x1d Audio
|
||||
e800 0 0 1 &i8259 6 2
|
||||
|
|
@ -415,7 +430,8 @@ gpio@400 {
|
|||
|
||||
};
|
||||
|
||||
pcie@ffe09000 {
|
||||
pci1: pcie@ffe09000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
|
|
@ -451,7 +467,8 @@ pcie@0 {
|
|||
};
|
||||
};
|
||||
|
||||
pcie@ffe0a000 {
|
||||
pci2: pcie@ffe0a000 {
|
||||
cell-index = <2>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
|
|
@ -464,6 +481,7 @@ pcie@ffe0a000 {
|
|||
clock-frequency = <1fca055>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <1b 2>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 0 1
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
/*
|
||||
* MPC8610 HPCD Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Freescale Semiconductor Inc.
|
||||
* Copyright 2007-2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License Version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8610HPCD";
|
||||
|
|
@ -15,6 +16,13 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -22,11 +30,11 @@ cpus {
|
|||
PowerPC,8610@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <d# 32>; // bytes
|
||||
i-cache-line-size = <d# 32>; // bytes
|
||||
d-cache-size = <8000>; // L1, 32K
|
||||
i-cache-size = <8000>; // L1, 32K
|
||||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>; // L1
|
||||
i-cache-size = <32768>; // L1
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
|
|
@ -34,7 +42,7 @@ PowerPC,8610@0 {
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 20000000>; // 512M at 0x0
|
||||
reg = <0x00000000 0x20000000>; // 512M at 0x0
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
|
|
@ -42,57 +50,66 @@ soc@e0000000 {
|
|||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "soc";
|
||||
ranges = <0 e0000000 00100000>;
|
||||
reg = <e0000000 1000>;
|
||||
compatible = "fsl,mpc8610-immr", "simple-bus";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x1000>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
compatible = "fsl-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
cs4270:codec@4f {
|
||||
compatible = "cirrus,cs4270";
|
||||
reg = <0x4f>;
|
||||
/* MCLK source is a stand-alone oscillator */
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
device_type = "i2c";
|
||||
compatible = "fsl-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3100 100>;
|
||||
interrupts = <2b 2>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
serial@4500 {
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <2a 2>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <1c 2>;
|
||||
interrupts = <28 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
|
||||
mpic: interrupt-controller@40000 {
|
||||
clock-frequency = <0>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
|
|
@ -100,68 +117,173 @@ mpic: interrupt-controller@40000 {
|
|||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8610-guts";
|
||||
reg = <e0000 1000>;
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
i2s@16000 {
|
||||
compatible = "fsl,mpc8610-ssi";
|
||||
cell-index = <0>;
|
||||
reg = <0x16000 0x100>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <62 2>;
|
||||
fsl,mode = "i2s-slave";
|
||||
codec-handle = <&cs4270>;
|
||||
};
|
||||
|
||||
ssi@16100 {
|
||||
compatible = "fsl,mpc8610-ssi";
|
||||
cell-index = <1>;
|
||||
reg = <0x16100 0x100>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <63 2>;
|
||||
};
|
||||
|
||||
dma@21300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
|
||||
cell-index = <0>;
|
||||
reg = <0x21300 0x4>; /* DMA general status register */
|
||||
ranges = <0x0 0x21100 0x200>;
|
||||
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8610-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
cell-index = <0>;
|
||||
reg = <0x0 0x80>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <20 2>;
|
||||
};
|
||||
dma-channel@1 {
|
||||
compatible = "fsl,mpc8610-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
cell-index = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <21 2>;
|
||||
};
|
||||
dma-channel@2 {
|
||||
compatible = "fsl,mpc8610-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
cell-index = <2>;
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <22 2>;
|
||||
};
|
||||
dma-channel@3 {
|
||||
compatible = "fsl,mpc8610-dma-channel",
|
||||
"fsl,eloplus-dma-channel";
|
||||
cell-index = <3>;
|
||||
reg = <0x180 0x80>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <23 2>;
|
||||
};
|
||||
};
|
||||
|
||||
dma@c300 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
|
||||
cell-index = <1>;
|
||||
reg = <0xc300 0x4>; /* DMA general status register */
|
||||
ranges = <0x0 0xc100 0x200>;
|
||||
|
||||
dma-channel@0 {
|
||||
compatible = "fsl,mpc8610-dma-channel",
|
||||
"fsl,mpc8540-dma-channel";
|
||||
cell-index = <0>;
|
||||
reg = <0x0 0x80>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <60 2>;
|
||||
};
|
||||
dma-channel@1 {
|
||||
compatible = "fsl,mpc8610-dma-channel",
|
||||
"fsl,mpc8540-dma-channel";
|
||||
cell-index = <1>;
|
||||
reg = <0x80 0x80>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <61 2>;
|
||||
};
|
||||
dma-channel@2 {
|
||||
compatible = "fsl,mpc8610-dma-channel",
|
||||
"fsl,mpc8540-dma-channel";
|
||||
cell-index = <2>;
|
||||
reg = <0x100 0x80>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <62 2>;
|
||||
};
|
||||
dma-channel@3 {
|
||||
compatible = "fsl,mpc8610-dma-channel",
|
||||
"fsl,mpc8540-dma-channel";
|
||||
cell-index = <3>;
|
||||
reg = <0x180 0x80>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <63 2>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci@e0008000 {
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8610-pci";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e0008000 1000>;
|
||||
reg = <0xe0008000 0x1000>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <02000000 0 80000000 80000000 0 10000000
|
||||
01000000 0 00000000 e1000000 0 00100000>;
|
||||
clock-frequency = <1fca055>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x11 */
|
||||
8800 0 0 1 &mpic 4 1
|
||||
8800 0 0 2 &mpic 5 1
|
||||
8800 0 0 3 &mpic 6 1
|
||||
8800 0 0 4 &mpic 7 1
|
||||
0x8800 0 0 1 &mpic 4 1
|
||||
0x8800 0 0 2 &mpic 5 1
|
||||
0x8800 0 0 3 &mpic 6 1
|
||||
0x8800 0 0 4 &mpic 7 1
|
||||
|
||||
/* IDSEL 0x12 */
|
||||
9000 0 0 1 &mpic 5 1
|
||||
9000 0 0 2 &mpic 6 1
|
||||
9000 0 0 3 &mpic 7 1
|
||||
9000 0 0 4 &mpic 4 1
|
||||
0x9000 0 0 1 &mpic 5 1
|
||||
0x9000 0 0 2 &mpic 6 1
|
||||
0x9000 0 0 3 &mpic 7 1
|
||||
0x9000 0 0 4 &mpic 4 1
|
||||
>;
|
||||
};
|
||||
|
||||
pcie@e000a000 {
|
||||
pci1: pcie@e000a000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <e000a000 1000>;
|
||||
reg = <0xe000a000 0x1000>;
|
||||
bus-range = <1 3>;
|
||||
ranges = <02000000 0 a0000000 a0000000 0 10000000
|
||||
01000000 0 00000000 e3000000 0 00100000>;
|
||||
clock-frequency = <1fca055>;
|
||||
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <1a 2>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupts = <26 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x1b */
|
||||
d800 0 0 1 &mpic 2 1
|
||||
0xd800 0 0 1 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x1c*/
|
||||
e000 0 0 1 &mpic 1 1
|
||||
e000 0 0 2 &mpic 1 1
|
||||
e000 0 0 3 &mpic 1 1
|
||||
e000 0 0 4 &mpic 1 1
|
||||
0xe000 0 0 1 &mpic 1 1
|
||||
0xe000 0 0 2 &mpic 1 1
|
||||
0xe000 0 0 3 &mpic 1 1
|
||||
0xe000 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x1f */
|
||||
f800 0 0 1 &mpic 3 0
|
||||
f800 0 0 2 &mpic 0 1
|
||||
0xf800 0 0 1 &mpic 3 0
|
||||
0xf800 0 0 2 &mpic 0 1
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
|
|
@ -169,22 +291,22 @@ pcie@0 {
|
|||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 a0000000
|
||||
02000000 0 a0000000
|
||||
0 10000000
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
ranges = <0x02000000 0x0 0xa0000000
|
||||
0x02000000 0x0 0xa0000000
|
||||
0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
uli1575@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
ranges = <02000000 0 a0000000
|
||||
02000000 0 a0000000
|
||||
0 10000000
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
ranges = <0x02000000 0x0 0xa0000000
|
||||
0x02000000 0x0 0xa0000000
|
||||
0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "MPC8641HPCN";
|
||||
|
|
@ -16,6 +17,17 @@ / {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -23,22 +35,22 @@ cpus {
|
|||
PowerPC,8641@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <8000>; // L1, 32K
|
||||
i-cache-size = <8000>; // L1, 32K
|
||||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>; // L1
|
||||
i-cache-size = <32768>; // L1
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
PowerPC,8641@1 {
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-size = <8000>; // L1, 32K
|
||||
i-cache-size = <8000>; // L1, 32K
|
||||
timebase-frequency = <0>; // 33 MHz, from uboot
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>; // From uboot
|
||||
clock-frequency = <0>; // From uboot
|
||||
};
|
||||
|
|
@ -46,31 +58,77 @@ PowerPC,8641@1 {
|
|||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 40000000>; // 1G at 0x0
|
||||
reg = <0x00000000 0x40000000>; // 1G at 0x0
|
||||
};
|
||||
|
||||
localbus@f8005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8641-localbus", "simple-bus";
|
||||
reg = <0xf8005000 0x1000>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ranges = <0 0 0xff800000 0x00800000
|
||||
1 0 0xfe000000 0x01000000
|
||||
2 0 0xf8200000 0x00100000
|
||||
3 0 0xf8100000 0x00100000>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x00800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x00000000 0x00300000>;
|
||||
};
|
||||
partition@300000 {
|
||||
label = "firmware b";
|
||||
reg = <0x00300000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "fs";
|
||||
reg = <0x00400000 0x00300000>;
|
||||
};
|
||||
partition@700000 {
|
||||
label = "firmware a";
|
||||
reg = <0x00700000 0x00100000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc8641@f8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <00000000 f8000000 00100000>;
|
||||
reg = <f8000000 00001000>; // CCSRBAR
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf8000000 0x00100000>;
|
||||
reg = <0xf8000000 0x00001000>; // CCSRBAR
|
||||
bus-frequency = <0>;
|
||||
|
||||
i2c@3000 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3000 100>;
|
||||
interrupts = <2b 2>;
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
device_type = "i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <3100 100>;
|
||||
interrupts = <2b 2>;
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
|
@ -78,129 +136,104 @@ i2c@3100 {
|
|||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "mdio";
|
||||
compatible = "gianfar";
|
||||
reg = <24520 20>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <a 1>;
|
||||
interrupts = <10 1>;
|
||||
reg = <0>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <a 1>;
|
||||
interrupts = <10 1>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <a 1>;
|
||||
interrupts = <10 1>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <a 1>;
|
||||
interrupts = <10 1>;
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <24000 1000>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <1d 2 1e 2 22 2>;
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <25000 1000>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <23 2 24 2 28 2>;
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@26000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet2: ethernet@26000 {
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <26000 1000>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <1F 2 20 2 21 2>;
|
||||
interrupts = <31 2 32 2 33 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@27000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enet3: ethernet@27000 {
|
||||
cell-index = <3>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <27000 1000>;
|
||||
/*
|
||||
* mac-address is deprecated and will be removed
|
||||
* in 2.6.25. Only recent versions of
|
||||
* U-Boot support local-mac-address, however.
|
||||
*/
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
reg = <0x27000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <25 2 26 2 27 2>;
|
||||
interrupts = <37 2 38 2 39 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
serial@4500 {
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4500 100>;
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <2a 2>;
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial@4600 {
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <4600 100>;
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <1c 2>;
|
||||
interrupts = <28 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
|
|
@ -209,7 +242,7 @@ mpic: pic@40000 {
|
|||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <40000 40000>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
|
|
@ -217,138 +250,139 @@ mpic: pic@40000 {
|
|||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8641-guts";
|
||||
reg = <e0000 1000>;
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pcie@f8008000 {
|
||||
pci0: pcie@f8008000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <f8008000 1000>;
|
||||
bus-range = <0 ff>;
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e2000000 0 00100000>;
|
||||
clock-frequency = <1fca055>;
|
||||
reg = <0xf8008000 0x1000>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
interrupt-map-mask = <ff00 0 0 7>;
|
||||
interrupts = <24 2>;
|
||||
interrupt-map-mask = <0xff00 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x11 func 0 - PCI slot 1 */
|
||||
8800 0 0 1 &mpic 2 1
|
||||
8800 0 0 2 &mpic 3 1
|
||||
8800 0 0 3 &mpic 4 1
|
||||
8800 0 0 4 &mpic 1 1
|
||||
0x8800 0 0 1 &mpic 2 1
|
||||
0x8800 0 0 2 &mpic 3 1
|
||||
0x8800 0 0 3 &mpic 4 1
|
||||
0x8800 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x11 func 1 - PCI slot 1 */
|
||||
8900 0 0 1 &mpic 2 1
|
||||
8900 0 0 2 &mpic 3 1
|
||||
8900 0 0 3 &mpic 4 1
|
||||
8900 0 0 4 &mpic 1 1
|
||||
0x8900 0 0 1 &mpic 2 1
|
||||
0x8900 0 0 2 &mpic 3 1
|
||||
0x8900 0 0 3 &mpic 4 1
|
||||
0x8900 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x11 func 2 - PCI slot 1 */
|
||||
8a00 0 0 1 &mpic 2 1
|
||||
8a00 0 0 2 &mpic 3 1
|
||||
8a00 0 0 3 &mpic 4 1
|
||||
8a00 0 0 4 &mpic 1 1
|
||||
0x8a00 0 0 1 &mpic 2 1
|
||||
0x8a00 0 0 2 &mpic 3 1
|
||||
0x8a00 0 0 3 &mpic 4 1
|
||||
0x8a00 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x11 func 3 - PCI slot 1 */
|
||||
8b00 0 0 1 &mpic 2 1
|
||||
8b00 0 0 2 &mpic 3 1
|
||||
8b00 0 0 3 &mpic 4 1
|
||||
8b00 0 0 4 &mpic 1 1
|
||||
0x8b00 0 0 1 &mpic 2 1
|
||||
0x8b00 0 0 2 &mpic 3 1
|
||||
0x8b00 0 0 3 &mpic 4 1
|
||||
0x8b00 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x11 func 4 - PCI slot 1 */
|
||||
8c00 0 0 1 &mpic 2 1
|
||||
8c00 0 0 2 &mpic 3 1
|
||||
8c00 0 0 3 &mpic 4 1
|
||||
8c00 0 0 4 &mpic 1 1
|
||||
0x8c00 0 0 1 &mpic 2 1
|
||||
0x8c00 0 0 2 &mpic 3 1
|
||||
0x8c00 0 0 3 &mpic 4 1
|
||||
0x8c00 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x11 func 5 - PCI slot 1 */
|
||||
8d00 0 0 1 &mpic 2 1
|
||||
8d00 0 0 2 &mpic 3 1
|
||||
8d00 0 0 3 &mpic 4 1
|
||||
8d00 0 0 4 &mpic 1 1
|
||||
0x8d00 0 0 1 &mpic 2 1
|
||||
0x8d00 0 0 2 &mpic 3 1
|
||||
0x8d00 0 0 3 &mpic 4 1
|
||||
0x8d00 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x11 func 6 - PCI slot 1 */
|
||||
8e00 0 0 1 &mpic 2 1
|
||||
8e00 0 0 2 &mpic 3 1
|
||||
8e00 0 0 3 &mpic 4 1
|
||||
8e00 0 0 4 &mpic 1 1
|
||||
0x8e00 0 0 1 &mpic 2 1
|
||||
0x8e00 0 0 2 &mpic 3 1
|
||||
0x8e00 0 0 3 &mpic 4 1
|
||||
0x8e00 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x11 func 7 - PCI slot 1 */
|
||||
8f00 0 0 1 &mpic 2 1
|
||||
8f00 0 0 2 &mpic 3 1
|
||||
8f00 0 0 3 &mpic 4 1
|
||||
8f00 0 0 4 &mpic 1 1
|
||||
0x8f00 0 0 1 &mpic 2 1
|
||||
0x8f00 0 0 2 &mpic 3 1
|
||||
0x8f00 0 0 3 &mpic 4 1
|
||||
0x8f00 0 0 4 &mpic 1 1
|
||||
|
||||
/* IDSEL 0x12 func 0 - PCI slot 2 */
|
||||
9000 0 0 1 &mpic 3 1
|
||||
9000 0 0 2 &mpic 4 1
|
||||
9000 0 0 3 &mpic 1 1
|
||||
9000 0 0 4 &mpic 2 1
|
||||
0x9000 0 0 1 &mpic 3 1
|
||||
0x9000 0 0 2 &mpic 4 1
|
||||
0x9000 0 0 3 &mpic 1 1
|
||||
0x9000 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x12 func 1 - PCI slot 2 */
|
||||
9100 0 0 1 &mpic 3 1
|
||||
9100 0 0 2 &mpic 4 1
|
||||
9100 0 0 3 &mpic 1 1
|
||||
9100 0 0 4 &mpic 2 1
|
||||
0x9100 0 0 1 &mpic 3 1
|
||||
0x9100 0 0 2 &mpic 4 1
|
||||
0x9100 0 0 3 &mpic 1 1
|
||||
0x9100 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x12 func 2 - PCI slot 2 */
|
||||
9200 0 0 1 &mpic 3 1
|
||||
9200 0 0 2 &mpic 4 1
|
||||
9200 0 0 3 &mpic 1 1
|
||||
9200 0 0 4 &mpic 2 1
|
||||
0x9200 0 0 1 &mpic 3 1
|
||||
0x9200 0 0 2 &mpic 4 1
|
||||
0x9200 0 0 3 &mpic 1 1
|
||||
0x9200 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x12 func 3 - PCI slot 2 */
|
||||
9300 0 0 1 &mpic 3 1
|
||||
9300 0 0 2 &mpic 4 1
|
||||
9300 0 0 3 &mpic 1 1
|
||||
9300 0 0 4 &mpic 2 1
|
||||
0x9300 0 0 1 &mpic 3 1
|
||||
0x9300 0 0 2 &mpic 4 1
|
||||
0x9300 0 0 3 &mpic 1 1
|
||||
0x9300 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x12 func 4 - PCI slot 2 */
|
||||
9400 0 0 1 &mpic 3 1
|
||||
9400 0 0 2 &mpic 4 1
|
||||
9400 0 0 3 &mpic 1 1
|
||||
9400 0 0 4 &mpic 2 1
|
||||
0x9400 0 0 1 &mpic 3 1
|
||||
0x9400 0 0 2 &mpic 4 1
|
||||
0x9400 0 0 3 &mpic 1 1
|
||||
0x9400 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x12 func 5 - PCI slot 2 */
|
||||
9500 0 0 1 &mpic 3 1
|
||||
9500 0 0 2 &mpic 4 1
|
||||
9500 0 0 3 &mpic 1 1
|
||||
9500 0 0 4 &mpic 2 1
|
||||
0x9500 0 0 1 &mpic 3 1
|
||||
0x9500 0 0 2 &mpic 4 1
|
||||
0x9500 0 0 3 &mpic 1 1
|
||||
0x9500 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x12 func 6 - PCI slot 2 */
|
||||
9600 0 0 1 &mpic 3 1
|
||||
9600 0 0 2 &mpic 4 1
|
||||
9600 0 0 3 &mpic 1 1
|
||||
9600 0 0 4 &mpic 2 1
|
||||
0x9600 0 0 1 &mpic 3 1
|
||||
0x9600 0 0 2 &mpic 4 1
|
||||
0x9600 0 0 3 &mpic 1 1
|
||||
0x9600 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x12 func 7 - PCI slot 2 */
|
||||
9700 0 0 1 &mpic 3 1
|
||||
9700 0 0 2 &mpic 4 1
|
||||
9700 0 0 3 &mpic 1 1
|
||||
9700 0 0 4 &mpic 2 1
|
||||
0x9700 0 0 1 &mpic 3 1
|
||||
0x9700 0 0 2 &mpic 4 1
|
||||
0x9700 0 0 3 &mpic 1 1
|
||||
0x9700 0 0 4 &mpic 2 1
|
||||
|
||||
// IDSEL 0x1c USB
|
||||
e000 0 0 1 &i8259 c 2
|
||||
e100 0 0 1 &i8259 9 2
|
||||
e200 0 0 1 &i8259 a 2
|
||||
e300 0 0 1 &i8259 b 2
|
||||
0xe000 0 0 1 &i8259 12 2
|
||||
0xe100 0 0 2 &i8259 9 2
|
||||
0xe200 0 0 3 &i8259 10 2
|
||||
0xe300 0 0 4 &i8259 112
|
||||
|
||||
// IDSEL 0x1d Audio
|
||||
e800 0 0 1 &i8259 6 2
|
||||
0xe800 0 0 1 &i8259 6 2
|
||||
|
||||
// IDSEL 0x1e Legacy
|
||||
f000 0 0 1 &i8259 7 2
|
||||
f100 0 0 1 &i8259 7 2
|
||||
0xf000 0 0 1 &i8259 7 2
|
||||
0xf100 0 0 1 &i8259 7 2
|
||||
|
||||
// IDSEL 0x1f IDE/SATA
|
||||
f800 0 0 1 &i8259 e 2
|
||||
f900 0 0 1 &i8259 5 2
|
||||
0xf800 0 0 1 &i8259 14 2
|
||||
0xf900 0 0 1 &i8259 5 2
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
|
|
@ -356,37 +390,37 @@ pcie@0 {
|
|||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 80000000
|
||||
02000000 0 80000000
|
||||
0 20000000
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
uli1575@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
ranges = <02000000 0 80000000
|
||||
02000000 0 80000000
|
||||
0 20000000
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
ranges = <0x02000000 0x0 0x80000000
|
||||
0x02000000 0x0 0x80000000
|
||||
0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
isa@1e {
|
||||
device_type = "isa";
|
||||
#interrupt-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
reg = <f000 0 0 0 0>;
|
||||
ranges = <1 0 01000000 0 0
|
||||
00001000>;
|
||||
reg = <0xf000 0 0 0 0>;
|
||||
ranges = <1 0 0x01000000 0 0
|
||||
0x00001000>;
|
||||
interrupt-parent = <&i8259>;
|
||||
|
||||
i8259: interrupt-controller@20 {
|
||||
reg = <1 20 2
|
||||
1 a0 2
|
||||
1 4d0 2>;
|
||||
reg = <1 0x20 2
|
||||
1 0xa0 2
|
||||
1 0x4d0 2>;
|
||||
interrupt-controller;
|
||||
device_type = "interrupt-controller";
|
||||
#address-cells = <0>;
|
||||
|
|
@ -399,8 +433,8 @@ i8259: interrupt-controller@20 {
|
|||
i8042@60 {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
reg = <1 60 1 1 64 1>;
|
||||
interrupts = <1 3 c 3>;
|
||||
reg = <1 0x60 1 1 0x64 1>;
|
||||
interrupts = <1 3 12 3>;
|
||||
interrupt-parent =
|
||||
<&i8259>;
|
||||
|
||||
|
|
@ -418,11 +452,11 @@ mouse@1 {
|
|||
rtc@70 {
|
||||
compatible =
|
||||
"pnpPNP,b00";
|
||||
reg = <1 70 2>;
|
||||
reg = <1 0x70 2>;
|
||||
};
|
||||
|
||||
gpio@400 {
|
||||
reg = <1 400 80>;
|
||||
reg = <1 0x400 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -430,39 +464,40 @@ gpio@400 {
|
|||
|
||||
};
|
||||
|
||||
pcie@f8009000 {
|
||||
pci1: pcie@f8009000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,mpc8641-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <f8009000 1000>;
|
||||
bus-range = <0 ff>;
|
||||
ranges = <02000000 0 a0000000 a0000000 0 20000000
|
||||
01000000 0 00000000 e3000000 0 00100000>;
|
||||
clock-frequency = <1fca055>;
|
||||
reg = <0xf8009000 0x1000>;
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
|
||||
clock-frequency = <33333333>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <19 2>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupts = <25 2>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 4 1
|
||||
0000 0 0 2 &mpic 5 1
|
||||
0000 0 0 3 &mpic 6 1
|
||||
0000 0 0 4 &mpic 7 1
|
||||
0x0000 0 0 1 &mpic 4 1
|
||||
0x0000 0 0 2 &mpic 5 1
|
||||
0x0000 0 0 3 &mpic 6 1
|
||||
0x0000 0 0 4 &mpic 7 1
|
||||
>;
|
||||
pcie@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <02000000 0 a0000000
|
||||
02000000 0 a0000000
|
||||
0 20000000
|
||||
ranges = <0x02000000 0x0 0xa0000000
|
||||
0x02000000 0x0 0xa0000000
|
||||
0x0 0x20000000
|
||||
|
||||
01000000 0 00000000
|
||||
01000000 0 00000000
|
||||
0 00100000>;
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
|
||||
/ {
|
||||
model = "MPC866ADS";
|
||||
compatible = "mpc8xx";
|
||||
compatible = "fsl,mpc866ads";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -23,15 +23,15 @@ cpus {
|
|||
PowerPC,866@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>; // 32 bytes
|
||||
i-cache-line-size = <20>; // 32 bytes
|
||||
d-cache-line-size = <10>; // 16 bytes
|
||||
i-cache-line-size = <10>; // 16 bytes
|
||||
d-cache-size = <2000>; // L1, 8K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <f 2>; // decrementer interrupt
|
||||
interrupt-parent = <&Mpc8xx_pic>;
|
||||
interrupt-parent = <&PIC>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -40,107 +40,139 @@ memory {
|
|||
reg = <00000000 800000>;
|
||||
};
|
||||
|
||||
soc866@ff000000 {
|
||||
localbus@ff000100 {
|
||||
compatible = "fsl,mpc866-localbus", "fsl,pq1-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <ff000100 40>;
|
||||
|
||||
ranges = <
|
||||
1 0 ff080000 00008000
|
||||
5 0 ff0a0000 00008000
|
||||
>;
|
||||
|
||||
board-control@1,0 {
|
||||
reg = <1 0 20 5 300 4>;
|
||||
compatible = "fsl,mpc866ads-bcsr";
|
||||
};
|
||||
};
|
||||
|
||||
soc@ff000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 ff000000 00100000>;
|
||||
reg = <ff000000 00000200>;
|
||||
bus-frequency = <0>;
|
||||
mdio@e80 {
|
||||
device_type = "mdio";
|
||||
compatible = "fs_enet";
|
||||
reg = <e80 8>;
|
||||
|
||||
mdio@e00 {
|
||||
compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
|
||||
reg = <e00 188>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
phy: ethernet-phy@f {
|
||||
PHY: ethernet-phy@f {
|
||||
reg = <f>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
fec@e00 {
|
||||
ethernet@e00 {
|
||||
device_type = "network";
|
||||
compatible = "fs_enet";
|
||||
model = "FEC";
|
||||
device-id = <1>;
|
||||
compatible = "fsl,mpc866-fec-enet",
|
||||
"fsl,pq1-fec-enet";
|
||||
reg = <e00 188>;
|
||||
mac-address = [ 00 00 0C 00 01 FD ];
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <3 1>;
|
||||
interrupt-parent = <&Mpc8xx_pic>;
|
||||
phy-handle = <&Phy>;
|
||||
interrupt-parent = <&PIC>;
|
||||
phy-handle = <&PHY>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
mpc8xx_pic: pic@ff000000 {
|
||||
PIC: pic@0 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 24>;
|
||||
device_type = "mpc8xx-pic";
|
||||
compatible = "CPM";
|
||||
compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
|
||||
};
|
||||
|
||||
cpm@ff000000 {
|
||||
cpm@9c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "cpm";
|
||||
model = "CPM";
|
||||
ranges = <0 0 4000>;
|
||||
reg = <860 f0>;
|
||||
command-proc = <9c0>;
|
||||
compatible = "fsl,mpc866-cpm", "fsl,cpm1";
|
||||
ranges;
|
||||
reg = <9c0 40>;
|
||||
brg-frequency = <0>;
|
||||
interrupts = <0 2>; // cpm error interrupt
|
||||
interrupt-parent = <&Cpm_pic>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
|
||||
cpm_pic: pic@930 {
|
||||
muram@2000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 2000 2000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 1c00>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@9f0 {
|
||||
compatible = "fsl,mpc866-brg",
|
||||
"fsl,cpm1-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <9f0 10>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
CPM_PIC: pic@930 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <5 2 0 2>;
|
||||
interrupt-parent = <&Mpc8xx_pic>;
|
||||
interrupt-parent = <&PIC>;
|
||||
reg = <930 20>;
|
||||
device_type = "cpm-pic";
|
||||
compatible = "CPM";
|
||||
compatible = "fsl,mpc866-cpm-pic",
|
||||
"fsl,cpm1-pic";
|
||||
};
|
||||
|
||||
smc@a80 {
|
||||
|
||||
serial@a80 {
|
||||
device_type = "serial";
|
||||
compatible = "cpm_uart";
|
||||
model = "SMC";
|
||||
device-id = <1>;
|
||||
compatible = "fsl,mpc866-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <a80 10 3e80 40>;
|
||||
clock-setup = <00ffffff 0>;
|
||||
rx-clock = <1>;
|
||||
tx-clock = <1>;
|
||||
current-speed = <0>;
|
||||
interrupts = <4 3>;
|
||||
interrupt-parent = <&Cpm_pic>;
|
||||
interrupts = <4>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0090>;
|
||||
};
|
||||
|
||||
smc@a90 {
|
||||
serial@a90 {
|
||||
device_type = "serial";
|
||||
compatible = "cpm_uart";
|
||||
model = "SMC";
|
||||
device-id = <2>;
|
||||
reg = <a90 20 3f80 40>;
|
||||
clock-setup = <ff00ffff 90000>;
|
||||
rx-clock = <2>;
|
||||
tx-clock = <2>;
|
||||
current-speed = <0>;
|
||||
interrupts = <3 3>;
|
||||
interrupt-parent = <&Cpm_pic>;
|
||||
compatible = "fsl,mpc866-smc-uart",
|
||||
"fsl,cpm1-smc-uart";
|
||||
reg = <a90 10 3f80 40>;
|
||||
interrupts = <3>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-brg = <2>;
|
||||
fsl,cpm-command = <00d0>;
|
||||
};
|
||||
|
||||
scc@a00 {
|
||||
ethernet@a00 {
|
||||
device_type = "network";
|
||||
compatible = "fs_enet";
|
||||
model = "SCC";
|
||||
device-id = <1>;
|
||||
reg = <a00 18 3c00 80>;
|
||||
mac-address = [ 00 00 0C 00 03 FD ];
|
||||
interrupts = <1e 3>;
|
||||
interrupt-parent = <&Cpm_pic>;
|
||||
compatible = "fsl,mpc866-scc-enet",
|
||||
"fsl,cpm1-scc-enet";
|
||||
reg = <a00 18 3c00 100>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <1e>;
|
||||
interrupt-parent = <&CPM_PIC>;
|
||||
fsl,cpm-command = <0000>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/soc/cpm/serial@a80";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
353
arch/powerpc/boot/dts/rainier.dts
Normal file
353
arch/powerpc/boot/dts/rainier.dts
Normal file
|
|
@ -0,0 +1,353 @@
|
|||
/*
|
||||
* Device Tree Source for AMCC Rainier
|
||||
*
|
||||
* Based on Sequoia code
|
||||
* Copyright (c) 2007 MontaVista Software, Inc.
|
||||
*
|
||||
* FIXME: Draft only!
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,rainier";
|
||||
compatible = "amcc,rainier";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
serial2 = &UART2;
|
||||
serial3 = &UART3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440GRx";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-size = <8000>;
|
||||
d-cache-size = <8000>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; /* Filled in by zImage */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440grx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440grx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1e 4 1f 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-440grx","ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0e0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1c 4 1d 4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-440grx", "ibm,sdr-440ep";
|
||||
dcr-reg = <00e 002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-440grx", "ibm,cpr-440ep";
|
||||
dcr-reg = <00c 002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440grx", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali";
|
||||
dcr-reg = <010 2>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
compatible = "ibm,dma-440grx", "ibm,dma-4xx";
|
||||
dcr-reg = <100 027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440grx", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
num-tx-chans = <2>;
|
||||
num-rx-chans = <2>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440grx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <00000000 1 00000000 80000000
|
||||
80000000 1 80000000 80000000>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <7 4>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440grx", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
interrupts = <5 1>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl256n", "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0 000000 4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "Kernel";
|
||||
reg = <0 180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "ramdisk";
|
||||
reg = <180000 200000>;
|
||||
};
|
||||
partition@380000 {
|
||||
label = "file system";
|
||||
reg = <380000 3aa0000>;
|
||||
};
|
||||
partition@3e20000 {
|
||||
label = "kozio";
|
||||
reg = <3e20000 140000>;
|
||||
};
|
||||
partition@3f60000 {
|
||||
label = "env";
|
||||
reg = <3f60000 40000>;
|
||||
};
|
||||
partition@3fa0000 {
|
||||
label = "u-boot";
|
||||
reg = <3fa0000 60000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600300 8>;
|
||||
virtual-reg = <ef600300>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
current-speed = <1c200>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
};
|
||||
|
||||
UART1: serial@ef600400 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600400 8>;
|
||||
virtual-reg = <ef600400>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
};
|
||||
|
||||
UART2: serial@ef600500 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600500 8>;
|
||||
virtual-reg = <ef600500>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <3 4>;
|
||||
};
|
||||
|
||||
UART3: serial@ef600600 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <ef600600 8>;
|
||||
virtual-reg = <ef600600>;
|
||||
clock-frequency = <0>;
|
||||
current-speed = <0>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <4 4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
device_type = "i2c";
|
||||
compatible = "ibm,iic-440grx", "ibm,iic";
|
||||
reg = <ef600700 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
device_type = "i2c";
|
||||
compatible = "ibm,iic-440grx", "ibm,iic";
|
||||
reg = <ef600800 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <7 4>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@ef600d00 {
|
||||
device_type = "zmii-interface";
|
||||
compatible = "ibm,zmii-440grx", "ibm,zmii";
|
||||
reg = <ef600d00 c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601000 {
|
||||
device_type = "rgmii-interface";
|
||||
compatible = "ibm,rgmii-440grx", "ibm,rgmii";
|
||||
reg = <ef601000 8>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600e00 {
|
||||
linux,network-index = <0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 18 4
|
||||
/*Wake*/ 1 &UIC1 1d 4>;
|
||||
reg = <ef600e00 70>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
|
||||
EMAC1: ethernet@ef600f00 {
|
||||
linux,network-index = <1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
|
||||
interrupt-parent = <&EMAC1>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0 &UIC0 19 4
|
||||
/*Wake*/ 1 &UIC1 1f 4>;
|
||||
reg = <ef600f00 70>;
|
||||
local-mac-address = [000000000000];
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000000>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@1ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <1 eec00000 8 /* Config space access */
|
||||
1 eed00000 4 /* IACK */
|
||||
1 eed00000 4 /* Special cycle */
|
||||
1 ef400000 40>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <02000000 0 80000000 1 80000000 0 10000000
|
||||
01000000 0 00000000 1 e8000000 0 00100000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
/* All PCI interrupts are routed to IRQ 67 */
|
||||
interrupt-map-mask = <0000 0 0 0>;
|
||||
interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@ef600300";
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
};
|
||||
244
arch/powerpc/boot/dts/sbc8349.dts
Normal file
244
arch/powerpc/boot/dts/sbc8349.dts
Normal file
|
|
@ -0,0 +1,244 @@
|
|||
/*
|
||||
* SBC8349E Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Wind River Inc.
|
||||
*
|
||||
* Paul Gortmaker (see MAINTAINERS for contact information)
|
||||
*
|
||||
* -based largely on the Freescale MPC834x_MDS dts.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "SBC8349E";
|
||||
compatible = "SBC834xE";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8349@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>; // 256MB at 0
|
||||
};
|
||||
|
||||
soc8349@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
wdt@200 {
|
||||
compatible = "mpc83xx_wdt";
|
||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
spi@7000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,spi";
|
||||
reg = <0x7000 0x1000>;
|
||||
interrupts = <16 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
mode = "cpu";
|
||||
};
|
||||
|
||||
/* phy type (ULPI or SERIAL) are only types supported for MPH */
|
||||
/* port = 0 or 1 */
|
||||
usb@22000 {
|
||||
compatible = "fsl-usb2-mph";
|
||||
reg = <0x22000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <39 0x8>;
|
||||
phy_type = "ulpi";
|
||||
port1;
|
||||
};
|
||||
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
|
||||
usb@23000 {
|
||||
device_type = "usb";
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
dr_mode = "otg";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@19 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <20 0x8>;
|
||||
reg = <0x19>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@1a {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <21 0x8>;
|
||||
reg = <0x1a>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy0>;
|
||||
linux,network-index = <0>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = <&phy1>;
|
||||
linux,network-index = <1>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <0>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
/* May need to remove if on a part without crypto engine */
|
||||
crypto@30000 {
|
||||
model = "SEC2";
|
||||
compatible = "talitos";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <11 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
num-channels = <4>;
|
||||
channel-fifo-len = <24>;
|
||||
exec-units-mask = <0x0000007e>;
|
||||
/* desc mask is for rev2.0,
|
||||
* we need runtime fixup for >2.0 */
|
||||
descriptor-types-mask = <0x01010ebf>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: pic@700 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
cell-index = <1>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x11 */
|
||||
0x8800 0x0 0x0 0x1 &ipic 20 0x8
|
||||
0x8800 0x0 0x0 0x2 &ipic 21 0x8
|
||||
0x8800 0x0 0x0 0x3 &ipic 22 0x8
|
||||
0x8800 0x0 0x0 0x4 &ipic 23 0x8>;
|
||||
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <0x42 0x8>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100>;
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
244
arch/powerpc/boot/dts/sbc8548.dts
Normal file
244
arch/powerpc/boot/dts/sbc8548.dts
Normal file
|
|
@ -0,0 +1,244 @@
|
|||
/*
|
||||
* SBC8548 Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Wind River Systems Inc.
|
||||
*
|
||||
* Paul Gortmaker (see MAINTAINERS for contact information)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "SBC8548";
|
||||
compatible = "SBC8548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
/* pci1 doesn't have a corresponding physical connector */
|
||||
pci2 = &pci2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8548@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <0x20>; // 32 bytes
|
||||
i-cache-line-size = <0x20>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc8548@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x00000000 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00001000>; // CCSRBAR
|
||||
bus-frequency = <0>;
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,8548-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x12 0x2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
compatible = "fsl,8548-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <0x20>; // 32 bytes
|
||||
cache-size = <0x80000>; // L2, 512K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x10 0x2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy0: ethernet-phy@19 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x6 0x1>;
|
||||
reg = <0x19>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@1a {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x7 0x1>;
|
||||
reg = <0x1a>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
interrupts = <0x2a 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
interrupts = <0x2a 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
global-utilities@e0000 { //global utilities reg
|
||||
compatible = "fsl,mpc8548-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
compatible = "chrp,open-pic";
|
||||
device_type = "open-pic";
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x01 (PCI-X slot) */
|
||||
0x0800 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0800 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0800 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0800 0x0 0x0 0x4 &mpic 0x3 0x1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x18 0x2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008000 0x1000>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
||||
pci2: pcie@e000a000 {
|
||||
cell-index = <2>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x0 (PEX) */
|
||||
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
||||
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
||||
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
||||
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x1a 0x2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;
|
||||
clock-frequency = <33333333>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe000a000 0x1000>;
|
||||
compatible = "fsl,mpc8548-pcie";
|
||||
device_type = "pci";
|
||||
pcie@0 {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0x0 0xa0000000
|
||||
0x02000000 0x0 0xa0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
330
arch/powerpc/boot/dts/sbc8560.dts
Normal file
330
arch/powerpc/boot/dts/sbc8560.dts
Normal file
|
|
@ -0,0 +1,330 @@
|
|||
/*
|
||||
* SBC8560 Device Tree Source
|
||||
*
|
||||
* Copyright 2007 Wind River Systems Inc.
|
||||
*
|
||||
* Paul Gortmaker (see MAINTAINERS for contact information)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "SBC8560";
|
||||
compatible = "SBC8560";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8560@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <0x20>; // 32 bytes
|
||||
i-cache-line-size = <0x20>; // 32 bytes
|
||||
d-cache-size = <0x8000>; // L1, 32K
|
||||
i-cache-size = <0x8000>; // L1, 32K
|
||||
timebase-frequency = <0>; // From uboot
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
soc@ff700000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xff700000 0x00100000>;
|
||||
reg = <0xff700000 0x00100000>;
|
||||
clock-frequency = <0>;
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,8560-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x12 0x2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
compatible = "fsl,8560-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <0x20>; // 32 bytes
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x10 0x2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <0x2b 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
phy0: ethernet-phy@19 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x6 0x1>;
|
||||
reg = <0x19>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy1: ethernet-phy@1a {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x7 0x1>;
|
||||
reg = <0x1a>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@1b {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x8 0x1>;
|
||||
reg = <0x1b>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@1c {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x8 0x1>;
|
||||
reg = <0x1c>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
|
||||
reg = <0x919c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram@80000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x80000 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0x0 0x4000 0x9000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@919f0 {
|
||||
compatible = "fsl,mpc8560-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x919f0 0x10 0x915f0 0x10>;
|
||||
clock-frequency = <165000000>;
|
||||
};
|
||||
|
||||
cpmpic: pic@90c00 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x2e 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x90c00 0x80>;
|
||||
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
|
||||
enet2: ethernet@91320 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8560-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fsl,cpm-command = <0x16200300>;
|
||||
interrupts = <0x21 0x8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet3: ethernet@91340 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8560-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fsl,cpm-command = <0x1a400300>;
|
||||
interrupts = <0x22 0x8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
};
|
||||
|
||||
global-utilities@e0000 {
|
||||
compatible = "fsl,mpc8560-guts";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,has-rstcr;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@ff708000 {
|
||||
cell-index = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xff708000 0x1000>;
|
||||
clock-frequency = <66666666>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x02 */
|
||||
0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
|
||||
0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
|
||||
0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
|
||||
0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <0x18 0x2>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
};
|
||||
|
||||
localbus@ff705000 {
|
||||
compatible = "fsl,mpc8560-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xff705000 0x100>; // BRx, ORx, etc.
|
||||
|
||||
ranges = <
|
||||
0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
|
||||
0x1 0x0 0xe4000000 0x4000000 // 64MB flash
|
||||
0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
|
||||
0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
|
||||
0x5 0x0 0xfc000000 0x0c00000 // EPLD
|
||||
0x6 0x0 0xe0000000 0x4000000 // 64MB flash
|
||||
0x7 0x0 0x80000000 0x0200000 // ATM1,2
|
||||
>;
|
||||
|
||||
epld@5,0 {
|
||||
compatible = "wrs,epld-localbus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x5 0x0 0xc00000>;
|
||||
ranges = <
|
||||
0x0 0x0 0x5 0x000000 0x1fff // LED disp.
|
||||
0x1 0x0 0x5 0x100000 0x1fff // switches
|
||||
0x2 0x0 0x5 0x200000 0x1fff // ID reg.
|
||||
0x3 0x0 0x5 0x300000 0x1fff // status reg.
|
||||
0x4 0x0 0x5 0x400000 0x1fff // reset reg.
|
||||
0x5 0x0 0x5 0x500000 0x1fff // Wind port
|
||||
0x7 0x0 0x5 0x700000 0x1fff // UART #1
|
||||
0x8 0x0 0x5 0x800000 0x1fff // UART #2
|
||||
0x9 0x0 0x5 0x900000 0x1fff // RTC
|
||||
0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
|
||||
>;
|
||||
|
||||
bidr@2,0 {
|
||||
compatible = "wrs,sbc8560-bidr";
|
||||
reg = <0x2 0x0 0x10>;
|
||||
};
|
||||
|
||||
bcsr@3,0 {
|
||||
compatible = "wrs,sbc8560-bcsr";
|
||||
reg = <0x3 0x0 0x10>;
|
||||
};
|
||||
|
||||
brstcr@4,0 {
|
||||
compatible = "wrs,sbc8560-brstcr";
|
||||
reg = <0x4 0x0 0x10>;
|
||||
};
|
||||
|
||||
serial0: serial@7,0 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x7 0x0 0x100>;
|
||||
clock-frequency = <1843200>;
|
||||
interrupts = <0x9 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@8,0 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x8 0x0 0x100>;
|
||||
clock-frequency = <1843200>;
|
||||
interrupts = <0xa 0x2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
rtc@9,0 {
|
||||
compatible = "m48t59";
|
||||
reg = <0x9 0x0 0x1fff>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -17,14 +17,24 @@ / {
|
|||
#size-cells = <1>;
|
||||
model = "amcc,sequoia";
|
||||
compatible = "amcc,sequoia";
|
||||
dcr-parent = <&/cpus/PowerPC,440EPx@0>;
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
ethernet1 = &EMAC1;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
serial2 = &UART2;
|
||||
serial3 = &UART3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,440EPx@0 {
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440EPx";
|
||||
reg = <0>;
|
||||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
|
|
@ -94,7 +104,6 @@ plb {
|
|||
clock-frequency = <0>; /* Filled in by zImage */
|
||||
|
||||
SDRAM0: sdram {
|
||||
device_type = "memory-controller";
|
||||
compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
|
||||
dcr-reg = <010 2>;
|
||||
};
|
||||
|
|
@ -122,6 +131,13 @@ MAL0: mcmal {
|
|||
interrupt-map-mask = <ffffffff>;
|
||||
};
|
||||
|
||||
USB1: usb@e0000400 {
|
||||
compatible = "ohci-be";
|
||||
reg = <0 e0000400 60>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <15 8>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440epx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -308,6 +324,33 @@ EMAC1: ethernet@ef600f00 {
|
|||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@1ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <1 eec00000 8 /* Config space access */
|
||||
1 eed00000 4 /* IACK */
|
||||
1 eed00000 4 /* Special cycle */
|
||||
1 ef400000 40>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <02000000 0 80000000 1 80000000 0 10000000
|
||||
01000000 0 00000000 1 e8000000 0 00100000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
/* All PCI interrupts are routed to IRQ 67 */
|
||||
interrupt-map-mask = <0000 0 0 0>;
|
||||
interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
|
|||
141
arch/powerpc/boot/dts/storcenter.dts
Normal file
141
arch/powerpc/boot/dts/storcenter.dts
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Device Tree Source for IOMEGA StorCenter
|
||||
*
|
||||
* Copyright 2007 Oyvind Repvik
|
||||
* Copyright 2007 Jon Loeliger
|
||||
*
|
||||
* Based on the Kurobox DTS by G. Liakhovetski <g.liakhovetski@gmx.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "StorCenter";
|
||||
compatible = "storcenter";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8241@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
timebase-frequency = <25000000>;
|
||||
bus-frequency = <0>; /* from bootwrapper */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <16384>;
|
||||
d-cache-size = <16384>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
|
||||
};
|
||||
|
||||
soc@fc000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8241", "mpc10x";
|
||||
store-gathering = <0>; /* 0 == off, !0 == on */
|
||||
ranges = <0x0 0xfc000000 0x100000>;
|
||||
reg = <0xfc000000 0x100000>; /* EUMB */
|
||||
bus-frequency = <0>; /* fixed by loader */
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <5 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <68>;
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x20>;
|
||||
clock-frequency = <97553800>; /* Hz */
|
||||
current-speed = <115200>;
|
||||
interrupts = <9 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x20>;
|
||||
clock-frequency = <97553800>; /* Hz */
|
||||
current-speed = <9600>;
|
||||
interrupts = <10 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@40000 {
|
||||
#interrupt-cells = <2>;
|
||||
device_type = "open-pic";
|
||||
compatible = "chrp,open-pic";
|
||||
interrupt-controller;
|
||||
reg = <0x40000 0x40000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci0: pci@fe800000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "mpc10x-pci";
|
||||
reg = <0xfe800000 0x1000>;
|
||||
ranges = <0x01000000 0x0 0x0 0xfe000000 0x0 0x00c00000
|
||||
0x02000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
|
||||
bus-range = <0 0xff>;
|
||||
clock-frequency = <97553800>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 13 - IDE */
|
||||
0x6800 0 0 1 &mpic 0 1
|
||||
0x6800 0 0 2 &mpic 0 1
|
||||
0x6800 0 0 3 &mpic 0 1
|
||||
0x6800 0 0 4 &mpic 0 1
|
||||
/* IDSEL 14 - USB */
|
||||
0x7000 0 0 1 &mpic 0 1
|
||||
0x7000 0 0 2 &mpic 0 1
|
||||
0x7000 0 0 3 &mpic 0 1
|
||||
0x7000 0 0 4 &mpic 0 1
|
||||
/* IDSEL 15 - ETH */
|
||||
0x7800 0 0 1 &mpic 0 1
|
||||
0x7800 0 0 2 &mpic 0 1
|
||||
0x7800 0 0 3 &mpic 0 1
|
||||
0x7800 0 0 4 &mpic 0 1
|
||||
>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/soc/serial@4500";
|
||||
};
|
||||
};
|
||||
228
arch/powerpc/boot/dts/stx_gp3_8560.dts
Normal file
228
arch/powerpc/boot/dts/stx_gp3_8560.dts
Normal file
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
* STX GP3 - 8560 ADS Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "stx,gp3";
|
||||
compatible = "stx,gp3-8560", "stx,gp3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8560@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc@fdf00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0 0xfdf00000 0x100000>;
|
||||
reg = <0xfdf00000 0x1000>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8560-immr", "simple-bus";
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,8540-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 4>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy4: ethernet-phy@4 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <5 4>;
|
||||
reg = <4>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy4>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
|
||||
reg = <0x919c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram@80000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x80000 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x4000 0x9000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@919f0 {
|
||||
compatible = "fsl,mpc8560-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x919f0 0x10 0x915f0 0x10>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cpmpic: pic@90c00 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <46 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x90c00 0x80>;
|
||||
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
|
||||
serial0: serial@91a20 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8560-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <0x91a20 0x20 0x88100 0x100>;
|
||||
fsl,cpm-brg = <2>;
|
||||
fsl,cpm-command = <0x4a00000>;
|
||||
interrupts = <41 8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@fdf08000 {
|
||||
cell-index = <0>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
|
||||
/* IDSEL 0x0c */
|
||||
0x6000 0 0 1 &mpic 1 1
|
||||
0x6000 0 0 2 &mpic 2 1
|
||||
0x6000 0 0 3 &mpic 3 1
|
||||
0x6000 0 0 4 &mpic 4 1
|
||||
|
||||
/* IDSEL 0x0d */
|
||||
0x6800 0 0 1 &mpic 4 1
|
||||
0x6800 0 0 2 &mpic 1 1
|
||||
0x6800 0 0 3 &mpic 2 1
|
||||
0x6800 0 0 4 &mpic 3 1
|
||||
|
||||
/* IDSEL 0x0e */
|
||||
0x7000 0 0 1 &mpic 3 1
|
||||
0x7000 0 0 2 &mpic 4 1
|
||||
0x7000 0 0 3 &mpic 1 1
|
||||
0x7000 0 0 4 &mpic 2 1
|
||||
|
||||
/* IDSEL 0x0f */
|
||||
0x7800 0 0 1 &mpic 2 1
|
||||
0x7800 0 0 2 &mpic 3 1
|
||||
0x7800 0 0 3 &mpic 4 1
|
||||
0x7800 0 0 4 &mpic 1 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xfdf08000 0x1000>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
};
|
||||
383
arch/powerpc/boot/dts/taishan.dts
Normal file
383
arch/powerpc/boot/dts/taishan.dts
Normal file
|
|
@ -0,0 +1,383 @@
|
|||
/*
|
||||
* Device Tree Source for IBM/AMCC Taishan
|
||||
*
|
||||
* Copyright 2007 IBM Corp.
|
||||
* Hugh Blemings <hugh@au.ibm.com> based off code by
|
||||
* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "amcc,taishan";
|
||||
compatible = "amcc,taishan";
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC2;
|
||||
ethernet1 = &EMAC3;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,440GX";
|
||||
reg = <0>;
|
||||
clock-frequency = <2FAF0800>; // 800MHz
|
||||
timebase-frequency = <0>; // Filled in by zImage
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <8000>; /* 32 kB */
|
||||
d-cache-size = <8000>; /* 32 kB */
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0>; // Filled in by zImage
|
||||
};
|
||||
|
||||
|
||||
UICB0: interrupt-controller-base {
|
||||
compatible = "ibm,uic-440gx", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <200 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic-440gx", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0c0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <01 4 00 4>; /* cascade - first non-critical */
|
||||
interrupt-parent = <&UICB0>;
|
||||
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic-440gx", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0d0 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <03 4 02 4>; /* cascade */
|
||||
interrupt-parent = <&UICB0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic-440gx", "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>; /* was 1 */
|
||||
dcr-reg = <210 009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <05 4 04 4>; /* cascade */
|
||||
interrupt-parent = <&UICB0>;
|
||||
};
|
||||
|
||||
|
||||
CPC0: cpc {
|
||||
compatible = "ibm,cpc-440gp";
|
||||
dcr-reg = <0b0 003 0e0 010>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440gx", "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <9896800>; // 160MHz
|
||||
|
||||
SDRAM0: memory-controller {
|
||||
compatible = "ibm,sdram-440gp";
|
||||
dcr-reg = <010 2>;
|
||||
// FIXME: anything else?
|
||||
};
|
||||
|
||||
SRAM0: sram {
|
||||
compatible = "ibm,sram-440gp";
|
||||
dcr-reg = <020 8 00a 1>;
|
||||
};
|
||||
|
||||
DMA0: dma {
|
||||
// FIXME: ???
|
||||
compatible = "ibm,dma-440gp";
|
||||
dcr-reg = <100 027>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal-440gx", "ibm,mcmal2";
|
||||
dcr-reg = <180 62>;
|
||||
num-tx-chans = <4>;
|
||||
num-rx-chans = <4>;
|
||||
interrupt-parent = <&MAL0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
|
||||
/*RXEOB*/ 1 &UIC0 b 4
|
||||
/*SERR*/ 2 &UIC1 0 4
|
||||
/*TXDE*/ 3 &UIC1 1 4
|
||||
/*RXDE*/ 4 &UIC1 2 4>;
|
||||
interrupt-map-mask = <ffffffff>;
|
||||
};
|
||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb-440gx", "ibm,opb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* Wish there was a nicer way of specifying a full 32-bit
|
||||
range */
|
||||
ranges = <00000000 1 00000000 80000000
|
||||
80000000 1 80000000 80000000>;
|
||||
dcr-reg = <090 00b>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <7 4>;
|
||||
clock-frequency = <4C4B400>; // 80MHz
|
||||
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc-440gx", "ibm,ebc";
|
||||
dcr-reg = <012 2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
clock-frequency = <4C4B400>; // 80MHz
|
||||
|
||||
/* ranges property is supplied by zImage
|
||||
* based on firmware's configuration of the
|
||||
* EBC bridge */
|
||||
|
||||
interrupts = <5 4>;
|
||||
interrupt-parent = <&UIC1>;
|
||||
|
||||
/* TODO: Add other EBC devices */
|
||||
};
|
||||
|
||||
|
||||
|
||||
UART0: serial@40000200 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <40000200 8>;
|
||||
virtual-reg = <e0000200>;
|
||||
clock-frequency = <A8C000>;
|
||||
current-speed = <1C200>; /* 115200 */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0 4>;
|
||||
};
|
||||
|
||||
UART1: serial@40000300 {
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <40000300 8>;
|
||||
virtual-reg = <e0000300>;
|
||||
clock-frequency = <A8C000>;
|
||||
current-speed = <1C200>; /* 115200 */
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <1 4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@40000400 {
|
||||
/* FIXME */
|
||||
device_type = "i2c";
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <40000400 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <2 4>;
|
||||
};
|
||||
IIC1: i2c@40000500 {
|
||||
/* FIXME */
|
||||
device_type = "i2c";
|
||||
compatible = "ibm,iic-440gp", "ibm,iic";
|
||||
reg = <40000500 14>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <3 4>;
|
||||
};
|
||||
|
||||
GPIO0: gpio@40000700 {
|
||||
/* FIXME */
|
||||
compatible = "ibm,gpio-440gp";
|
||||
reg = <40000700 20>;
|
||||
};
|
||||
|
||||
ZMII0: emac-zmii@40000780 {
|
||||
device_type = "zgmii-interface";
|
||||
compatible = "ibm,zmii-440gx", "ibm,zmii";
|
||||
reg = <40000780 c>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@40000790 {
|
||||
device_type = "rgmii-interface";
|
||||
compatible = "ibm,rgmii";
|
||||
reg = <40000790 8>;
|
||||
};
|
||||
|
||||
|
||||
EMAC0: ethernet@40000800 {
|
||||
unused = <1>;
|
||||
linux,network-index = <2>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gx", "ibm,emac4";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1c 4 1d 4>;
|
||||
reg = <40000800 70>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <0>;
|
||||
};
|
||||
EMAC1: ethernet@40000900 {
|
||||
unused = <1>;
|
||||
linux,network-index = <3>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gx", "ibm,emac4";
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <1e 4 1f 4>;
|
||||
reg = <40000900 70>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <1>;
|
||||
mal-rx-channel = <1>;
|
||||
cell-index = <1>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rmii";
|
||||
phy-map = <00000001>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <1>;
|
||||
};
|
||||
|
||||
EMAC2: ethernet@40000c00 {
|
||||
linux,network-index = <0>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gx", "ibm,emac4";
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <0 4 1 4>;
|
||||
reg = <40000c00 70>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <2>;
|
||||
mal-rx-channel = <2>;
|
||||
cell-index = <2>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000001>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <2>;
|
||||
};
|
||||
|
||||
EMAC3: ethernet@40000e00 {
|
||||
linux,network-index = <1>;
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac-440gx", "ibm,emac4";
|
||||
interrupt-parent = <&UIC2>;
|
||||
interrupts = <2 4 3 4>;
|
||||
reg = <40000e00 70>;
|
||||
local-mac-address = [000000000000]; // Filled in by zImage
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <3>;
|
||||
mal-rx-channel = <3>;
|
||||
cell-index = <3>;
|
||||
max-frame-size = <5dc>;
|
||||
rx-fifo-size = <1000>;
|
||||
tx-fifo-size = <800>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <00000003>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <1>;
|
||||
zmii-device = <&ZMII0>;
|
||||
zmii-channel = <3>;
|
||||
};
|
||||
|
||||
|
||||
GPT0: gpt@40000a00 {
|
||||
/* FIXME */
|
||||
reg = <40000a00 d4>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <12 4 13 4 14 4 15 4 16 4>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
PCIX0: pci@20ec00000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
|
||||
primary;
|
||||
large-inbound-windows;
|
||||
enable-msi-hole;
|
||||
reg = <2 0ec00000 8 /* Config space access */
|
||||
0 0 0 /* no IACK cycles */
|
||||
2 0ed00000 4 /* Special cycles */
|
||||
2 0ec80000 100 /* Internal registers */
|
||||
2 0ec80100 fc>; /* Internal messaging registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed
|
||||
*/
|
||||
ranges = <02000000 0 80000000 00000003 80000000 0 80000000
|
||||
01000000 0 00000000 00000002 08000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 0 80000000>;
|
||||
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 1 &UIC0 17 8
|
||||
0800 0 0 2 &UIC0 18 8
|
||||
0800 0 0 3 &UIC0 19 8
|
||||
0800 0 0 4 &UIC0 1a 8
|
||||
|
||||
/* IDSEL 2 */
|
||||
1000 0 0 1 &UIC0 18 8
|
||||
1000 0 0 2 &UIC0 19 8
|
||||
1000 0 0 3 &UIC0 1a 8
|
||||
1000 0 0 4 &UIC0 17 8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = "/plb/opb/serial@40000300";
|
||||
};
|
||||
};
|
||||
177
arch/powerpc/boot/dts/tqm5200.dts
Normal file
177
arch/powerpc/boot/dts/tqm5200.dts
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
/*
|
||||
* TQM5200 board Device Tree Source
|
||||
*
|
||||
* Copyright (C) 2007 Semihalf
|
||||
* Marian Balakowicz <m8@semihalf.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "tqc,tqm5200";
|
||||
compatible = "tqc,tqm5200";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <20>;
|
||||
i-cache-line-size = <20>;
|
||||
d-cache-size = <4000>; // L1, 16K
|
||||
i-cache-size = <4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <00000000 04000000>; // 64MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200-immr";
|
||||
ranges = <0 f0000000 0000c000>;
|
||||
reg = <f0000000 00000100>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200-cdm";
|
||||
reg = <200 38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "fsl,mpc5200-pic";
|
||||
reg = <500 80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
reg = <600 10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <b00 40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <1000 ff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
compatible = "fsl,mpc5200-bestcomm";
|
||||
reg = <1200 80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 a 0 3 b 0
|
||||
3 c 0 3 d 0 3 e 0 3 f 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200-xlb";
|
||||
reg = <1f00 100>;
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
reg = <2000 100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
serial@2200 { // PSC2
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <1>; // Logical port assignment
|
||||
reg = <2200 100>;
|
||||
interrupts = <2 2 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
serial@2400 { // PSC3
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <2>; // Logical port assignment
|
||||
reg = <2400 100>;
|
||||
interrupts = <2 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200-fec";
|
||||
reg = <3000 800>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
compatible = "fsl,mpc5200-ata";
|
||||
reg = <3a00 100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <3d40 40>;
|
||||
interrupts = <2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200-sram";
|
||||
reg = <8000 4000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200-pci";
|
||||
reg = <f0000d00 100>;
|
||||
interrupt-map-mask = <f800 0 0 7>;
|
||||
interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
|
||||
c000 0 0 2 &mpc5200_pic 0 0 3
|
||||
c000 0 0 3 &mpc5200_pic 0 0 3
|
||||
c000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 a 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <42000000 0 80000000 80000000 0 10000000
|
||||
02000000 0 90000000 90000000 0 10000000
|
||||
01000000 0 00000000 a0000000 0 01000000>;
|
||||
};
|
||||
};
|
||||
204
arch/powerpc/boot/dts/tqm8540.dts
Normal file
204
arch/powerpc/boot/dts/tqm8540.dts
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
/*
|
||||
* TQM 8540 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqm,8540";
|
||||
compatible = "tqm,8540", "tqm,85xx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8540@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x100000>;
|
||||
reg = <0xe0000000 0x200>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8540-immr", "simple-bus";
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,8540-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
cell-index = <2>;
|
||||
device_type = "network";
|
||||
model = "FEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x26000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <41 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xe0008000 0x1000>;
|
||||
clock-frequency = <66666666>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 28 */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
228
arch/powerpc/boot/dts/tqm8541.dts
Normal file
228
arch/powerpc/boot/dts/tqm8541.dts
Normal file
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
* TQM 8541 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqm,8541";
|
||||
compatible = "tqm,8541", "tqm,85xx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8541@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x100000>;
|
||||
reg = <0xe0000000 0x200>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8541-immr", "simple-bus";
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,8540-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus";
|
||||
reg = <0x919c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram@80000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x80000 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x2000 0x9000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@919f0 {
|
||||
compatible = "fsl,mpc8541-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x919f0 0x10 0x915f0 0x10>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cpmpic: pic@90c00 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <46 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x90c00 0x80>;
|
||||
compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xe0008000 0x1000>;
|
||||
clock-frequency = <66666666>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 28 */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
228
arch/powerpc/boot/dts/tqm8555.dts
Normal file
228
arch/powerpc/boot/dts/tqm8555.dts
Normal file
|
|
@ -0,0 +1,228 @@
|
|||
/*
|
||||
* TQM 8555 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqm,8555";
|
||||
compatible = "tqm,8555", "tqm,85xx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8555@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x100000>;
|
||||
reg = <0xe0000000 0x200>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8555-immr", "simple-bus";
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,8540-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>; // reg base, size
|
||||
clock-frequency = <0>; // should we fill in in uboot?
|
||||
interrupts = <42 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus";
|
||||
reg = <0x919c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram@80000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x80000 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x2000 0x9000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@919f0 {
|
||||
compatible = "fsl,mpc8555-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x919f0 0x10 0x915f0 0x10>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cpmpic: pic@90c00 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <46 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x90c00 0x80>;
|
||||
compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xe0008000 0x1000>;
|
||||
clock-frequency = <66666666>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 28 */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
245
arch/powerpc/boot/dts/tqm8560.dts
Normal file
245
arch/powerpc/boot/dts/tqm8560.dts
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
/*
|
||||
* TQM 8560 Device Tree Source
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "tqm,8560";
|
||||
compatible = "tqm,8560", "tqm,85xx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8560@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
soc@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
ranges = <0x0 0xe0000000 0x100000>;
|
||||
reg = <0xe0000000 0x200>;
|
||||
bus-frequency = <0>;
|
||||
compatible = "fsl,mpc8560-immr", "simple-bus";
|
||||
|
||||
memory-controller@2000 {
|
||||
compatible = "fsl,8540-memory-controller";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <18 2>;
|
||||
};
|
||||
|
||||
l2-cache-controller@20000 {
|
||||
compatible = "fsl,8540-l2-cache-controller";
|
||||
reg = <0x20000 0x1000>;
|
||||
cache-line-size = <32>;
|
||||
cache-size = <0x40000>; // L2, 256K
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <16 2>;
|
||||
};
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <43 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
dfsrr;
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@24520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x24520 0x20>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <8 1>;
|
||||
reg = <3>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <29 2 30 2 34 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy2>;
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "TSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 2 36 2 40 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
mpic: pic@40000 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x40000>;
|
||||
device_type = "open-pic";
|
||||
};
|
||||
|
||||
cpm@919c0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
|
||||
reg = <0x919c0 0x30>;
|
||||
ranges;
|
||||
|
||||
muram@80000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x80000 0x10000>;
|
||||
|
||||
data@0 {
|
||||
compatible = "fsl,cpm-muram-data";
|
||||
reg = <0 0x4000 0x9000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
brg@919f0 {
|
||||
compatible = "fsl,mpc8560-brg",
|
||||
"fsl,cpm2-brg",
|
||||
"fsl,cpm-brg";
|
||||
reg = <0x919f0 0x10 0x915f0 0x10>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cpmpic: pic@90c00 {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <46 2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
reg = <0x90c00 0x80>;
|
||||
compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
|
||||
};
|
||||
|
||||
serial0: serial@91a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8560-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <0x91a00 0x20 0x88000 0x100>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <0x800000>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <40 8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
};
|
||||
|
||||
serial1: serial@91a20 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8560-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <0x91a20 0x20 0x88100 0x100>;
|
||||
fsl,cpm-brg = <2>;
|
||||
fsl,cpm-command = <0x4a00000>;
|
||||
current-speed = <115200>;
|
||||
interrupts = <41 8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
};
|
||||
|
||||
enet2: ethernet@91340 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc8560-fcc-enet",
|
||||
"fsl,cpm2-fcc-enet";
|
||||
reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
fsl,cpm-command = <0x1a400300>;
|
||||
interrupts = <34 8>;
|
||||
interrupt-parent = <&cpmpic>;
|
||||
phy-handle = <&phy3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008000 {
|
||||
cell-index = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
|
||||
device_type = "pci";
|
||||
reg = <0xe0008000 0x1000>;
|
||||
clock-frequency = <66666666>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 28 */
|
||||
0xe000 0 0 1 &mpic 2 1
|
||||
0xe000 0 0 2 &mpic 3 1>;
|
||||
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <24 2>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -14,14 +14,21 @@ / {
|
|||
#size-cells = <1>;
|
||||
model = "ibm,walnut";
|
||||
compatible = "ibm,walnut";
|
||||
dcr-parent = <&/cpus/PowerPC,405GP@0>;
|
||||
dcr-parent = <&/cpus/cpu@0>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,405GP@0 {
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,405GP";
|
||||
reg = <0>;
|
||||
clock-frequency = <bebc200>; /* Filled in by zImage */
|
||||
timebase-frequency = <0>; /* Filled in by zImage */
|
||||
|
|
@ -168,9 +175,10 @@ partition@0 {
|
|||
};
|
||||
};
|
||||
|
||||
ds1743@1,0 {
|
||||
nvram@1,0 {
|
||||
/* NVRAM and RTC */
|
||||
compatible = "ds1743";
|
||||
compatible = "ds1743-nvram";
|
||||
#bytes = <2000>;
|
||||
reg = <1 0 2000>;
|
||||
};
|
||||
|
||||
|
|
@ -190,6 +198,45 @@ fpga@7,0 {
|
|||
virtual-reg = <f0300005>;
|
||||
};
|
||||
};
|
||||
|
||||
PCI0: pci@ec000000 {
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
|
||||
primary;
|
||||
reg = <eec00000 8 /* Config space access */
|
||||
eed80000 4 /* IACK */
|
||||
eed80000 4 /* Special cycle */
|
||||
ef480000 40>; /* Internal registers */
|
||||
|
||||
/* Outbound ranges, one memory and one IO,
|
||||
* later cannot be changed. Chip supports a second
|
||||
* IO range but we don't use it for now
|
||||
*/
|
||||
ranges = <02000000 0 80000000 80000000 0 20000000
|
||||
01000000 0 00000000 e8000000 0 00010000>;
|
||||
|
||||
/* Inbound 2GB range starting at 0 */
|
||||
dma-ranges = <42000000 0 0 0 0 80000000>;
|
||||
|
||||
/* Walnut has all 4 IRQ pins tied together per slot */
|
||||
interrupt-map-mask = <f800 0 0 0>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 1 */
|
||||
0800 0 0 0 &UIC0 1c 8
|
||||
|
||||
/* IDSEL 2 */
|
||||
1000 0 0 0 &UIC0 1d 8
|
||||
|
||||
/* IDSEL 3 */
|
||||
1800 0 0 0 &UIC0 1e 8
|
||||
|
||||
/* IDSEL 4 */
|
||||
2000 0 0 0 &UIC0 1f 8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue