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mmc: sh_mmcif: simplify IRQ processing
The classical way to process IRQs is read out the status, ack all triggered IRQs, possibly mask them, then process them. Follow this simple procesure instead of the current complex custom algorithm. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
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parent
e475b2702f
commit
8af5075088
1 changed files with 19 additions and 46 deletions
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@ -129,6 +129,10 @@
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INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
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INT_RDATTO | INT_RBSYTO | INT_RSPTO)
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#define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \
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INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
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INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
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/* CE_INT_MASK */
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#define MASK_ALL 0x00000000
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#define MASK_MCCSDE (1 << 29)
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@ -160,6 +164,11 @@
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MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
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MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
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#define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \
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MASK_MBUFREN | MASK_MBUFWEN | \
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MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \
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MASK_MCMD12RBE | MASK_MCMD12CRE)
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/* CE_HOST_STS1 */
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#define STS1_CMDSEQ (1 << 31)
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@ -1233,58 +1242,22 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
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{
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struct sh_mmcif_host *host = dev_id;
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u32 state;
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int err = 0;
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state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
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if (state & INT_ERR_STS) {
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/* error interrupts - process first */
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
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err = 1;
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} else if (state & INT_RBSYE) {
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sh_mmcif_writel(host->addr, MMCIF_CE_INT,
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~(INT_RBSYE | INT_CRSPE));
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
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} else if (state & INT_CRSPE) {
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
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} else if (state & INT_BUFREN) {
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
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} else if (state & INT_BUFWEN) {
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sh_mmcif_writel(host->addr, MMCIF_CE_INT,
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~(INT_BUFWEN | INT_DTRANE | INT_CMD12DRE |
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INT_CMD12RBE | INT_CMD12CRE));
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
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} else if (state & INT_CMD12DRE) {
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sh_mmcif_writel(host->addr, MMCIF_CE_INT,
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~(INT_CMD12DRE | INT_CMD12RBE |
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INT_CMD12CRE | INT_BUFRE));
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
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} else if (state & INT_BUFRE) {
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
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} else if (state & INT_DTRANE) {
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sh_mmcif_writel(host->addr, MMCIF_CE_INT,
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~(INT_CMD12DRE | INT_CMD12RBE |
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INT_CMD12CRE | INT_DTRANE));
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
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} else if (state & INT_CMD12RBE) {
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sh_mmcif_writel(host->addr, MMCIF_CE_INT,
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~(INT_CMD12RBE | INT_CMD12CRE));
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
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} else {
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dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
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sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
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sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
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err = 1;
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}
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if (err) {
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if (state & ~MASK_CLEAN)
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dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n",
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state);
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if (state & INT_ERR_STS || state & ~INT_ALL) {
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host->sd_error = true;
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dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
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dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state);
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}
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if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
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if (!host->mrq)
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dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state);
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if (!host->dma_active)
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return IRQ_WAKE_THREAD;
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else if (host->sd_error)
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