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drm/msm/dsi: add support for DSI-PHY on SM8550
SM8550 use a 4nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 4nm variant inside the common 5+7nm driver. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/517515/ Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-mdss-dsi-v3-6-660c3bcb127f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
parent
93f0ca6fd6
commit
8b034e6771
4 changed files with 79 additions and 16 deletions
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@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
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Choose this option if DSI PHY on SDM845 is used on the platform.
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config DRM_MSM_DSI_7NM_PHY
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bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
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bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
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depends on DRM_MSM_DSI
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default y
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help
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Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
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Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
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is used on the platform.
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config DRM_MSM_HDMI
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@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
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.data = &dsi_phy_5nm_8350_cfgs },
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{ .compatible = "qcom,sm8450-dsi-phy-5nm",
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.data = &dsi_phy_5nm_8450_cfgs },
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{ .compatible = "qcom,sm8550-dsi-phy-4nm",
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.data = &dsi_phy_4nm_8550_cfgs },
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#endif
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{}
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};
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@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
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struct msm_dsi_dphy_timing {
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u32 clk_zero;
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@ -47,6 +47,8 @@
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#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
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/* Hardware is V4.3 */
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#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
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/* Hardware is V5.2 */
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#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
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struct dsi_pll_config {
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bool enable_ssc;
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@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
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if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
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config->pll_clock_inverters = 0x28;
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else if (pll_freq <= 1000000000ULL)
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config->pll_clock_inverters = 0xa0;
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else if (pll_freq <= 2500000000ULL)
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config->pll_clock_inverters = 0x20;
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else if (pll_freq <= 3020000000ULL)
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config->pll_clock_inverters = 0x00;
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else
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config->pll_clock_inverters = 0x40;
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else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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if (pll_freq <= 1300000000ULL)
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config->pll_clock_inverters = 0xa0;
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else if (pll_freq <= 2500000000ULL)
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config->pll_clock_inverters = 0x20;
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else if (pll_freq <= 4000000000ULL)
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config->pll_clock_inverters = 0x00;
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else
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config->pll_clock_inverters = 0x40;
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} else {
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if (pll_freq <= 1000000000ULL)
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config->pll_clock_inverters = 0xa0;
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else if (pll_freq <= 2500000000ULL)
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config->pll_clock_inverters = 0x20;
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else if (pll_freq <= 3020000000ULL)
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config->pll_clock_inverters = 0x00;
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else
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config->pll_clock_inverters = 0x40;
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}
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config->decimal_div_start = dec;
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config->frac_div_start = frac;
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@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
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vco_config_1 = 0x01;
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}
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if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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if (pll->vco_current_rate < 1557000000ULL)
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vco_config_1 = 0x08;
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else
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vco_config_1 = 0x01;
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}
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dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
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analog_controls_five_1);
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dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
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@ -860,7 +880,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
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pr_warn("PLL turned on before configuring PHY\n");
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/* Request for REFGEN READY */
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if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
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udelay(500);
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}
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@ -894,7 +915,19 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
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lane_ctrl0 = 0x1f;
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}
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if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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if (phy->cphy_mode) {
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vreg_ctrl_0 = 0x45;
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vreg_ctrl_1 = 0x45;
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glbl_rescode_top_ctrl = 0x00;
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glbl_rescode_bot_ctrl = 0x00;
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} else {
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vreg_ctrl_0 = 0x44;
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vreg_ctrl_1 = 0x19;
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glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03;
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glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c;
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}
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} else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
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if (phy->cphy_mode) {
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glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01;
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glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b;
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@ -943,9 +976,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
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dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
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/* program CMN_CTRL_4 for minor_ver 2 chipsets*/
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data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
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data = data & (0xf0);
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if (data == 0x20)
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
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(dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
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dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
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/* Configure PHY lane swap (TODO: we need to calculate this) */
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@ -1058,7 +1090,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
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dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
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/* Turn off REFGEN Vote */
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if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
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wmb();
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/* Delay to ensure HW removes vote before PHY shut down */
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@ -1092,6 +1125,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
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{ .supply = "vdds", .init_load_uA = 97800 },
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};
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static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = {
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{ .supply = "vdds", .init_load_uA = 98400 },
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};
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const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
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.has_phy_lane = true,
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.regulator_data = dsi_phy_7nm_36mA_regulators,
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@ -1201,3 +1238,26 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
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.num_dsi_phy = 2,
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.quirks = DSI_PHY_7NM_QUIRK_V4_3,
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};
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const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
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.has_phy_lane = true,
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.regulator_data = dsi_phy_7nm_98400uA_regulators,
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.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators),
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.ops = {
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.enable = dsi_7nm_phy_enable,
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.disable = dsi_7nm_phy_disable,
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.pll_init = dsi_pll_7nm_init,
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.save_pll_state = dsi_7nm_pll_save_state,
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.restore_pll_state = dsi_7nm_pll_restore_state,
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.set_continuous_clock = dsi_7nm_set_continuous_clock,
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},
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.min_pll_rate = 600000000UL,
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#ifdef CONFIG_64BIT
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.max_pll_rate = 5000000000UL,
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#else
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.max_pll_rate = ULONG_MAX,
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#endif
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.io_start = { 0xae95000, 0xae97000 },
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.num_dsi_phy = 2,
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.quirks = DSI_PHY_7NM_QUIRK_V5_2,
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};
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