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Merge branch 'linux-4.12' of git://github.com/skeggsb/linux into drm-next
Some nouveau regression fixes. * 'linux-4.12' of git://github.com/skeggsb/linux: drm/nouveau/fb/gf100-: Fix 32 bit wraparound in new ram detection drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr() drm/nouveau/kms: Increase max retries in scanout position queries. drm/nouveau/bios/bitP: check that table is long enough for optional pointers drm/nouveau/fifo/nv40: no ctxsw for pre-nv44 mpeg engine
This commit is contained in:
commit
8b03d1ed2c
9 changed files with 10 additions and 8 deletions
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@ -111,7 +111,7 @@ nouveau_display_scanoutpos_head(struct drm_crtc *crtc, int *vpos, int *hpos,
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};
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};
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struct nouveau_display *disp = nouveau_display(crtc->dev);
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struct nouveau_display *disp = nouveau_display(crtc->dev);
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struct drm_vblank_crtc *vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
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struct drm_vblank_crtc *vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
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int ret, retry = 1;
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int ret, retry = 20;
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do {
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do {
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ret = nvif_mthd(&disp->disp, 0, &args, sizeof(args));
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ret = nvif_mthd(&disp->disp, 0, &args, sizeof(args));
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@ -44,6 +44,8 @@ nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx)
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*ctx = 0x38;
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*ctx = 0x38;
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return true;
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return true;
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case NVKM_ENGINE_MPEG:
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case NVKM_ENGINE_MPEG:
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if (engine->subdev.device->chipset < 0x44)
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return false;
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*reg = 0x00330c;
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*reg = 0x00330c;
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*ctx = 0x54;
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*ctx = 0x54;
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return true;
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return true;
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@ -33,7 +33,7 @@ nvbios_boostTe(struct nvkm_bios *bios,
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u32 boost = 0;
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u32 boost = 0;
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (bit_P.version == 2)
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if (bit_P.version == 2 && bit_P.length >= 0x34)
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boost = nvbios_rd32(bios, bit_P.offset + 0x30);
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boost = nvbios_rd32(bios, bit_P.offset + 0x30);
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if (boost) {
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if (boost) {
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@ -33,7 +33,7 @@ nvbios_cstepTe(struct nvkm_bios *bios,
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u32 cstep = 0;
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u32 cstep = 0;
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (bit_P.version == 2)
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if (bit_P.version == 2 && bit_P.length >= 0x38)
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cstep = nvbios_rd32(bios, bit_P.offset + 0x34);
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cstep = nvbios_rd32(bios, bit_P.offset + 0x34);
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if (cstep) {
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if (cstep) {
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@ -32,7 +32,7 @@ nvbios_fan_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
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u32 fan = 0;
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u32 fan = 0;
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (bit_P.version == 2 && bit_P.length >= 0x5a)
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if (bit_P.version == 2 && bit_P.length >= 0x5c)
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fan = nvbios_rd32(bios, bit_P.offset + 0x58);
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fan = nvbios_rd32(bios, bit_P.offset + 0x58);
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if (fan) {
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if (fan) {
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@ -33,7 +33,7 @@ nvbios_power_budget_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt,
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u32 power_budget;
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u32 power_budget;
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if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 ||
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if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 ||
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bit_P.length < 0x2c)
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bit_P.length < 0x30)
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return 0;
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return 0;
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power_budget = nvbios_rd32(bios, bit_P.offset + 0x2c);
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power_budget = nvbios_rd32(bios, bit_P.offset + 0x2c);
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@ -31,7 +31,7 @@ nvbios_vpstate_offset(struct nvkm_bios *b)
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struct bit_entry bit_P;
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struct bit_entry bit_P;
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if (!bit_entry(b, 'P', &bit_P)) {
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if (!bit_entry(b, 'P', &bit_P)) {
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if (bit_P.version == 2)
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if (bit_P.version == 2 && bit_P.length >= 0x3c)
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return nvbios_rd32(b, bit_P.offset + 0x38);
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return nvbios_rd32(b, bit_P.offset + 0x38);
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}
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}
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@ -589,7 +589,7 @@ gf100_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb,
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nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n",
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nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n",
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fbp, size, ltcs);
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fbp, size, ltcs);
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lcomm = min(lcomm, (u64)(size / ltcs) << 20);
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lcomm = min(lcomm, (u64)(size / ltcs) << 20);
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total += size << 20;
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total += (u64) size << 20;
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ltcn += ltcs;
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ltcn += ltcs;
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} else {
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} else {
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nvkm_debug(subdev, "FBP %d: disabled\n", fbp);
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nvkm_debug(subdev, "FBP %d: disabled\n", fbp);
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@ -48,7 +48,7 @@ gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
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mc = ioremap(mc_base, 0xd00);
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mc = ioremap(mc_base, 0xd00);
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if (!mc) {
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if (!mc) {
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nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n");
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nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n");
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return PTR_ERR(mc);
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return -ENOMEM;
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}
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}
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sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
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sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
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((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);
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((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);
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