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Merge branch 'linux-4.12' of git://github.com/skeggsb/linux into drm-next

Browse source 
Some nouveau regression fixes.

* 'linux-4.12' of git://github.com/skeggsb/linux:
  drm/nouveau/fb/gf100-: Fix 32 bit wraparound in new ram detection
  drm/nouveau/secboot/gm20b: fix the error return code in gm20b_secboot_tegra_read_wpr()
  drm/nouveau/kms: Increase max retries in scanout position queries.
  drm/nouveau/bios/bitP: check that table is long enough for optional pointers
  drm/nouveau/fifo/nv40: no ctxsw for pre-nv44 mpeg engine
This commit is contained in:
Dave Airlie 2017-05-02 04:46:01 +10:00
commit 8b03d1ed2c
9 changed files with 10 additions and 8 deletions
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2
drivers/gpu/drm/nouveau/nouveau_display.c
View file

@ -111,7 +111,7 @@ nouveau_display_scanoutpos_head(struct drm_crtc *crtc, int *vpos, int *hpos,
}; };
struct nouveau_display *disp = nouveau_display(crtc->dev); struct nouveau_display *disp = nouveau_display(crtc->dev);
struct drm_vblank_crtc *vblank = &crtc->dev->vblank[drm_crtc_index(crtc)]; struct drm_vblank_crtc *vblank = &crtc->dev->vblank[drm_crtc_index(crtc)];
int ret, retry = 1; int ret, retry = 20;
do { do {
ret = nvif_mthd(&disp->disp, 0, &args, sizeof(args)); ret = nvif_mthd(&disp->disp, 0, &args, sizeof(args));

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c
View file

@ -44,6 +44,8 @@ nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx)
*ctx = 0x38; *ctx = 0x38;
return true; return true;
case NVKM_ENGINE_MPEG: case NVKM_ENGINE_MPEG:
if (engine->subdev.device->chipset < 0x44)
return false;
*reg = 0x00330c; *reg = 0x00330c;
*ctx = 0x54; *ctx = 0x54;
return true; return true;

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c
View file

@ -33,7 +33,7 @@ nvbios_boostTe(struct nvkm_bios *bios,
u32 boost = 0; u32 boost = 0;
if (!bit_entry(bios, 'P', &bit_P)) { if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2) if (bit_P.version == 2 && bit_P.length >= 0x34)
boost = nvbios_rd32(bios, bit_P.offset + 0x30); boost = nvbios_rd32(bios, bit_P.offset + 0x30);
if (boost) { if (boost) {

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c
View file

@ -33,7 +33,7 @@ nvbios_cstepTe(struct nvkm_bios *bios,
u32 cstep = 0; u32 cstep = 0;
if (!bit_entry(bios, 'P', &bit_P)) { if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2) if (bit_P.version == 2 && bit_P.length >= 0x38)
cstep = nvbios_rd32(bios, bit_P.offset + 0x34); cstep = nvbios_rd32(bios, bit_P.offset + 0x34);
if (cstep) { if (cstep) {

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.c
View file

@ -32,7 +32,7 @@ nvbios_fan_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
u32 fan = 0; u32 fan = 0;
if (!bit_entry(bios, 'P', &bit_P)) { if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2 && bit_P.length >= 0x5a) if (bit_P.version == 2 && bit_P.length >= 0x5c)
fan = nvbios_rd32(bios, bit_P.offset + 0x58); fan = nvbios_rd32(bios, bit_P.offset + 0x58);
if (fan) { if (fan) {

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.c
View file

@ -33,7 +33,7 @@ nvbios_power_budget_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt,
u32 power_budget; u32 power_budget;
if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 || if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 ||
bit_P.length < 0x2c) bit_P.length < 0x30)
return 0; return 0;
power_budget = nvbios_rd32(bios, bit_P.offset + 0x2c); power_budget = nvbios_rd32(bios, bit_P.offset + 0x2c);

2
drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.c
View file

@ -31,7 +31,7 @@ nvbios_vpstate_offset(struct nvkm_bios *b)
struct bit_entry bit_P; struct bit_entry bit_P;
if (!bit_entry(b, 'P', &bit_P)) { if (!bit_entry(b, 'P', &bit_P)) {
if (bit_P.version == 2) if (bit_P.version == 2 && bit_P.length >= 0x3c)
return nvbios_rd32(b, bit_P.offset + 0x38); return nvbios_rd32(b, bit_P.offset + 0x38);
} }

2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
View file

@ -589,7 +589,7 @@ gf100_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb,
nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n", nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n",
fbp, size, ltcs); fbp, size, ltcs);
lcomm = min(lcomm, (u64)(size / ltcs) << 20); lcomm = min(lcomm, (u64)(size / ltcs) << 20);
total += size << 20; total += (u64) size << 20;
ltcn += ltcs; ltcn += ltcs;
} else { } else {
nvkm_debug(subdev, "FBP %d: disabled\n", fbp); nvkm_debug(subdev, "FBP %d: disabled\n", fbp);

2
drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c
View file

@ -48,7 +48,7 @@ gm20b_secboot_tegra_read_wpr(struct gm200_secboot *gsb, u32 mc_base)
mc = ioremap(mc_base, 0xd00); mc = ioremap(mc_base, 0xd00);
if (!mc) { if (!mc) {
nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n");
return PTR_ERR(mc); return -ENOMEM;
} }
sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);