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ALSA: hda - Fix SSYNC register value for non-Intel controllers
SSYNC register was once defined as 0x34-37 in the old Intel datasheet, but corrected later to 0x38-3b. For fixing the register usage, a new bit-flag is introduced for indicating the old ICH SSYNC register, and ICH* PCI entries are added explicitly to enable this quirk. Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
parent
695cd4a34e
commit
8b0bd2266f
1 changed files with 29 additions and 3 deletions
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@ -177,7 +177,8 @@ MODULE_DESCRIPTION("Intel HDA driver");
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#define ICH6_REG_INTCTL 0x20
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#define ICH6_REG_INTCTL 0x20
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#define ICH6_REG_INTSTS 0x24
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#define ICH6_REG_INTSTS 0x24
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#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
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#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
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#define ICH6_REG_SYNC 0x34
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#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
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#define ICH6_REG_SSYNC 0x38
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#define ICH6_REG_CORBLBASE 0x40
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#define ICH6_REG_CORBLBASE 0x40
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#define ICH6_REG_CORBUBASE 0x44
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#define ICH6_REG_CORBUBASE 0x44
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#define ICH6_REG_CORBWP 0x48
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#define ICH6_REG_CORBWP 0x48
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@ -479,6 +480,7 @@ enum {
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#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
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#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
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#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
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#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
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#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
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#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
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#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
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/* quirks for ATI SB / AMD Hudson */
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/* quirks for ATI SB / AMD Hudson */
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#define AZX_DCAPS_PRESET_ATI_SB \
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#define AZX_DCAPS_PRESET_ATI_SB \
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@ -1795,7 +1797,11 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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spin_lock(&chip->reg_lock);
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spin_lock(&chip->reg_lock);
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if (nsync > 1) {
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if (nsync > 1) {
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/* first, set SYNC bits of corresponding streams */
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/* first, set SYNC bits of corresponding streams */
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azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
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if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
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azx_writel(chip, OLD_SSYNC,
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azx_readl(chip, OLD_SSYNC) | sbits);
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else
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azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
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}
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}
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snd_pcm_group_for_each_entry(s, substream) {
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snd_pcm_group_for_each_entry(s, substream) {
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if (s->pcm->card != substream->pcm->card)
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if (s->pcm->card != substream->pcm->card)
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@ -1851,7 +1857,11 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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if (nsync > 1) {
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if (nsync > 1) {
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spin_lock(&chip->reg_lock);
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spin_lock(&chip->reg_lock);
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/* reset SYNC bits */
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/* reset SYNC bits */
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azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
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if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
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azx_writel(chip, OLD_SSYNC,
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azx_readl(chip, OLD_SSYNC) & ~sbits);
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else
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azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
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spin_unlock(&chip->reg_lock);
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spin_unlock(&chip->reg_lock);
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}
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}
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return 0;
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return 0;
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@ -2819,6 +2829,22 @@ static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
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/* SCH */
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/* SCH */
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{ PCI_DEVICE(0x8086, 0x811b),
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{ PCI_DEVICE(0x8086, 0x811b),
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.driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP },
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.driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP },
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{ PCI_DEVICE(0x8086, 0x2668),
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.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC }, /* ICH6 */
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{ PCI_DEVICE(0x8086, 0x27d8),
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.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC }, /* ICH7 */
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{ PCI_DEVICE(0x8086, 0x269a),
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.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC }, /* ESB2 */
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{ PCI_DEVICE(0x8086, 0x284b),
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.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC }, /* ICH8 */
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{ PCI_DEVICE(0x8086, 0x293e),
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.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC }, /* ICH9 */
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{ PCI_DEVICE(0x8086, 0x293f),
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.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC }, /* ICH9 */
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{ PCI_DEVICE(0x8086, 0x3a3e),
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.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC }, /* ICH10 */
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{ PCI_DEVICE(0x8086, 0x3a6e),
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.driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC }, /* ICH10 */
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/* Generic Intel */
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/* Generic Intel */
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
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.class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
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.class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
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