arm: Xilinx Zynq dt patches for v3.17 third pull request

- Add Adapteva Parallella board/DT
 - Add SPI nodes
 - Add CAN nodes
 - Clean Zynq description
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Merge tag 'zynq-dt-for-3.17-3' of git://git.xilinx.com/linux-xlnx into next/dt

Merge "Xilinx Zynq dt changes for v3.17 - third pull request" from Michal
Simek:

arm: Xilinx Zynq dt patches for v3.17 third pull request

- Add Adapteva Parallella board/DT
- Add SPI nodes
- Add CAN nodes
- Clean Zynq description

* tag 'zynq-dt-for-3.17-3' of git://git.xilinx.com/linux-xlnx:
  ARM: zynq: DT: Clarify Xilinx Zynq platform
  ARM: zynq: DT: Remove DMA from board DTs
  ARM: zynq: DT: Add CAN node
  ARM: dts: zynq: Add SPI
  ARM: dts: zynq: Add DMAC for Parallella
  ARM: dts: zynq: Add Parallella device tree
  Documentation: devicetree: Adapteva boards
  Documentation: devicetree: Adapteva vendor prefix

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-07-30 12:54:57 -07:00
commit 8b510129ba
7 changed files with 148 additions and 6 deletions

View file

@ -0,0 +1,7 @@
Adapteva Platforms Device Tree Bindings
---------------------------------------
Parallella board
Required root node properties:
- compatible = "adapteva,parallella";

View file

@ -1,7 +1,7 @@
Xilinx Zynq EP107 Emulation Platform board
Xilinx Zynq Platforms Device Tree Bindings
This board is an emulation platform for the Zynq product which is
based on an ARM Cortex A9 processor.
Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor
shall have the following properties.
Required root node properties:
- compatible = "xlnx,zynq-ep107";
- compatible = "xlnx,zynq-7000";

View file

@ -6,6 +6,7 @@ using them to avoid name-space collisions.
abilis Abilis Systems
active-semi Active-Semi International Inc
ad Avionic Design GmbH
adapteva Adapteva, Inc.
adi Analog Devices, Inc.
aeroflexgaisler Aeroflex Gaisler AB
ak Asahi Kasei Corp.

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@ -458,7 +458,9 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
wm8650-mid.dtb \
wm8750-apc8750.dtb \
wm8850-w70v2.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-parallella.dtb \
zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \

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@ -71,7 +71,31 @@ adc@f8007100 {
interrupts = <0 7 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 12>;
};
};
can0: can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 19>, <&clkc 36>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0 28 4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 20>, <&clkc 37>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0 51 4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
@ -140,6 +164,30 @@ uart1: serial@e0001000 {
interrupts = <0 50 4>;
};
spi0: spi@e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 26 4>;
clocks = <&clkc 25>, <&clkc 34>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 49 4>;
clocks = <&clkc 26>, <&clkc 35>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
};
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;
@ -204,6 +252,22 @@ clkc: clkc@100 {
};
};
dmac_s: dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 13 4>,
<0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>,
<0 40 4>, <0 41 4>,
<0 42 4>, <0 43 4>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <4>;
clocks = <&clkc 27>;
clock-names = "apb_pclk";
};
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;

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@ -0,0 +1,64 @@
/*
* Copyright (c) 2014 SUSE LINUX Products GmbH
*
* Derived from zynq-zed.dts:
*
* Copyright (C) 2011 Xilinx
* Copyright (C) 2012 National Instruments Corp.
* Copyright (C) 2013 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
/ {
model = "Adapteva Parallella Board";
compatible = "adapteva,parallella", "xlnx,zynq-7000";
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
chosen {
bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
linux,stdout-path = "/amba/serial@e0001000";
};
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
#address-cells = <1>;
#size-cells = <0>;
ethernet_phy: ethernet-phy@0 {
/* Marvell 88E1318 */
compatible = "ethernet-phy-id0141.0e90",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
<0x3 0x11 0xfff0 0xa>;
};
};
&i2c0 {
status = "okay";
};
&sdhci1 {
status = "okay";
};
&uart1 {
status = "okay";
};

View file

@ -29,6 +29,10 @@ chosen {
};
&can0 {
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii";