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MIPS: Provide actually relaxed MMIO accessors
Improve performance for the relevant systems and remove the DMA ordering barrier from `readX_relaxed' and `writeX_relaxed' MMIO accessors, where it is not needed according to our requirements[1]. For consistency make the same arrangement with low-level port I/O accessors, but do not actually provide any accessors making use of it. References: [1] "LINUX KERNEL MEMORY BARRIERS", Documentation/memory-barriers.txt, Section "KERNEL I/O BARRIER EFFECTS" Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20865/ Cc: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 28 additions and 20 deletions
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@ -46,6 +46,11 @@
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# define __raw_ioswabq(a, x) (x)
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# define ____raw_ioswabq(a, x) (x)
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# define __relaxed_ioswabb ioswabb
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# define __relaxed_ioswabw ioswabw
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# define __relaxed_ioswabl ioswabl
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# define __relaxed_ioswabq ioswabq
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/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
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#define IO_SPACE_LIMIT 0xffff
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@ -311,7 +316,7 @@ static inline void iounmap(const volatile void __iomem *addr)
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#define war_io_reorder_wmb() barrier()
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#endif
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#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, irq) \
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#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
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\
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static inline void pfx##write##bwlq(type val, \
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volatile void __iomem *mem) \
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@ -385,11 +390,12 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
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} \
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\
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/* prevent prefetching of coherent DMA data prematurely */ \
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rmb(); \
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if (!relax) \
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rmb(); \
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return pfx##ioswab##bwlq(__mem, __val); \
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}
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#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, p) \
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#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \
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\
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static inline void pfx##out##bwlq##p(type val, unsigned long port) \
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{ \
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@ -426,19 +432,21 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
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__val = *__addr; \
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\
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/* prevent prefetching of coherent DMA data prematurely */ \
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rmb(); \
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if (!relax) \
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rmb(); \
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return pfx##ioswab##bwlq(__addr, __val); \
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}
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#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
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#define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \
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\
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__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, 1)
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__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
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#define BUILDIO_MEM(bwlq, type) \
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\
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__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
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__BUILD_MEMORY_PFX(, bwlq, type) \
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__BUILD_MEMORY_PFX(__mem_, bwlq, type) \
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__BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \
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__BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \
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__BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \
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__BUILD_MEMORY_PFX(, bwlq, type, 0)
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BUILDIO_MEM(b, u8)
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BUILDIO_MEM(w, u16)
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@ -446,8 +454,8 @@ BUILDIO_MEM(l, u32)
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BUILDIO_MEM(q, u64)
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#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1,) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, _p)
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
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#define BUILDIO_IOPORT(bwlq, type) \
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__BUILD_IOPORT_PFX(, bwlq, type) \
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@ -462,19 +470,19 @@ BUILDIO_IOPORT(q, u64)
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#define __BUILDIO(bwlq, type) \
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\
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__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0)
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__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
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__BUILDIO(q, u64)
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#define readb_relaxed readb
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#define readw_relaxed readw
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#define readl_relaxed readl
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#define readq_relaxed readq
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#define readb_relaxed __relaxed_readb
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#define readw_relaxed __relaxed_readw
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#define readl_relaxed __relaxed_readl
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#define readq_relaxed __relaxed_readq
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#define writeb_relaxed writeb
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#define writew_relaxed writew
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#define writel_relaxed writel
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#define writeq_relaxed writeq
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#define writeb_relaxed __relaxed_writeb
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#define writew_relaxed __relaxed_writew
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#define writel_relaxed __relaxed_writel
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#define writeq_relaxed __relaxed_writeq
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#define readb_be(addr) \
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__raw_readb((__force unsigned *)(addr))
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