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arm64: traps: correctly handle MRS/MSR with XZR
Currently we hand-roll XZR-safe register handling in
user_cache_maint_handler(), though we forget to do the same in
ctr_read_handler(), and may erroneously write back to the user SP rather
than XZR.
Use the new helpers to handle these cases correctly and consistently.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Fixes: 116c81f427
("arm64: Work around systems with mismatched cache line sizes")
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
parent
6c23e2ff70
commit
8b6e70fccf
1 changed files with 4 additions and 2 deletions
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@ -466,7 +466,7 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
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int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
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int ret = 0;
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address = (rt == 31) ? 0 : regs->regs[rt];
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address = pt_regs_read_reg(regs, rt);
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switch (crm) {
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case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */
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@ -495,8 +495,10 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
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static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
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{
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int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
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pt_regs_write_reg(regs, rt, val);
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regs->regs[rt] = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
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regs->pc += 4;
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}
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