NTB: unify translation addresses
There is no need for the upstream and downstream addresses to be different for the NTB configs. Go to using a single set of address. It is still possible to configure them differently using module parameter override however. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Acked and Tested-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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@ -2204,17 +2204,17 @@ static const struct intel_ntb_xlat_reg xeon_sec_xlat = {
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};
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};
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static struct intel_b2b_addr xeon_b2b_usd_addr = {
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static struct intel_b2b_addr xeon_b2b_usd_addr = {
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.bar2_addr64 = XEON_B2B_BAR2_USD_ADDR64,
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.bar2_addr64 = XEON_B2B_BAR2_ADDR64,
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.bar4_addr64 = XEON_B2B_BAR4_USD_ADDR64,
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.bar4_addr64 = XEON_B2B_BAR4_ADDR64,
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.bar4_addr32 = XEON_B2B_BAR4_USD_ADDR32,
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.bar4_addr32 = XEON_B2B_BAR4_ADDR32,
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.bar5_addr32 = XEON_B2B_BAR5_USD_ADDR32,
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.bar5_addr32 = XEON_B2B_BAR5_ADDR32,
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};
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};
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static struct intel_b2b_addr xeon_b2b_dsd_addr = {
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static struct intel_b2b_addr xeon_b2b_dsd_addr = {
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.bar2_addr64 = XEON_B2B_BAR2_DSD_ADDR64,
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.bar2_addr64 = XEON_B2B_BAR2_ADDR64,
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.bar4_addr64 = XEON_B2B_BAR4_DSD_ADDR64,
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.bar4_addr64 = XEON_B2B_BAR4_ADDR64,
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.bar4_addr32 = XEON_B2B_BAR4_DSD_ADDR32,
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.bar4_addr32 = XEON_B2B_BAR4_ADDR32,
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.bar5_addr32 = XEON_B2B_BAR5_DSD_ADDR32,
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.bar5_addr32 = XEON_B2B_BAR5_ADDR32,
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};
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};
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/* operations for primary side of local ntb */
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/* operations for primary side of local ntb */
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@ -227,16 +227,11 @@
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/* Use the following addresses for translation between b2b ntb devices in case
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/* Use the following addresses for translation between b2b ntb devices in case
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* the hardware default values are not reliable. */
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* the hardware default values are not reliable. */
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#define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull
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#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
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#define XEON_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
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#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
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#define XEON_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
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#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
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#define XEON_B2B_BAR4_USD_ADDR32 0x20000000u
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#define XEON_B2B_BAR4_ADDR32 0x20000000u
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#define XEON_B2B_BAR5_USD_ADDR32 0x40000000u
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#define XEON_B2B_BAR5_ADDR32 0x40000000u
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#define XEON_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
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#define XEON_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
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#define XEON_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
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#define XEON_B2B_BAR4_DSD_ADDR32 0xa0000000u
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#define XEON_B2B_BAR5_DSD_ADDR32 0xc0000000u
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/* The peer ntb secondary config space is 32KB fixed size */
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/* The peer ntb secondary config space is 32KB fixed size */
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#define XEON_B2B_MIN_SIZE 0x8000
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#define XEON_B2B_MIN_SIZE 0x8000
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