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phy: tegra: xusb: Support sleepwalk for Tegra234
Add new registers programming in sleepwalk sequence for Tegra234: MASTER_ENABLE_A/B/C/D in XUSB_AO_UTMIP_SLEEPWALK. Signed-off-by: Henry Lin <henryl@nvidia.com> Signed-off-by: Haotien Hsu <haotienh@nvidia.com> Link: https://lore.kernel.org/r/20230309061708.4156383-1-haotienh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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2 changed files with 21 additions and 0 deletions
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@ -145,6 +145,8 @@
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#define MODE_HS MODE(0)
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#define MODE_RST MODE(1)
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#define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x) (0xa0 + (x) * 4)
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#define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4)
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#define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4)
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#define FAKE_USBOP_VAL BIT(0)
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@ -172,24 +174,30 @@
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#define AP_A BIT(4)
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#define AN_A BIT(5)
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#define HIGHZ_A BIT(6)
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#define MASTER_ENABLE_A BIT(7)
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/* phase B */
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#define USBOP_RPD_B BIT(8)
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#define USBON_RPD_B BIT(9)
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#define AP_B BIT(12)
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#define AN_B BIT(13)
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#define HIGHZ_B BIT(14)
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#define MASTER_ENABLE_B BIT(15)
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/* phase C */
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#define USBOP_RPD_C BIT(16)
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#define USBON_RPD_C BIT(17)
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#define AP_C BIT(20)
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#define AN_C BIT(21)
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#define HIGHZ_C BIT(22)
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#define MASTER_ENABLE_C BIT(23)
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/* phase D */
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#define USBOP_RPD_D BIT(24)
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#define USBON_RPD_D BIT(25)
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#define AP_D BIT(28)
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#define AN_D BIT(29)
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#define HIGHZ_D BIT(30)
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#define MASTER_ENABLE_D BIT(31)
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#define MASTER_ENABLE_B_C_D \
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(MASTER_ENABLE_B | MASTER_ENABLE_C | MASTER_ENABLE_D)
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#define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4)
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/* phase A */
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@ -417,6 +425,8 @@ static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
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value |= HIGHZ_A;
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value |= AP_A;
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value |= AN_B | AN_C | AN_D;
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if (padctl->soc->supports_lp_cfg_en)
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value |= MASTER_ENABLE_B_C_D;
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break;
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case USB_SPEED_LOW:
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@ -424,6 +434,8 @@ static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
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value |= HIGHZ_A;
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value |= AN_A;
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value |= AP_B | AP_C | AP_D;
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if (padctl->soc->supports_lp_cfg_en)
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value |= MASTER_ENABLE_B_C_D;
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break;
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default:
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@ -488,6 +500,13 @@ static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
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value |= WAKE_VAL_NONE;
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ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
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if (padctl->soc->supports_lp_cfg_en) {
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/* disable the four stages of sleepwalk */
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value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK(index));
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value &= ~(MASTER_ENABLE_A | MASTER_ENABLE_B_C_D);
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ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
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}
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/* power down the line state detectors of the port */
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value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
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value |= USBOP_VAL_PD | USBON_VAL_PD;
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@ -1673,6 +1692,7 @@ const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {
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.supports_gen2 = true,
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.poll_trk_completed = true,
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.trk_hw_mode = true,
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.supports_lp_cfg_en = true,
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};
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EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
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#endif
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@ -434,6 +434,7 @@ struct tegra_xusb_padctl_soc {
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bool need_fake_usb3_port;
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bool poll_trk_completed;
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bool trk_hw_mode;
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bool supports_lp_cfg_en;
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};
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struct tegra_xusb_padctl {
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