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ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant
A typical SMP system expects cache coherency. Initial NPS platform support was slated to be SMP w/o cache coherency. However it seems the platform now selects that option, so there is no point in keeping it around. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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3 changed files with 0 additions and 8 deletions
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@ -180,16 +180,12 @@ config CPU_BIG_ENDIAN
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config SMP
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config SMP
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bool "Symmetric Multi-Processing"
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bool "Symmetric Multi-Processing"
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default n
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default n
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select ARC_HAS_COH_CACHES if ISA_ARCV2
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select ARC_MCIP if ISA_ARCV2
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select ARC_MCIP if ISA_ARCV2
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help
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help
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This enables support for systems with more than one CPU.
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This enables support for systems with more than one CPU.
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if SMP
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if SMP
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config ARC_HAS_COH_CACHES
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def_bool n
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config NR_CPUS
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config NR_CPUS
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int "Maximum number of CPUs (2-4096)"
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int "Maximum number of CPUs (2-4096)"
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range 2 4096
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range 2 4096
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@ -219,8 +215,6 @@ config ARC_MCIP
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menuconfig ARC_CACHE
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menuconfig ARC_CACHE
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bool "Enable Cache Support"
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bool "Enable Cache Support"
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default y
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default y
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# if SMP, cache enabled ONLY if ARC implementation has cache coherency
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depends on !SMP || ARC_HAS_COH_CACHES
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if ARC_CACHE
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if ARC_CACHE
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@ -5,7 +5,6 @@
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menuconfig ARC_PLAT_EZNPS
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menuconfig ARC_PLAT_EZNPS
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bool "\"EZchip\" ARC dev platform"
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bool "\"EZchip\" ARC dev platform"
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select ARC_HAS_COH_CACHES if SMP
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select CPU_BIG_ENDIAN
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select CPU_BIG_ENDIAN
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select CLKSRC_NPS
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select CLKSRC_NPS
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select EZNPS_GIC
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select EZNPS_GIC
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@ -8,7 +8,6 @@
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menuconfig ARC_PLAT_SIM
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menuconfig ARC_PLAT_SIM
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bool "ARC nSIM based simulation virtual platforms"
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bool "ARC nSIM based simulation virtual platforms"
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select ARC_HAS_COH_CACHES if SMP
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help
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help
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Support for nSIM based ARC simulation platforms
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Support for nSIM based ARC simulation platforms
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This includes the standalone nSIM (uart only) vs. System C OSCI VP
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This includes the standalone nSIM (uart only) vs. System C OSCI VP
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