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ARM: dts: meson: move the L2 cache-controller inside the SoC node

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All IO mapped SoC peripherals should be within the "soc" node. Move the
L2 cache-controller there as well since it's the only one not following
this pattern.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200815182223.408965-1-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl 2020-08-15 20:22:23 +02:00 committed by Kevin Hilman
parent 9123e3a74e
commit 8bcbcdb729
1 changed files with 7 additions and 7 deletions
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14
arch/arm/boot/dts/meson.dtsi
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@ -11,13 +11,6 @@ / {
#size-cells = <1>;
interrupt-parent = <&gic>;
L2: cache-controller@c4200000 {
compatible = "arm,pl310-cache";
reg = <0xc4200000 0x1000>;
cache-unified;
cache-level = <2>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -172,6 +165,13 @@ timer_abcde: timer@9940 {
};
};
L2: cache-controller@c4200000 {
compatible = "arm,pl310-cache";
reg = <0xc4200000 0x1000>;
cache-unified;
cache-level = <2>;
};
periph: bus@c4300000 {
compatible = "simple-bus";
reg = <0xc4300000 0x10000>;