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mmc: mediatek: fix CMD_TA to 2 for MT8173 HS200/HS400 mode
commit8f34e5bd70
upstream. there is a chance that always get response CRC error after HS200 tuning, the reason is that need set CMD_TA to 2. this modification is only for MT8173. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Tested-by: Hsin-Yi Wang <hsinyi@chromium.org> Cc: stable@vger.kernel.org Fixes:1ede5cb88a
("mmc: mediatek: Use data tune for CMD line tune") Link: https://lore.kernel.org/r/20191204071958.18553-1-chaotian.jing@mediatek.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 3 additions and 0 deletions
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@ -212,6 +212,8 @@
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#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
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#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
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#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
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#define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
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#define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
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#define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
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@ -1442,6 +1444,7 @@ static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
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/* select EMMC50 PAD CMD tune */
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sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
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sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
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if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
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mmc->ios.timing == MMC_TIMING_UHS_SDR104)
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