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drm/i915/psr: Check if source supports sink specific SU granularity

Browse source 
According to eDP spec, sink can required specific selective update
granularity that source must comply.
Here caching the value if required and checking if source supports
it.

v3:
- Returning the default granularity in case DPCD read fails(Dhinakaran)
- Changed DPCD error message level(Dhinakaran)

v4:
- Setting granularity to defaul when granularity read is equal to
0(Dhinakaran)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181204003403.23361-9-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza 2018-12-03 16:34:03 -08:00
parent bef5e5b3be
commit 8c0d2c2908
2 changed files with 34 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
drivers/gpu/drm/i915/i915_drv.h
View file

@ -509,6 +509,7 @@ struct i915_psr {
ktime_t last_exit;
bool sink_not_reliable;
bool irq_aux_error;
u16 su_x_granularity;
};
enum intel_pch {

37
drivers/gpu/drm/i915/intel_psr.c
View file

@ -261,6 +261,32 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
return val;
}
static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
{
u16 val;
ssize_t r;
/*
* Returning the default X granularity if granularity not required or
* if DPCD read fails
*/
if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED))
return 4;
r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &val, 2);
if (r != 2)
DRM_DEBUG_KMS("Unable to read DP_PSR2_SU_X_GRANULARITY\n");
/*
* Spec says that if the value read is 0 the default granularity should
* be used instead.
*/
if (r != 2 || val == 0)
val = 4;
return val;
}
void intel_psr_init_dpcd(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv =
@ -315,6 +341,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
if (dev_priv->psr.sink_psr2_support) {
dev_priv->psr.colorimetry_support =
intel_dp_get_colorimetry_status(intel_dp);
dev_priv->psr.su_x_granularity =
intel_dp_get_su_x_granulartiy(intel_dp);
}
}
}
@ -539,11 +567,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
/*
* HW sends SU blocks of size four scan lines, which means the starting
* X coordinate and Y granularity requirements will always be met. We
* only need to validate the SU block width is a multiple of 4.
* only need to validate the SU block width is a multiple of
* x granularity.
*/
if (crtc_hdisplay % 4) {
DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of 4\n",
crtc_hdisplay);
if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n",
crtc_hdisplay, dev_priv->psr.su_x_granularity);
return false;
}