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arm64: errata: Don't enable workarounds for "rare" errata by default
Arm classifies some of its CPU errata as "rare", indicating that the hardware error is unlikely to occur in practice. Given that the cost of errata workarounds can often be significant in terms of power and performance, don't enable workarounds for "rare" errata by default and update our documentation to reflect that. Cc: James Morse <james.morse@arm.com> Signed-off-by: Will Deacon <will@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20240209183916.25860-1-will@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2 changed files with 14 additions and 16 deletions
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@ -35,8 +35,9 @@ can be triggered by Linux).
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For software workarounds that may adversely impact systems unaffected by
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the erratum in question, a Kconfig entry is added under "Kernel
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Features" -> "ARM errata workarounds via the alternatives framework".
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These are enabled by default and patched in at runtime when an affected
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CPU is detected. For less-intrusive workarounds, a Kconfig option is not
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With the exception of workarounds for errata deemed "rare" by Arm, these
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are enabled by default and patched in at runtime when an affected CPU is
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detected. For less-intrusive workarounds, a Kconfig option is not
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available and the code is structured (preferably with a comment) in such
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a way that the erratum will not be hit.
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@ -547,9 +547,8 @@ config ARM64_ERRATUM_832075
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If unsure, say Y.
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config ARM64_ERRATUM_834220
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bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
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bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)"
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depends on KVM
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default y
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help
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This option adds an alternative code sequence to work around ARM
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erratum 834220 on Cortex-A57 parts up to r1p2.
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@ -565,7 +564,7 @@ config ARM64_ERRATUM_834220
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as it depends on the alternative framework, which will only patch
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the kernel if an affected CPU is detected.
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If unsure, say Y.
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If unsure, say N.
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config ARM64_ERRATUM_1742098
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bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
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@ -692,8 +691,7 @@ config ARM64_WORKAROUND_REPEAT_TLBI
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bool
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config ARM64_ERRATUM_2441007
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bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
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default y
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bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
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select ARM64_WORKAROUND_REPEAT_TLBI
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help
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This option adds a workaround for ARM Cortex-A55 erratum #2441007.
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@ -706,11 +704,10 @@ config ARM64_ERRATUM_2441007
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Work around this by adding the affected CPUs to the list that needs
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TLB sequences to be done twice.
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If unsure, say Y.
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If unsure, say N.
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config ARM64_ERRATUM_1286807
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bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
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default y
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bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)"
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select ARM64_WORKAROUND_REPEAT_TLBI
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help
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This option adds a workaround for ARM Cortex-A76 erratum 1286807.
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@ -724,6 +721,8 @@ config ARM64_ERRATUM_1286807
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invalidated has been observed by other observers. The
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workaround repeats the TLBI+DSB operation.
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If unsure, say N.
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config ARM64_ERRATUM_1463225
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bool "Cortex-A76: Software Step might prevent interrupt recognition"
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default y
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@ -743,8 +742,7 @@ config ARM64_ERRATUM_1463225
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If unsure, say Y.
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config ARM64_ERRATUM_1542419
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bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
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default y
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bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
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help
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This option adds a workaround for ARM Neoverse-N1 erratum
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1542419.
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@ -756,7 +754,7 @@ config ARM64_ERRATUM_1542419
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Workaround the issue by hiding the DIC feature from EL0. This
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forces user-space to perform cache maintenance.
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If unsure, say Y.
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If unsure, say N.
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config ARM64_ERRATUM_1508412
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bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
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@ -931,8 +929,7 @@ config ARM64_ERRATUM_2224489
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If unsure, say Y.
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config ARM64_ERRATUM_2441009
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bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
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default y
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bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
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select ARM64_WORKAROUND_REPEAT_TLBI
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help
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This option adds a workaround for ARM Cortex-A510 erratum #2441009.
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@ -945,7 +942,7 @@ config ARM64_ERRATUM_2441009
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Work around this by adding the affected CPUs to the list that needs
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TLB sequences to be done twice.
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If unsure, say Y.
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If unsure, say N.
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config ARM64_ERRATUM_2064142
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bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
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