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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-03 07:38:10 +00:00
Add support for XCVR on i.MX93 platform
Merge series from Chancel Liu <chancel.liu@nxp.com>: This patchset supports XCVR on i.MX93 platform. changes in v2: - remove unnecessary code which causes kernel test robot reporting error Chancel Liu (3): ASoC: dt-bindings: fsl,xcvr: Add compatible string for i.MX93 platform ASoC: fsl_xcvr: Add support for i.MX93 platform ASoC: fsl_xcvr: Add constraints of period size while using eDMA .../devicetree/bindings/sound/fsl,xcvr.yaml | 1 + sound/soc/fsl/fsl_xcvr.c | 155 ++++++++++++------ sound/soc/fsl/fsl_xcvr.h | 7 + 3 files changed, 115 insertions(+), 48 deletions(-) -- 2.25.1
This commit is contained in:
Mark Brown
commit
8c187e2212
3 changed files with 115 additions and 48 deletions
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@ -21,6 +21,7 @@ properties:
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compatible:
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enum:
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- fsl,imx8mp-xcvr
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- fsl,imx93-xcvr
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reg:
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items:
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@ -21,6 +21,8 @@
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struct fsl_xcvr_soc_data {
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const char *fw_name;
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bool spdif_only;
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bool use_edma;
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};
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struct fsl_xcvr {
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@ -261,6 +263,9 @@ static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx)
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u32 i, div = 0, log2;
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int ret;
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if (xcvr->soc_data->spdif_only)
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return 0;
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for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) {
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if (fsl_xcvr_pll_cfg[i].fout % freq == 0) {
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div = fsl_xcvr_pll_cfg[i].fout / freq;
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@ -353,6 +358,7 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
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struct device *dev = &xcvr->pdev->dev;
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int ret;
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freq = xcvr->soc_data->spdif_only ? freq / 10 : freq;
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clk_disable_unprepare(xcvr->phy_clk);
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ret = clk_set_rate(xcvr->phy_clk, freq);
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if (ret < 0) {
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@ -365,6 +371,8 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
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return ret;
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}
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if (xcvr->soc_data->spdif_only)
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return 0;
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/* Release AI interface from reset */
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ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
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FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
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@ -531,6 +539,16 @@ static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
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return -EBUSY;
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}
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/*
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* EDMA controller needs period size to be a multiple of
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* tx/rx maxburst
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*/
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if (xcvr->soc_data->use_edma)
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snd_pcm_hw_constraint_step(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
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tx ? xcvr->dma_prms_tx.maxburst :
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xcvr->dma_prms_rx.maxburst);
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switch (xcvr->mode) {
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case FSL_XCVR_MODE_SPDIF:
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case FSL_XCVR_MODE_ARC:
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@ -547,10 +565,12 @@ static int fsl_xcvr_startup(struct snd_pcm_substream *substream,
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xcvr->streams |= BIT(substream->stream);
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/* Disable XCVR controls if there is stream started */
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
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if (!xcvr->soc_data->spdif_only) {
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/* Disable XCVR controls if there is stream started */
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false);
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false);
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false);
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}
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return 0;
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}
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@ -567,12 +587,13 @@ static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream,
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/* Enable XCVR controls if there is no stream started */
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if (!xcvr->streams) {
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
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(xcvr->mode == FSL_XCVR_MODE_ARC));
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
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(xcvr->mode == FSL_XCVR_MODE_EARC));
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if (!xcvr->soc_data->spdif_only) {
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true);
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name,
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(xcvr->mode == FSL_XCVR_MODE_ARC));
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fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name,
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(xcvr->mode == FSL_XCVR_MODE_EARC));
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}
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ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0,
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FSL_XCVR_IRQ_EARC_ALL, 0);
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if (ret < 0) {
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@ -673,7 +694,10 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd,
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dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret);
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return ret;
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}
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fallthrough;
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if (xcvr->soc_data->spdif_only)
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break;
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else
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fallthrough;
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case FSL_XCVR_MODE_EARC:
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/* clear ISR_CMDC_TX_EN, W1C */
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ret = regmap_write(xcvr->regmap,
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@ -877,9 +901,13 @@ static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai)
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snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx);
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snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
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snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
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snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
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if (xcvr->soc_data->spdif_only)
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xcvr->mode = FSL_XCVR_MODE_SPDIF;
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else {
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snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1);
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snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1);
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snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1);
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}
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snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls,
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ARRAY_SIZE(fsl_xcvr_tx_ctls));
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snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls,
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@ -930,10 +958,11 @@ static const struct reg_default fsl_xcvr_reg_defaults[] = {
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{ FSL_XCVR_ISR_SET, 0x00000000 },
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{ FSL_XCVR_ISR_CLR, 0x00000000 },
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{ FSL_XCVR_ISR_TOG, 0x00000000 },
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{ FSL_XCVR_RX_DPTH_CTRL, 0x00002C89 },
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{ FSL_XCVR_RX_DPTH_CTRL_SET, 0x00002C89 },
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{ FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00002C89 },
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{ FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00002C89 },
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{ FSL_XCVR_CLK_CTRL, 0x0000018F },
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{ FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 },
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{ FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 },
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{ FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 },
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{ FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 },
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{ FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 },
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{ FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
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{ FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
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@ -966,6 +995,12 @@ static const struct reg_default fsl_xcvr_reg_defaults[] = {
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static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
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{
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struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
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if (xcvr->soc_data->spdif_only)
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if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) ||
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reg > FSL_XCVR_TX_DPTH_BCRR)
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return false;
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switch (reg) {
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case FSL_XCVR_VERSION:
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case FSL_XCVR_EXT_CTRL:
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@ -991,6 +1026,12 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
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case FSL_XCVR_RX_DPTH_CTRL_SET:
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case FSL_XCVR_RX_DPTH_CTRL_CLR:
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case FSL_XCVR_RX_DPTH_CTRL_TOG:
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case FSL_XCVR_RX_CS_DATA_0:
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case FSL_XCVR_RX_CS_DATA_1:
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case FSL_XCVR_RX_CS_DATA_2:
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case FSL_XCVR_RX_CS_DATA_3:
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case FSL_XCVR_RX_CS_DATA_4:
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case FSL_XCVR_RX_CS_DATA_5:
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case FSL_XCVR_RX_DPTH_CNTR_CTRL:
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case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
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case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
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@ -1027,6 +1068,11 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
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static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
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{
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struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
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if (xcvr->soc_data->spdif_only)
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if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA)
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return false;
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switch (reg) {
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case FSL_XCVR_EXT_CTRL:
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case FSL_XCVR_EXT_IER0:
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@ -1103,32 +1149,34 @@ static irqreturn_t irq0_isr(int irq, void *devid)
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if (isr & FSL_XCVR_IRQ_NEW_CS) {
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dev_dbg(dev, "Received new CS block\n");
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isr_clr |= FSL_XCVR_IRQ_NEW_CS;
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/* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
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regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_PAGE_MASK,
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FSL_XCVR_EXT_CTRL_PAGE(8));
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if (!xcvr->soc_data->spdif_only) {
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/* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */
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regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_PAGE_MASK,
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FSL_XCVR_EXT_CTRL_PAGE(8));
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/* Find updated CS buffer */
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reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
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reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
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memcpy_fromio(&val, reg_ctrl, sizeof(val));
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if (!val) {
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reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
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reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
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/* Find updated CS buffer */
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reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0;
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reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0;
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memcpy_fromio(&val, reg_ctrl, sizeof(val));
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}
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if (val) {
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/* copy CS buffer */
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memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
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sizeof(xcvr->rx_iec958.status));
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for (i = 0; i < 6; i++) {
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val = *(u32 *)(xcvr->rx_iec958.status + i*4);
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*(u32 *)(xcvr->rx_iec958.status + i*4) =
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bitrev32(val);
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if (!val) {
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reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1;
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reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1;
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memcpy_fromio(&val, reg_ctrl, sizeof(val));
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}
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if (val) {
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/* copy CS buffer */
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memcpy_fromio(&xcvr->rx_iec958.status, reg_buff,
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sizeof(xcvr->rx_iec958.status));
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for (i = 0; i < 6; i++) {
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val = *(u32 *)(xcvr->rx_iec958.status + i*4);
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*(u32 *)(xcvr->rx_iec958.status + i*4) =
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bitrev32(val);
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}
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/* clear CS control register */
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memset_io(reg_ctrl, 0, sizeof(val));
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}
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/* clear CS control register */
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memset_io(reg_ctrl, 0, sizeof(val));
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}
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}
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if (isr & FSL_XCVR_IRQ_NEW_UD) {
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@ -1168,8 +1216,14 @@ static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = {
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.fw_name = "imx/xcvr/xcvr-imx8mp.bin",
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};
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static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = {
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.spdif_only = true,
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.use_edma = true,
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};
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static const struct of_device_id fsl_xcvr_dt_ids[] = {
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{ .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data },
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{ .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids);
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@ -1229,7 +1283,7 @@ static int fsl_xcvr_probe(struct platform_device *pdev)
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return PTR_ERR(xcvr->regmap);
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}
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xcvr->reset = devm_reset_control_get_exclusive(dev, NULL);
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xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
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if (IS_ERR(xcvr->reset)) {
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dev_err(dev, "failed to get XCVR reset control\n");
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return PTR_ERR(xcvr->reset);
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@ -1306,12 +1360,14 @@ static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev)
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if (ret < 0)
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dev_err(dev, "Failed to clear IER0: %d\n", ret);
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/* Assert M0+ reset */
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ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_CORE_RESET,
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FSL_XCVR_EXT_CTRL_CORE_RESET);
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if (ret < 0)
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dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
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if (!xcvr->soc_data->spdif_only) {
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/* Assert M0+ reset */
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ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
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FSL_XCVR_EXT_CTRL_CORE_RESET,
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FSL_XCVR_EXT_CTRL_CORE_RESET);
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if (ret < 0)
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dev_err(dev, "Failed to assert M0+ core: %d\n", ret);
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}
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regcache_cache_only(xcvr->regmap, true);
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@ -1367,6 +1423,9 @@ static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev)
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goto stop_spba_clk;
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}
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if (xcvr->soc_data->spdif_only)
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return 0;
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ret = reset_control_deassert(xcvr->reset);
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if (ret) {
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dev_err(dev, "failed to deassert M0+ reset.\n");
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@ -49,6 +49,13 @@
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#define FSL_XCVR_RX_DPTH_CTRL_CLR 0x188
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#define FSL_XCVR_RX_DPTH_CTRL_TOG 0x18c
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#define FSL_XCVR_RX_CS_DATA_0 0x190
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#define FSL_XCVR_RX_CS_DATA_1 0x194
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#define FSL_XCVR_RX_CS_DATA_2 0x198
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#define FSL_XCVR_RX_CS_DATA_3 0x19C
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#define FSL_XCVR_RX_CS_DATA_4 0x1A0
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#define FSL_XCVR_RX_CS_DATA_5 0x1A4
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#define FSL_XCVR_RX_DPTH_CNTR_CTRL 0x1C0
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#define FSL_XCVR_RX_DPTH_CNTR_CTRL_SET 0x1C4
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#define FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR 0x1C8
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