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perf/x86/intel: Use 0x11 as extra reg test value
The next patch adds a new perf extra register where 0x1ff is not a valid value. Use 0x11 instead. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1435707205-6676-3-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -3579,7 +3579,7 @@ __init int intel_pmu_init(void)
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*/
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if (x86_pmu.extra_regs) {
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for (er = x86_pmu.extra_regs; er->msr; er++) {
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er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
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er->extra_msr_access = check_msr(er->msr, 0x11UL);
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/* Disable LBR select mapping */
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if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
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x86_pmu.lbr_sel_map = NULL;
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