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arm: dts: zynq: Move crystal freq. to board level

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The fact that all supported boards use the same 33MHz crystal is a
co-incidence. The Zynq PS support a range of crystal freqs so the
hardcoded setting should be removed from the dtsi. Re-implement it
on the board level.

This prepares support for Zynq boards with different crystal
frequencies (e.g. the Digilent ZYBO).

Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Peter Crosthwaite 2014-12-01 10:25:49 +10:00 committed by Michal Simek
parent d86e3104e8
commit 8c7634c0ee
5 changed files with 16 additions and 1 deletions
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1
arch/arm/boot/dts/zynq-7000.dtsi
View file

@ -244,7 +244,6 @@ slcr: slcr@f8000000 {
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
fclk-enable = <0>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",

4
arch/arm/boot/dts/zynq-parallella.dts
View file

@ -34,6 +34,10 @@ chosen {
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";

4
arch/arm/boot/dts/zynq-zc702.dts
View file

@ -42,6 +42,10 @@ &can0 {
status = "okay";
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";

4
arch/arm/boot/dts/zynq-zc706.dts
View file

@ -29,6 +29,10 @@ chosen {
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";

4
arch/arm/boot/dts/zynq-zed.dts
View file

@ -29,6 +29,10 @@ chosen {
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";