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ARM/PCI: Move to generic PCI domains
Most if not all ARM PCI host controller device drivers either ignore the domain field in the pci_sys_data structure or just increment it every time a host controller is probed, using it as a domain counter. Therefore, instead of relying on pci_sys_data to stash the domain number in a standard location, ARM pcibios code can be moved to the newly introduced generic PCI domains code, implemented in commits:41e5c0f81d
("of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()")670ba0c888
("PCI: Add generic domain handling") ARM code is made to select PCI_DOMAINS_GENERIC by default, which builds core PCI code that assigns the domain number through the generic function: void pci_bus_assign_domain_nr(...) that relies on a DT property to define the domain number or falls back to a counter according to a predefined logic; its usage replaces the current domain assignment code in PCI host controllers present in the kernel. Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Yijing Wang <wangyijing@huawei.com> Reviewed-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> # mvebu Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Arnd Bergmann <arnd@arndb.de> CC: Mohit Kumar <mohit.kumar@st.com>
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parent
c88d54ba0c
commit
8c7d14746a
7 changed files with 5 additions and 35 deletions
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@ -1279,6 +1279,9 @@ config PCI_DOMAINS
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bool
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depends on PCI
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config PCI_DOMAINS_GENERIC
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def_bool PCI_DOMAINS
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config PCI_NANOENGINE
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bool "BSE nanoEngine PCI support"
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depends on SA1100_NANOENGINE
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@ -19,9 +19,6 @@ struct pci_bus;
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struct device;
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struct hw_pci {
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#ifdef CONFIG_PCI_DOMAINS
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int domain;
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#endif
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#ifdef CONFIG_PCI_MSI
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struct msi_controller *msi_ctrl;
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#endif
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@ -45,9 +42,6 @@ struct hw_pci {
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* Per-controller structure
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*/
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struct pci_sys_data {
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#ifdef CONFIG_PCI_DOMAINS
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int domain;
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#endif
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#ifdef CONFIG_PCI_MSI
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struct msi_controller *msi_ctrl;
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#endif
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@ -18,13 +18,6 @@ static inline int pcibios_assign_all_busses(void)
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}
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#ifdef CONFIG_PCI_DOMAINS
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static inline int pci_domain_nr(struct pci_bus *bus)
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{
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struct pci_sys_data *root = bus->sysdata;
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return root->domain;
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}
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return pci_domain_nr(bus);
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@ -463,9 +463,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
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if (!sys)
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panic("PCI: unable to allocate sys data!");
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#ifdef CONFIG_PCI_DOMAINS
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sys->domain = hw->domain;
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#endif
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#ifdef CONFIG_PCI_MSI
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sys->msi_ctrl = hw->msi_ctrl;
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#endif
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@ -101,9 +101,7 @@ struct mvebu_pcie {
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struct mvebu_pcie_port *ports;
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struct msi_controller *msi;
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struct resource io;
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char io_name[30];
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struct resource realio;
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char mem_name[30];
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struct resource mem;
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struct resource busn;
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int nports;
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@ -723,18 +721,9 @@ static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct mvebu_pcie *pcie = sys_to_pcie(sys);
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int i;
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int domain = 0;
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#ifdef CONFIG_PCI_DOMAINS
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domain = sys->domain;
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#endif
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snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x",
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domain);
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pcie->mem.name = pcie->mem_name;
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snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain);
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pcie->realio.name = pcie->io_name;
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pcie->mem.name = "PCI MEM";
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pcie->realio.name = "PCI I/O";
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if (request_resource(&iomem_resource, &pcie->mem))
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return 0;
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@ -508,9 +508,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
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dw_pci.private_data = (void **)&pp;
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pci_common_init_dev(pp->dev, &dw_pci);
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#ifdef CONFIG_PCI_DOMAINS
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dw_pci.domain++;
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#endif
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return 0;
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}
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@ -397,9 +397,6 @@ static void rcar_pcie_enable(struct rcar_pcie *pcie)
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#endif
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pci_common_init_dev(&pdev->dev, &rcar_pci);
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#ifdef CONFIG_PCI_DOMAINS
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rcar_pci.domain++;
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#endif
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}
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static int phy_wait_for_ack(struct rcar_pcie *pcie)
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