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dma40: use helper for channel registers base
The register offset computation for accessing channel registers is copy/pasted in several places. Create a helper function to do it. Acked-by: Per Forlin <per.forlin@stericsson.com> Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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7d83a854a1
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8ca84687b9
1 changed files with 30 additions and 44 deletions
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@ -306,6 +306,12 @@ static struct device *chan2dev(struct d40_chan *d40c)
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return &d40c->chan.dev->device;
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}
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static void __iomem *chan_base(struct d40_chan *chan)
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{
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return chan->base->virtbase + D40_DREG_PCBASE +
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chan->phy_chan->num * D40_DREG_PCDELTA;
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}
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static int d40_pool_lli_alloc(struct d40_desc *d40d,
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int lli_len, bool is_log)
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{
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@ -695,8 +701,7 @@ static void d40_term_all(struct d40_chan *d40c)
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static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
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u32 event, int reg)
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{
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void __iomem *addr = d40c->base->virtbase + D40_DREG_PCBASE
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+ d40c->phy_chan->num * D40_DREG_PCDELTA + reg;
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void __iomem *addr = chan_base(d40c) + reg;
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int tries;
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if (!enable) {
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@ -755,15 +760,12 @@ static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
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static u32 d40_chan_has_events(struct d40_chan *d40c)
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{
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void __iomem *chanbase = chan_base(d40c);
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u32 val;
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val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SSLNK);
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val = readl(chanbase + D40_CHAN_REG_SSLNK);
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val |= readl(chanbase + D40_CHAN_REG_SDLNK);
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val |= readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDLNK);
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return val;
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}
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@ -810,29 +812,17 @@ static void d40_config_write(struct d40_chan *d40c)
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writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
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if (d40c->log_num != D40_PHY_CHAN) {
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int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
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& D40_SREG_ELEM_LOG_LIDX_MASK;
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void __iomem *chanbase = chan_base(d40c);
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/* Set default config for CFG reg */
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writel(d40c->src_def_cfg,
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d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SSCFG);
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writel(d40c->dst_def_cfg,
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d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDCFG);
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writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
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writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
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/* Set LIDX for lcla */
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writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
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D40_SREG_ELEM_LOG_LIDX_MASK,
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d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDELT);
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writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
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D40_SREG_ELEM_LOG_LIDX_MASK,
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d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SSELT);
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writel(lidx, chanbase + D40_CHAN_REG_SSELT);
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writel(lidx, chanbase + D40_CHAN_REG_SDELT);
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}
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}
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@ -843,12 +833,12 @@ static u32 d40_residue(struct d40_chan *d40c)
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if (d40c->log_num != D40_PHY_CHAN)
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num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
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>> D40_MEM_LCSP2_ECNT_POS;
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else
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num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDELT) &
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D40_SREG_ELEM_PHY_ECNT_MASK) >>
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D40_SREG_ELEM_PHY_ECNT_POS;
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else {
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u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
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num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
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>> D40_SREG_ELEM_PHY_ECNT_POS;
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}
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return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
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}
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@ -859,10 +849,9 @@ static bool d40_tx_is_linked(struct d40_chan *d40c)
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if (d40c->log_num != D40_PHY_CHAN)
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is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
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else
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is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDLNK) &
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D40_SREG_LNK_PHYS_LNK_MASK;
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is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
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& D40_SREG_LNK_PHYS_LNK_MASK;
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return is_link;
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}
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@ -1550,6 +1539,7 @@ static int d40_free_dma(struct d40_chan *d40c)
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static bool d40_is_paused(struct d40_chan *d40c)
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{
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void __iomem *chanbase = chan_base(d40c);
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bool is_paused = false;
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unsigned long flags;
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void __iomem *active_reg;
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@ -1576,14 +1566,10 @@ static bool d40_is_paused(struct d40_chan *d40c)
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if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
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d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
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event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
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status = readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SDLNK);
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status = readl(chanbase + D40_CHAN_REG_SDLNK);
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} else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
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event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
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status = readl(d40c->base->virtbase + D40_DREG_PCBASE +
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d40c->phy_chan->num * D40_DREG_PCDELTA +
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D40_CHAN_REG_SSLNK);
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status = readl(chanbase + D40_CHAN_REG_SSLNK);
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} else {
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dev_err(&d40c->chan.dev->device,
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"[%s] Unknown direction\n", __func__);
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