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powerpc/book3s: Add an HV variant of FIXUP_ENDIAN that is recoverable
Add an HV variant of FIXUP_ENDIAN which uses HSRR[01] and does not clear MSR[RI], which improves recoverability. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -774,6 +774,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
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#ifdef CONFIG_PPC_BOOK3E
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#ifdef CONFIG_PPC_BOOK3E
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#define FIXUP_ENDIAN
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#define FIXUP_ENDIAN
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#else
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#else
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/*
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* This version may be used in in HV or non-HV context.
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* MSR[EE] must be disabled.
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*/
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#define FIXUP_ENDIAN \
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#define FIXUP_ENDIAN \
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tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
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tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
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b 191f; /* Skip trampoline if endian is good */ \
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b 191f; /* Skip trampoline if endian is good */ \
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@ -789,6 +793,24 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
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.long 0x2400004c; /* rfid */ \
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.long 0x2400004c; /* rfid */ \
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191:
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191:
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/*
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* This version that may only be used with MSR[HV]=1
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* - Does not clear MSR[RI], so more robust.
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* - Slightly smaller and faster.
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*/
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#define FIXUP_ENDIAN_HV \
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tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \
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b 191f; /* Skip trampoline if endian is good */ \
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.long 0xa600607d; /* mfmsr r11 */ \
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.long 0x01006b69; /* xori r11,r11,1 */ \
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.long 0x05009f42; /* bcl 20,31,$+4 */ \
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.long 0xa602487d; /* mflr r10 */ \
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.long 0x14004a39; /* addi r10,r10,20 */ \
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.long 0xa64b5a7d; /* mthsrr0 r10 */ \
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.long 0xa64b7b7d; /* mthsrr1 r11 */ \
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.long 0x2402004c; /* hrfid */ \
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191:
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#endif /* !CONFIG_PPC_BOOK3E */
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#endif /* !CONFIG_PPC_BOOK3E */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLY__ */
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