MIPS: tlbex: Use GPR number macros
Use GPR number macros in uasm code generation parts to reduce code duplication. No functional change. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Jiaxun Yang
Thomas Bogendoerfer
parent
6aec8e0502
commit
8cc461b85f
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@ -34,6 +34,7 @@
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#include <asm/cpu-type.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/regdef.h>
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#include <asm/uasm.h>
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#include <asm/setup.h>
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#include <asm/tlbex.h>
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@ -277,10 +278,6 @@ static inline void dump_handler(const char *symbol, const void *start, const voi
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pr_debug("\tEND(%s)\n", symbol);
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}
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/* The only general purpose registers allowed in TLB handlers. */
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#define K0 26
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#define K1 27
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#ifdef CONFIG_64BIT
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# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
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#else
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@ -340,30 +337,30 @@ static struct work_registers build_get_work_registers(u32 **p)
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if (scratch_reg >= 0) {
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/* Save in CPU local C0_KScratch? */
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UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
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r.r1 = K0;
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r.r2 = K1;
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r.r3 = 1;
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r.r1 = GPR_K0;
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r.r2 = GPR_K1;
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r.r3 = GPR_AT;
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return r;
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}
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if (num_possible_cpus() > 1) {
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/* Get smp_processor_id */
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UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
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UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
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UASM_i_CPUID_MFC0(p, GPR_K0, SMP_CPUID_REG);
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UASM_i_SRL_SAFE(p, GPR_K0, GPR_K0, SMP_CPUID_REGSHIFT);
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/* handler_reg_save index in K0 */
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UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
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/* handler_reg_save index in GPR_K0 */
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UASM_i_SLL(p, GPR_K0, GPR_K0, ilog2(sizeof(struct tlb_reg_save)));
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UASM_i_LA(p, K1, (long)&handler_reg_save);
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UASM_i_ADDU(p, K0, K0, K1);
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UASM_i_LA(p, GPR_K1, (long)&handler_reg_save);
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UASM_i_ADDU(p, GPR_K0, GPR_K0, GPR_K1);
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} else {
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UASM_i_LA(p, K0, (long)&handler_reg_save);
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UASM_i_LA(p, GPR_K0, (long)&handler_reg_save);
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}
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/* K0 now points to save area, save $1 and $2 */
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UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
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UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
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/* GPR_K0 now points to save area, save $1 and $2 */
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UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), GPR_K0);
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UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), GPR_K0);
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r.r1 = K1;
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r.r1 = GPR_K1;
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r.r2 = 1;
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r.r3 = 2;
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return r;
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@ -376,9 +373,9 @@ static void build_restore_work_registers(u32 **p)
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UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
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return;
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}
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/* K0 already points to save area, restore $1 and $2 */
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UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
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UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
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/* GPR_K0 already points to save area, restore $1 and $2 */
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UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), GPR_K0);
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UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), GPR_K0);
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}
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#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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@ -397,22 +394,22 @@ static void build_r3000_tlb_refill_handler(void)
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memset(tlb_handler, 0, sizeof(tlb_handler));
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p = tlb_handler;
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uasm_i_mfc0(&p, K0, C0_BADVADDR);
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uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
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uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
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uasm_i_srl(&p, K0, K0, 22); /* load delay */
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uasm_i_sll(&p, K0, K0, 2);
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uasm_i_addu(&p, K1, K1, K0);
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uasm_i_mfc0(&p, K0, C0_CONTEXT);
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uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
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uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
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uasm_i_addu(&p, K1, K1, K0);
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uasm_i_lw(&p, K0, 0, K1);
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uasm_i_mfc0(&p, GPR_K0, C0_BADVADDR);
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uasm_i_lui(&p, GPR_K1, uasm_rel_hi(pgdc)); /* cp0 delay */
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uasm_i_lw(&p, GPR_K1, uasm_rel_lo(pgdc), GPR_K1);
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uasm_i_srl(&p, GPR_K0, GPR_K0, 22); /* load delay */
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uasm_i_sll(&p, GPR_K0, GPR_K0, 2);
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uasm_i_addu(&p, GPR_K1, GPR_K1, GPR_K0);
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uasm_i_mfc0(&p, GPR_K0, C0_CONTEXT);
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uasm_i_lw(&p, GPR_K1, 0, GPR_K1); /* cp0 delay */
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uasm_i_andi(&p, GPR_K0, GPR_K0, 0xffc); /* load delay */
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uasm_i_addu(&p, GPR_K1, GPR_K1, GPR_K0);
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uasm_i_lw(&p, GPR_K0, 0, GPR_K1);
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uasm_i_nop(&p); /* load delay */
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uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
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uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
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uasm_i_mtc0(&p, GPR_K0, C0_ENTRYLO0);
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uasm_i_mfc0(&p, GPR_K1, C0_EPC); /* cp0 delay */
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uasm_i_tlbwr(&p); /* cp0 delay */
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uasm_i_jr(&p, K1);
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uasm_i_jr(&p, GPR_K1);
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uasm_i_rfe(&p); /* branch delay */
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if (p > tlb_handler + 32)
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@ -1260,11 +1257,11 @@ static void build_r4000_tlb_refill_handler(void)
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memset(final_handler, 0, sizeof(final_handler));
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if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
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htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
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htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, GPR_K0, GPR_K1,
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scratch_reg);
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vmalloc_mode = refill_scratch;
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} else {
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htlb_info.huge_pte = K0;
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htlb_info.huge_pte = GPR_K0;
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htlb_info.restore_scratch = 0;
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htlb_info.need_reload_pte = true;
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vmalloc_mode = refill_noscratch;
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@ -1274,29 +1271,29 @@ static void build_r4000_tlb_refill_handler(void)
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if (bcm1250_m3_war()) {
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unsigned int segbits = 44;
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uasm_i_dmfc0(&p, K0, C0_BADVADDR);
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uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
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uasm_i_xor(&p, K0, K0, K1);
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uasm_i_dsrl_safe(&p, K1, K0, 62);
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uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
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uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
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uasm_i_or(&p, K0, K0, K1);
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uasm_il_bnez(&p, &r, K0, label_leave);
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uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR);
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uasm_i_dmfc0(&p, GPR_K1, C0_ENTRYHI);
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uasm_i_xor(&p, GPR_K0, GPR_K0, GPR_K1);
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uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, 62);
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uasm_i_dsrl_safe(&p, GPR_K0, GPR_K0, 12 + 1);
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uasm_i_dsll_safe(&p, GPR_K0, GPR_K0, 64 + 12 + 1 - segbits);
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uasm_i_or(&p, GPR_K0, GPR_K0, GPR_K1);
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uasm_il_bnez(&p, &r, GPR_K0, label_leave);
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/* No need for uasm_i_nop */
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}
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#ifdef CONFIG_64BIT
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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build_get_pmde64(&p, &l, &r, GPR_K0, GPR_K1); /* get pmd in GPR_K1 */
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#else
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build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
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build_get_pgde32(&p, GPR_K0, GPR_K1); /* get pgd in GPR_K1 */
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#endif
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#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
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build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
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build_is_huge_pte(&p, &r, GPR_K0, GPR_K1, label_tlb_huge_update);
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#endif
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build_get_ptep(&p, K0, K1);
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build_update_entries(&p, K0, K1);
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build_get_ptep(&p, GPR_K0, GPR_K1);
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build_update_entries(&p, GPR_K0, GPR_K1);
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build_tlb_write_entry(&p, &l, &r, tlb_random);
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uasm_l_leave(&l, p);
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uasm_i_eret(&p); /* return from trap */
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@ -1304,14 +1301,14 @@ static void build_r4000_tlb_refill_handler(void)
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#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
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uasm_l_tlb_huge_update(&l, p);
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if (htlb_info.need_reload_pte)
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UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
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build_huge_update_entries(&p, htlb_info.huge_pte, K1);
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build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
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UASM_i_LW(&p, htlb_info.huge_pte, 0, GPR_K1);
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build_huge_update_entries(&p, htlb_info.huge_pte, GPR_K1);
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build_huge_tlb_write_entry(&p, &l, &r, GPR_K0, tlb_random,
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htlb_info.restore_scratch);
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#endif
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#ifdef CONFIG_64BIT
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build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
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build_get_pgd_vmalloc64(&p, &l, &r, GPR_K0, GPR_K1, vmalloc_mode);
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#endif
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/*
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@ -1484,34 +1481,35 @@ static void build_loongson3_tlb_refill_handler(void)
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memset(tlb_handler, 0, sizeof(tlb_handler));
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if (check_for_high_segbits) {
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uasm_i_dmfc0(&p, K0, C0_BADVADDR);
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uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_TABLE_ORDER + PAGE_SHIFT - 3);
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uasm_il_beqz(&p, &r, K1, label_vmalloc);
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uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR);
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uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0,
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PGDIR_SHIFT + PGD_TABLE_ORDER + PAGE_SHIFT - 3);
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uasm_il_beqz(&p, &r, GPR_K1, label_vmalloc);
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uasm_i_nop(&p);
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uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
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uasm_il_bgez(&p, &r, GPR_K0, label_large_segbits_fault);
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uasm_i_nop(&p);
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uasm_l_vmalloc(&l, p);
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}
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uasm_i_dmfc0(&p, K1, C0_PGD);
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uasm_i_dmfc0(&p, GPR_K1, C0_PGD);
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uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
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uasm_i_lddir(&p, GPR_K0, GPR_K1, 3); /* global page dir */
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#ifndef __PAGETABLE_PMD_FOLDED
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uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
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uasm_i_lddir(&p, GPR_K1, GPR_K0, 1); /* middle page dir */
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#endif
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uasm_i_ldpte(&p, K1, 0); /* even */
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uasm_i_ldpte(&p, K1, 1); /* odd */
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uasm_i_ldpte(&p, GPR_K1, 0); /* even */
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uasm_i_ldpte(&p, GPR_K1, 1); /* odd */
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uasm_i_tlbwr(&p);
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/* restore page mask */
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if (PM_DEFAULT_MASK >> 16) {
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uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
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uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
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uasm_i_mtc0(&p, K0, C0_PAGEMASK);
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uasm_i_lui(&p, GPR_K0, PM_DEFAULT_MASK >> 16);
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uasm_i_ori(&p, GPR_K0, GPR_K0, PM_DEFAULT_MASK & 0xffff);
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uasm_i_mtc0(&p, GPR_K0, C0_PAGEMASK);
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} else if (PM_DEFAULT_MASK) {
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uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
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uasm_i_mtc0(&p, K0, C0_PAGEMASK);
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uasm_i_ori(&p, GPR_K0, 0, PM_DEFAULT_MASK);
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uasm_i_mtc0(&p, GPR_K0, C0_PAGEMASK);
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} else {
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uasm_i_mtc0(&p, 0, C0_PAGEMASK);
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}
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@ -1520,8 +1518,8 @@ static void build_loongson3_tlb_refill_handler(void)
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if (check_for_high_segbits) {
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uasm_l_large_segbits_fault(&l, p);
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UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
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uasm_i_jr(&p, K1);
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UASM_i_LA(&p, GPR_K1, (unsigned long)tlb_do_page_fault_0);
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uasm_i_jr(&p, GPR_K1);
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uasm_i_nop(&p);
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}
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@ -1887,11 +1885,11 @@ static void build_r3000_tlb_load_handler(void)
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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build_r3000_tlbchange_handler_head(&p, K0, K1);
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build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
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build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);
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build_pte_present(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbl);
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uasm_i_nop(&p); /* load delay */
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build_make_valid(&p, &r, K0, K1, -1);
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build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
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build_make_valid(&p, &r, GPR_K0, GPR_K1, -1);
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build_r3000_tlb_reload_write(&p, &l, &r, GPR_K0, GPR_K1);
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uasm_l_nopage_tlbl(&l, p);
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uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
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@ -1917,11 +1915,11 @@ static void build_r3000_tlb_store_handler(void)
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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build_r3000_tlbchange_handler_head(&p, K0, K1);
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build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
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build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);
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build_pte_writable(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbs);
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uasm_i_nop(&p); /* load delay */
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build_make_write(&p, &r, K0, K1, -1);
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build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
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build_make_write(&p, &r, GPR_K0, GPR_K1, -1);
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build_r3000_tlb_reload_write(&p, &l, &r, GPR_K0, GPR_K1);
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uasm_l_nopage_tlbs(&l, p);
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uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
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@ -1947,11 +1945,11 @@ static void build_r3000_tlb_modify_handler(void)
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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build_r3000_tlbchange_handler_head(&p, K0, K1);
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build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
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build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1);
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build_pte_modifiable(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbm);
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uasm_i_nop(&p); /* load delay */
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build_make_write(&p, &r, K0, K1, -1);
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build_r3000_pte_reload_tlbwi(&p, K0, K1);
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build_make_write(&p, &r, GPR_K0, GPR_K1, -1);
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build_r3000_pte_reload_tlbwi(&p, GPR_K0, GPR_K1);
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uasm_l_nopage_tlbm(&l, p);
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uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
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@ -2067,14 +2065,14 @@ static void build_r4000_tlb_load_handler(void)
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if (bcm1250_m3_war()) {
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unsigned int segbits = 44;
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uasm_i_dmfc0(&p, K0, C0_BADVADDR);
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uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
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uasm_i_xor(&p, K0, K0, K1);
|
||||
uasm_i_dsrl_safe(&p, K1, K0, 62);
|
||||
uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
|
||||
uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
|
||||
uasm_i_or(&p, K0, K0, K1);
|
||||
uasm_il_bnez(&p, &r, K0, label_leave);
|
||||
uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR);
|
||||
uasm_i_dmfc0(&p, GPR_K1, C0_ENTRYHI);
|
||||
uasm_i_xor(&p, GPR_K0, GPR_K0, GPR_K1);
|
||||
uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, 62);
|
||||
uasm_i_dsrl_safe(&p, GPR_K0, GPR_K0, 12 + 1);
|
||||
uasm_i_dsll_safe(&p, GPR_K0, GPR_K0, 64 + 12 + 1 - segbits);
|
||||
uasm_i_or(&p, GPR_K0, GPR_K0, GPR_K1);
|
||||
uasm_il_bnez(&p, &r, GPR_K0, label_leave);
|
||||
/* No need for uasm_i_nop */
|
||||
}
|
||||
|
||||
|
|
@ -2217,9 +2215,9 @@ static void build_r4000_tlb_load_handler(void)
|
|||
build_restore_work_registers(&p);
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
if ((unsigned long)tlb_do_page_fault_0 & 1) {
|
||||
uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
|
||||
uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
|
||||
uasm_i_jr(&p, K0);
|
||||
uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_0));
|
||||
uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_0));
|
||||
uasm_i_jr(&p, GPR_K0);
|
||||
} else
|
||||
#endif
|
||||
uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
|
||||
|
|
@ -2273,9 +2271,9 @@ static void build_r4000_tlb_store_handler(void)
|
|||
build_restore_work_registers(&p);
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
if ((unsigned long)tlb_do_page_fault_1 & 1) {
|
||||
uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
|
||||
uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
|
||||
uasm_i_jr(&p, K0);
|
||||
uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_1));
|
||||
uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_1));
|
||||
uasm_i_jr(&p, GPR_K0);
|
||||
} else
|
||||
#endif
|
||||
uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
|
||||
|
|
@ -2330,9 +2328,9 @@ static void build_r4000_tlb_modify_handler(void)
|
|||
build_restore_work_registers(&p);
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
if ((unsigned long)tlb_do_page_fault_1 & 1) {
|
||||
uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
|
||||
uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
|
||||
uasm_i_jr(&p, K0);
|
||||
uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_1));
|
||||
uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_1));
|
||||
uasm_i_jr(&p, GPR_K0);
|
||||
} else
|
||||
#endif
|
||||
uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
|
||||
|
|
|
|||
Loading…
Reference in New Issue