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phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC
UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-12-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -942,6 +942,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
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.serdes = sm8350_ufsphy_hs_b_serdes,
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.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
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},
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.tbls_hs_g4 = {
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.tx = sm8350_ufsphy_g4_tx,
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.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
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.rx = sm8350_ufsphy_g4_rx,
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.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
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.pcs = sm8350_ufsphy_g4_pcs,
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.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
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},
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.clk_list = sm8450_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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