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MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.

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Previously it was unconditionally used on all Sibyte family SOCs.  The
M3 bug has to be handled in the TLB exception handler which is extremly
performance sensitive, so this modification is expected to deliver around
2-3% performance improvment.  This is important as required changes to the
M3 workaround will make it more costly.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2010-03-23 00:02:43 +01:00
parent 9538ca636f
commit 8d9df29db2
2 changed files with 20 additions and 1 deletions
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6
arch/mips/include/asm/mach-sibyte/war.h
View file

@ -16,7 +16,11 @@
#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
#define BCM1250_M3_WAR 1
#ifndef __ASSEMBLY__
extern int sb1250_m3_workaround_needed(void);
#endif
#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
#define SIBYTE_1956_WAR 1
#else

15
arch/mips/sibyte/sb1250/setup.c
View file

@ -87,6 +87,21 @@ static int __init setup_bcm1250(void)
return ret;
}
int sb1250_m3_workaround_needed(void)
{
switch (soc_type) {
case K_SYS_SOC_TYPE_BCM1250:
case K_SYS_SOC_TYPE_BCM1250_ALT:
case K_SYS_SOC_TYPE_BCM1250_ALT2:
case K_SYS_SOC_TYPE_BCM1125:
case K_SYS_SOC_TYPE_BCM1125H:
return soc_pass < K_SYS_REVISION_BCM1250_C0;
default:
return 0;
}
}
static int __init setup_bcm112x(void)
{
int ret = 0;