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ARM: OMAP3: Fix HW SAVEANDRESTORE shift define
The OMAP3430ES2_SAVEANDRESTORE_SHIFT macro is used by powerdomain code in "1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT" manner, but the definition was also (1 << 4), meaning we actually modified bit 16. So the definition needs to be 4. This fixes also a cold reset HW bug in OMAP3430 ES3.x where some of the efuse bits are not isolated during wake-up from off mode. This can cause randomish cold resets with off mode. Enabling the USBTLL hardware SAVEANDRESTORE causes the core power up assert to be delayed in a way that we will not get faulty values when boot ROM is reading the unisolated registers. Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -409,7 +409,7 @@
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/* PM_PREPWSTST_CAM specific bits */
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/* PM_PWSTCTRL_USBHOST specific bits */
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#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4)
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#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
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/* RM_RSTST_PER specific bits */
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