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drm/amd/display: Allow 16 max_slices for DP2 DSC

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Enable 12 and 16 max_slices for DP2 DSC

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Fangzhi Zuo 2023-10-18 09:38:33 -04:00 committed by Alex Deucher
parent 92e11f0159
commit 8df0d7d33a
3 changed files with 22 additions and 1 deletions
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10
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
View file

@ -137,7 +137,15 @@ void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;
}
// TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM.
/* For pixel clock bigger than a single-pipe limit needing four engines ODM 4:1, which then quardruples our
* throughput and number of slices
*/
if (pixel_clock_100Hz > DCN20_MAX_PIXEL_CLOCK_Mhz*10000*2) {
dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;
dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;
dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 4;
}
dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
}

11
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
View file

@ -512,6 +512,11 @@ static bool intersect_dsc_caps(
dsc_sink_caps->slice_caps1.bits.NUM_SLICES_4 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;
dsc_common_caps->slice_caps.bits.NUM_SLICES_8 =
dsc_sink_caps->slice_caps1.bits.NUM_SLICES_8 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;
dsc_common_caps->slice_caps.bits.NUM_SLICES_12 =
dsc_sink_caps->slice_caps1.bits.NUM_SLICES_12 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_12;
dsc_common_caps->slice_caps.bits.NUM_SLICES_16 =
dsc_sink_caps->slice_caps2.bits.NUM_SLICES_16 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_16;
if (!dsc_common_caps->slice_caps.raw)
return false;
@ -703,6 +708,12 @@ static int get_available_dsc_slices(union dsc_enc_slice_caps slice_caps, int *av
if (slice_caps.bits.NUM_SLICES_8)
available_slices[idx++] = 8;
if (slice_caps.bits.NUM_SLICES_12)
available_slices[idx++] = 12;
if (slice_caps.bits.NUM_SLICES_16)
available_slices[idx++] = 16;
return idx;
}

2
drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
View file

@ -76,6 +76,8 @@ union dsc_enc_slice_caps {
uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
uint8_t NUM_SLICES_4 : 1;
uint8_t NUM_SLICES_8 : 1;
uint8_t NUM_SLICES_12 : 1;
uint8_t NUM_SLICES_16 : 1;
} bits;
uint8_t raw;
};